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Ogic Tyle: Prof. Kaushik Roy at Purdue Univ

This document summarizes three logic styles: 1) DCVSPG reduces area and power by using a pass gate but has limited logical depth and differential noise immunity. 2) SRPL has low stand-by power, high design margin and process tolerance, and less delay through sense-amp action. 3) DPL is high speed by avoiding buffers and VT drops, using a redundant device structure.

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Dr. Sampatrao L Pinjare
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30 views10 pages

Ogic Tyle: Prof. Kaushik Roy at Purdue Univ

This document summarizes three logic styles: 1) DCVSPG reduces area and power by using a pass gate but has limited logical depth and differential noise immunity. 2) SRPL has low stand-by power, high design margin and process tolerance, and less delay through sense-amp action. 3) DPL is high speed by avoiding buffers and VT drops, using a redundant device structure.

Uploaded by

Dr. Sampatrao L Pinjare
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LOGIC STYLE

Prof. Kaushik Roy


@ Purdue Univ.
DCVS Logic With Pass Gate (DCVSPG)
VDD VDD
1 2

Q Q’
0 VDD-VT VDD

3
B’ 5
4
B 6

A A’ A’ A

- Full Swing - Limited logical depth


- Area, power reduction - Body effect
- Differential noise immunity
Swing-Restored Pass Gate Logic (SRPL)
VDD VDD

Q
Q’

3
B’ 5
4
B 6

A A’ A’ A

- Low stand-by power


- High design margin, process tolerance
- Less delay via sense-amp action
Double Pass-Transistor Logic (DPL)
Q’ Q

A’

B’

VDD B’ VDD A B GND A’ GND

- High Speed
- Avoids buffer
- Avoids VT drop
- Redundant device structure

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