4.

Questions on Arithmetic Circuits

Arithmetic Operation Basics - Digital Circuits Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Introduction of Arithmetic Operation”.

1. The basic building blocks of the arithmetic unit in a digital computers are
a) Subtractors
b) Adders
c) Multiplexer
d) None of the Mentioned
View Answer

Answer: b
Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders.
Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade.
By controlling the data inputs to the parallel adder, it is possible to obtain different types of
arithmetic operations.

2. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: a
Explanation: A digital system consists of two types of circuits and these are combinational and
sequential logic circuit.

3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) None of the Mentioned
View Answer

Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values
at that time.
4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Present input values
d) Both past output and present input
View Answer

Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as
well as past output values.

5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) None of the Mentioned
View Answer

Answer: c
Explanation: The given arrangement in option c is the right sequence for the designing of the
combinational circuits.

6. All logic operations can be obtained by means of

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) AND, OR and NOT operations
View Answer

Answer: d
Explanation: Since, the logic gates AND, OR and NOT are called as universal logic gates. It
means that any operations can be obtained by implementation of these gates.

7. The design of an ALU is based on

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) None of the Mentioned
View Answer
Answer: b
Explanation: The design of an ALU is based on combinational logic. Because the unit has a
regular pattern, it can be broken into identical stages connected in cascade through carries.

8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a
possible _____ result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
View Answer

Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry
and a possible zero result.

9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest
are the sign of the result, a zero indication and
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) None of the Mentioned
View Answer

Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions
of interest are the sign of the result, a zero indication and an overflow condition.

10. The flag bits in an ALU is defined as

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
d) All of the Mentioned
View Answer

Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag
bits.

Half Adder & Full Adder - Digital Circuits Questions and Answers -
Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Half Adder & Full Adder”.
1. In parts of the processor, adders are used to calculate
a) Addresses
b) Table indices
c) Increment and decrement operators
d) All of the Mentioned
View Answer

Answer: d
Explanation: In parts of the processor, adders are used to calculate addresses, table indices,
increment and decrement operators, and similar operations.

2. Total number of inputs in a half adder is

a) 2
b) 3
c) 4
d) 1
View Answer

Answer: a
Explanation: Total number of inputs in a half adder is two. Since, an EXOR gates has 2 inputs
and carry is connected with the input of EXOR gates.

3. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
View Answer

Answer: b
Explanation: In addition, carry is obtained. For example: 1 0 1 + 1 1 1 = 1 0 0; in this example
carry is obtained after 1st addition (i.e. 1 + 1 = 1 0).

4. If A and B are the inputs of a half adder, the sum is given by

a) A AND B
b) A OR B
c) A XOR B
d) A EXOR B
View Answer

Answer: c
Explanation: If A and B are the inputs of a half adder, the sum is given by A XOR B.

5. If A and B are the inputs of a half adder, the carry is given by

a) A AND B
b) A OR B
c) A XOR B
d) A EXOR B
View Answer

Answer: a
Explanation: If A and B are the inputs of a half adder, the carry is given by: A(AND)B.

6. Half-adders have a major limitation in that they cannot

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) None of the Mentioned
View Answer

Answer: c
Explanation: Half-adders have a major limitation in that they cannot accept a carry bit from a
previous stage, meaning that they cannot be chained together to add multi-bit numbers. However,
the two output bits of a half-adder can also represent the result A+B=3 as sum and carry both
being high.

7. The difference between half adder and full adder is

a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
d) All of the Mentioned
View Answer

Answer: c
Explanation: Half adder has two inputs while full adder has three outputs; this is the difference
between them.

8. If A, B and C are the inputs of a full adder then the sum is given by
a) A AND B AND C
b) A OR B AND C
c) A OR B OR C
d) A XOR B XOR C
View Answer

Answer: c
Explanation: If A, B and C are the inputs of a full adder then the sum is given by A OR B OR C.

9. If A, B and C are the inputs of a full adder then the carry is given by
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
View Answer

Answer: a
Explanation: If A, B and C are the inputs of a full adder then the carry is given by A AND B OR
(A OR B) AND C.

10. How many AND, OR and EXOR gates are required for the configuration of full adder
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
View Answer

Answer: b
Explanation: There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full
adder.

Half & Full Subtractor - Digital Circuits Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Half & Full Subtractor”.

1. Half subtractor is used to perform subtraction of

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
View Answer

Answer: a
Explanation: Half subtractor is a combinational circuit which is used to perform subtraction of
two bits, namely minuend and subtrahend.

2. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.

a) Carry
b) Borrow
c) Not possible
d) None of the Mentioned
View Answer
Answer: b
Explanation: For subtracting 1 from 0, we use to take a borrow from neighbouring bits because
carry is taken into consideration during addition process.

3. How many outputs are required for the implementation of a subtractor?

a) 1
b) 2
c) 3
d) 4
View Answer

Answer: b
Explanation: There are two outputs required for the implementation of a subtractor. One for the
output and another for borrow.

4. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
View Answer

Answer: a
Explanation: The output for A = B will be 0. If A = B, it means that A = B = 0 or A = B = 1. In
both of the situation subtractor gives 0 as the output.

5. Let A and B is the input of a subtractor then the output will be

a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
View Answer

Answer: a
Explanation: Since, the output of a subtractor is given by AB’ + BA’ and this is the output of a
XOR gate. So, the final output is AB’ + BA’.

6. Let A and B is the input of a subtractor then the borrow will be

a) A * B’
b) A’ * B
c) A OR B
d) A AND B
View Answer
Answer: b
Explanation: The borrow of a subtractor is received through NAND gate whose one input is
inverted. On that basis the borrow will be (A’ * B).

7. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) None of the Mentioned
View Answer

Answer: c
Explanation: Minuend and subtrahend are the two bits of input of a subtractor. If A and B are the
two inputs of a subtractor then A is called minuend and B as subtrahend.

8. Full subtractor is used to perform subtraction of

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
View Answer

Answer: b
Explanation: Full subtractor is used to perform subtraction of 3 bits, namely minuend bit,
subtrahend bit and borrow from the previous stage.

9. The full subtractor can be implemented using

a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) None of the Mentioned
View Answer

Answer: b
Explanation: The full subtractor can be implemented using two half subtractors and an OR gate.

10. The output of a subtractor is given by (if A, B and X are the inputs)
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
View Answer

Answer: b
Explanation: The output of a subtractor is given by (if A, B and X are the inputs) A XOR B XOR
X.
11. The output of a full subtractor is same as
a) Half adder
b) Full adder
c) Half subtractor
d) None of the Mentioned
View Answer

Answer: b
Explanation: The output of a full adder and a full subtractor are same. If A, B and C are the input
of a full adder and a full subtractor then the output will be given by (A XOR B XOR C).

Combinational Circuits Design Procedure Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Procedure For The Design of Combinational Circuits”.

1. The basic building blocks of the arithmetic unit in a digital computers are
a) Subtractors
b) Adders
c) Multiplexer
d) None of the Mentioned
View Answer

Answer: b
Explanation: The basic building blocks of the arithmetic unit in a digital computers are adders.
Since, a parallel adder is constructed with a number of full-adder circuits connected in cascade.
By controlling the data inputs to the parallel adder, it is possible to obtain different types of
arithmetic operations.

2. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
View Answer

Answer: a
Explanation: A digital system consists of two types of circuits and these are combinational and
sequential logic circuit.

3. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) None of the Mentioned
View Answer

Answer: c
Explanation: In a combinational circuit, the output at any time depends only on the input values
at that time.

4. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Present input values
d) None of the Mentioned
View Answer

Answer: c
Explanation: In a sequential circuit, the output at any time depends on the present input values as
well as past output values.

5. Procedure for the design of combinational circuits are:

A. From the word description of the problem, identify the inputs and outputs and draw a block
diagram.
B. Draw the truth table such that it completely describes the operation of the circuit for different
combinations of inputs.
C. Simplify the switching expression(s) for the output(s).
D. Implement the simplified expression using logic gates.
E. Write down the switching expression(s) for the output(s).
a) B, C, D, E, A
b) A, D, E, B, C
c) A, B, E, C, D
d) None of the Mentioned
View Answer

Answer: c
Explanation: The given arrangement in option c is the right sequence for the designing of the
combinational circuits.

6. All logic operations can be obtained by means of

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) AND, OR and NOT operations
View Answer
Answer: d
Explanation: Since, the logic gates AND, OR and NOT are called as universal logic gates. It
means that any operations can be obtained by implementation of these gates.

7. The design of an ALU is based on

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) None of the Mentioned
View Answer

Answer: b
Explanation: The design of an ALU is based on combinational logic. Because the unit has a
regular pattern, it can be broken into identical stages connected in cascade through carries.

8. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a
possible _____ result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
View Answer

Answer: d
Explanation: If the two numbers are unsigned, the bit conditions of interest are the output carry
and a possible zero result.

9. If the two numbers include a sign bit in the highest order position, the bit conditions of interest
are the sign of the result, a zero indication and
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) None of the Mentioned
View Answer

Answer: c
Explanation: If the two numbers include a sign bit in the highest order position, the bit conditions
of interest are the sign of the result, a zero indication and an overflow condition.

10. The flag bits in an ALU is defined as

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
d) All of the Mentioned
View Answer
Answer: b
Explanation: In an ALU, status bit conditions are sometimes called condition code bits or flag
bits.

K-Map Simplification - Digital Circuits Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “K-Map Simplification”.

1. Which statement below best describes a Karnaugh map?

a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
View Answer

Answer: a
Explanation: K-map is simply a rearranged truth table.

2. Which of the examples below expresses the commutative law of multiplication?

a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
View Answer

Answer: d
Explanation: The cumulative law of multiplication is (A * B) = (B * A).

3. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?

a) NAND
b) NOR
c) AND
d) OR
View Answer

Answer: a
Explanation: If A and B are the input for AND gate the output is obtained as AB and after
inversion we get (AB)’, which is the expression of NAND gate.

4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND
gate is referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
View Answer

Answer: b
Explanation: DeMorgan’s Law: ~(P^Q) <=> ~Pv~Q
~(PvQ) <=> ~P^~Q.

5. The systematic reduction of logic circuits is accomplished by:

a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
View Answer

Answer: c
Explanation: The systematic reduction of logic circuits is accomplished by using boolean
algebra.

6. Each “1” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
View Answer

Answer: a
Explanation: Each “1” entry in a K-map square represents a HIGH for each input truth table
condition that produces a HIGH output.

7. Each “0” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
View Answer

Answer: a
Explanation: Each “0” entry in a K-map square represents a LOW output for all possible HIGH
input conditions.

8. Which of the following statements accurately represents the two BEST methods of logic
circuit simplification?
a) Boolean algebra and Karnaugh mapping
b) Karnaugh mapping and circuit waveform analysis
c) Actual circuit trial and error evaluation and waveform analysis
d) Boolean algebra and actual circuit trial and error evaluation
View Answer

Answer: c
Explanation: The two BEST methods of logic circuit simplification Boolean algebra and
Karnaugh mapping.

9. Looping on a K-map always results in the elimination of

a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
View Answer

Answer: c
Explanation: Looping on a K-map always results in the elimination of variables within the loop
that appear in both complemented and uncomplemented form.

10. Which of the following expressions is in the sum-of-products form?

a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
View Answer

Answer: d
Explanation: Sum of product means that the number is multiplied firstly and then it is added: A *
B + C * D.

11. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
View Answer

Answer: a
Explanation: An important feature of the sum-of-products form of expressions in the given
option is that all logic circuits are reduced to nothing more than simple AND and OR operations.

12. Which of the following expressions is in the product-of-sums form?

a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
View Answer

Answer:
Explanation: (A + B)(C + D) represents the product-of-sums form.

Controlled Inverter - Digital Circuits Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Controlled Inverter”.

1. Controlled inverter is also known as

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) None of the Mentioned
View Answer

Answer: c
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well.

2. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) None of the Mentioned
View Answer

Answer: c
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different.
When one input is true, the output is the inversion of the other. When one input is false, the
output is the non-inversion of the other.

3. Controlled buffers can be useful

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
d) All of the Mentioned
View Answer

Answer: a
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose
value should match the output of one of several components. By placing a controlled buffer
between each component output and the bus, you can control whether that component’s output is
fed onto the bus or not.

4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
View Answer

Answer: a
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are
same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs
HIGH or both inputs are LOW.

5. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
View Answer

Answer: d
Explanation: Documentation is a set of documents provided on paper, or online, or on digital or
analog media, such as audio tape or CDs. So, for the implementation of micro function good
documentation is necessary.

6. What is the major difference between half-adders and full-adders?

a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
View Answer

Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number
like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is
1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second
bits addition of the number. So, half adders are useless. But in full adders, one more carry input
is present, so that, if carry of one stage is present, it can be added with the next stage as it is done
in normal addition. So, therefore, full adders have a carry input capability.

7. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
View Answer

Answer: a
Explanation: The binary subtraction of 0 – 0 = 0.

8. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
View Answer

Answer: b
Explanation: There are 4 binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.

9. When performing subtraction by addition in the 2’s-complement system:

a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
View Answer

Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the
minuend is left in its original form and the subtrahend is changed to its 2’s-complement.

10. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
View Answer

Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder.

11. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
View Answer

Answer: d
Explanation: By using maximum of two half adders we can make a full adder.
12. The selector inputs to an arithmetic/logic unit (ALU) determine the:
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
View Answer

Answer: b
Explanation: An ALU performs basic arithmetic and logic operations. Examples of arithmetic
operations are addition, subtraction, multiplication, and division. Examples of logic operations
are comparisons of values such as NOT, AND and OR.

4-Bit Parallel Adder/Subtractor - Digital Circuits Questions and Answers

- Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “4-Bit Parallel Adder/Subtractor – 1”.

1. Controlled inverter is also known as

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) None of the Mentioned
View Answer

Answer: c
Explanation: Controlled inverter is also known as controlled buffer and NOT gate as well.

2. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) None of the Mentioned
View Answer

Answer: c
Explanation: The XOR (Exclusive Or) gate has a true output when the two inputs are different.
When one input is true, the output is the inversion of the other. When one input is false, the
output is the non-inversion of the other.

3. Controlled buffers can be useful

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
d) All of the Mentioned
View Answer

Answer: a
Explanation: Controlled buffers can be useful when you have a wire (often called a bus) whose
value should match the output of one of several components. By placing a controlled buffer
between each component output and the bus, you can control whether that component’s output is
fed onto the bus or not.

4. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is
a) Ex-NOR gate
b) OR gate
c) Ex-OR gate
d) NAND gate
View Answer

Answer: a
Explanation: EX-OR gate gives 1 if both inputs are different means 0 or 1 and gives 0 if both are
same and EX-NOR is opposite of EX-OR gate, so it provides a HIGH output for both inputs
HIGH or both inputs are LOW.

5. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
View Answer

Answer: d
Explanation: Documentation is a set of documents provided on paper, or online, or on digital or
analog media, such as audio tape or CDs. So, for the implementation of micro function good
documentation is necessary.

6. What is the major difference between half-adders and full-adders?

a) Full-adders are made up of two half-adders
b) Full adders can handle double-digit numbers
c) Full adders have a carry input capability
d) Half adders can handle only single-digit numbers
View Answer

Answer: c
Explanation: Half adders have only two inputs A and B. When we add two 4 bit binary number
like 0001 and 0011, then half adder can not be used because if the first bit of both the numbers is
1, then the sum would be 0 and carry would be 1. But this carry can not be added with the second
bits addition of the number. So, half adders are useless. But in full adders, one more carry input
is present, so that, if carry of one stage is present, it can be added with the next stage as it is done
in normal addition. So, therefore, full adders have a carry input capability.

7. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
View Answer

Answer: a
Explanation: The binary subtraction of 0 – 0 = 0.

8. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
View Answer

Answer: b
Explanation: There are 4 binary subtraction operations (0-0, 1-0, 0-1, 1-1) are possible.

9. When performing subtraction by addition in the 2’s-complement system:

a) The minuend and the subtrahend are both changed to the 2’s-complement
b) The minuend is changed to 2’s-complement and the subtrahend is left in its original form
c) The minuend is left in its original form and the subtrahend is changed to its 2’s-complement
d) The minuend and subtrahend are both left in their original form
View Answer

Answer: c
Explanation: When performing subtraction by addition in the 2’s-complement system, the
minuend is left in its original form and the subtrahend is changed to its 2’s-complement.

10. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
View Answer

Answer: b
Explanation: There are two types of adder circuits: half-adder and full-adder.

11. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
View Answer

Answer: d
Explanation: By using maximum of two half adders we can make a full adder.

12. The selector inputs to an arithmetic/logic unit (ALU) determine the:

a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
View Answer

Answer: b
Explanation: An ALU performs basic arithmetic and logic operations. Examples of arithmetic
operations are addition, subtraction, multiplication, and division. Examples of logic operations
are comparisons of values such as NOT, AND and OR.

Digital Electronic Circuits Test - Sanfoundry

by Manish

This set of Digital Electronic/Circuits Test focuses on “4-Bit Parallel Adder/Subtractor – 2”.

1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the result is:
a) The same as if the carry-in is tied LOW since the least significant carry-in is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored
View Answer

Answer: c
Explanation: For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, one will be
added to the final result as a result because carry-in gives output as 1.

2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which

a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
View Answer

Answer: b
Explanation: A carry-lookahead adder (CLA) is a type of adder used in digital logic. A carry-
lookahead adder improves speed by reducing the amount of time required to determine carry
bits.

3. One way to make a four-bit adder to perform subtraction is by:

a) Inverting the output
b) Inverting the carry-in
c) Inverting the B inputs
d) Grounding the B inputs
View Answer

Answer: c
Explanation: Since, a four bit adder has four A, four B and a carry at the input end. So, for
subtraction to be performed, all the Bs terminal should be inverted.

4. What distinguishes the look-ahead-carry adder?

a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
View Answer

Answer: c
Explanation: It is slower than the ripple-carry adder. It is easier to implement logically than a full
adder. It is faster than a ripple-carry adder.

5. Carry lookahead logic uses the concepts of

a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
View Answer

Answer: c
Explanation: Carry lookahead logic uses the concepts of generating and propagating carries.
Although in the context of a carry lookahead adder, it is most natural to think of generating and
propagating in the context of binary addition, the concepts can be used more generally than this.

6. What is one disadvantage of the ripple-carry adder?

a) The interconnections are more complex
b) More stages are required to a full adder
c) It is slow due to propagation time
d) All of the Mentioned
View Answer

Answer: c
Explanation: The main disadvantage in using this type of adders is that the time delay increases
as for each adder to add the carry should be generated in the previous adder, and for that to add
the carry from the one before is required.

7. The carry propagation delay in 4-bit full-adder circuits:

a) Is cumulative for each stage and limits the speed at which arithmetic operations are performed
b) Is normally not a consideration because the delays are usually in the nanosecond range
c) Decreases in direct ratio to the total number of full-adder stages
d) Increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting
the speed of arithmetic operations
View Answer

Answer: a
Explanation: The carry propagation delay in 4-bit full-adder circuits is cumulative for each stage
and limits the speed at which arithmetic operations are performed.

8. What is Manchester carry chain?

a) Is a chain of controlled inverter
b) Variation of a carry-lookahead adder
c) Variation of a full-adder
d) None of the Mentioned
View Answer

Answer: b
Explanation: The Manchester carry chain is a variation of the carry-lookahead adder that uses
shared logic to lower the transistor count.

9. The main disadvantage of Manchester carry chain is

a) Ripple factor
b) Propagation delay
c) Capacitive load
d) Both propagation delay and capacitive load
View Answer

Answer: d
Explanation: One of the major downsides of the Manchester carry chain is that the capacitive
load of all of these outputs, together with the resistance of the transistors causes the propagation
delay to increase much more quickly than a regular carry lookahead.

10. The summing outputs of a half or full-adder are designated by which Greek symbol?
a) Omega
b) Theta
c) Lambda
d) Sigma
View Answer
Answer: d
Explanation: The summing outputs of a half or full-adder are designated by “sigma” which is a
Greek symbol.

11. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
a) To decrease the cost
b) To make it smaller
c) To slow down the circuit
d) To speed up the circuit
View Answer

Answer: d
Explanation: Since, it is easy to implement and can be implemented on any types of chip and
have capability to reduce propagation delay, which helps in increasing the speed of 7483 4-bit
full-adder.

Fast & Serial Adder - Digital Circuits Questions and Answers -

Sanfoundry
by Manish

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses
on “Fast Adder & Serial Adder – 1”.

1. The inverter can be produced with how many NAND gates?

a) 2
b) 1
c) 3
d) 4
View Answer

Answer: b
Explanation: The inverter can be produced with the help of single NAND gate, because we can
combine both the inputs of the NAND gate together and make it single. It works as an inverter.

2. One positive pulse with tw = 75 µs is applied to one of the inputs of an exclusive-OR circuit.
A second positive pulse with tw = 15 µs is applied to the other input beginning 20 µs after the
leading edge of the first pulse. Which statement describes the output’s relation with the inputs?
a) The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with a separation of 15 s
between the pulses
b) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with a separation of 40 s
between the pulses
c) The exclusive-OR output is a 15 s pulse followed by a 40 s pulse
d) The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, followed by a 40 s pulse
View Answer
Answer: d
Explanation: When both the input pulses are high or low X-OR output is low. But when one of
the input is high and another is low or vice-versa, output is high. In this problem for the first
20uS one input is high and another is low. So, obviously output is a high. for next 15uS both the
input is high so output is low and for remaining 40uS(75-20-15) first input is still high and
second one is low so output is high.

3. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
a) 2
b) 3
c) 4
d) 5
View Answer

Answer: a
Explanation: Since, in the given expression two inputs are complemented. So, we require two
NOT gate at the input.

4. The carry look ahead adder is based on the principle of looking at the lower order bits of
________ and ________ if a high order carry is generated.
a) Addend, minuend
b) Minuend, subtrahend
c) Addend, minuend
d) Augend, addend
View Answer

Answer: d
Explanation: The carry look ahead adder is based on the principle of looking at the lower order
bits of the augend and addend if a high order carry is generated.

5. What are carry generate combinations?

a) If all the input are same then a carry is generated
b) If all of the output are independent of the inputs
c) If all of the input are dependent on the output
d) None of the Mentioned
View Answer

Answer: b
Explanation: If the input is either 0, 0, 0 or 0, 0, 1 then the output will be 0 (i.e. independent of
input) and if the input is either 1, 1, 0 or 1, 1, 1 then the output is 1 (i.e independent of input).
Such situation is known as carry generate combinations.

6. In serial addition, the addition is carried out

a) 3 bit per second
b) Byte by byte
c) Bit by bit
d) None of the Mentioned
View Answer

Answer: c
Explanation: In serial addition, the addition is carried out bit by bit.

7. How many shift registers are used in a 4 bit serial adder?

a) 4
b) 3
c) 2
d) 5
View Answer

Answer: c
Explanation: There are two shift registers are used in a 4-bit serial adder, which is used to store
the numbers to be added serially.

8. A D flip-flop is used in a 4-bit serial adder, why?

a) It is used to invert the input of the full adder
b) It is used to store the output of the full adder
c) It is used to store the carry output of the full adder
d) None of the Mentioned
View Answer

Answer: c
Explanation: The D flip-flop, i.e. carry flip-flop, is used to store the carry output of the full adder
so that it can be added to the next significant position of the numbers in the registers.

9. What is ripple carry adder?

a) The carry output of the lower order stage is connected to the carry input of the next higher
order stage
b) The carry input of the lower order stage is connected to the carry output of the next higher
order stage
c) The carry output of the higher order stage is connected to the carry input of the next lower
order stage
d) None of the Mentioned
View Answer

Answer: a
Explanation: When the carry output of the lower order stage is connected to the carry input of the
next higher order stage, such types of connection is called ripple carry adder in a 4-bit binary
parallel adder.

10. If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the borrow
output will be:
a) 0
b) 1
c) Not possible
d) None of the Mentioned
View Answer

Answer: b
Explanation: If minuend = 0, subtrahend = 1 and borrow input = 1 in a full subtractor then the
borrow output will be 1. Because on subtracting 0 and 1, one borrow is taken and it proceeds till
the next step (i.e 0 – 1 – 1 = 0, borrow = 1).

Digital Electronic Circuits Quiz - Sanfoundry

by Manish

This set of Digital Electronic/Circuits Quiz focuses on “Fast Adder & Serial Adder – 2”.

1. A serial subtractor can be obtained by converting the serial adder by using the
a) 1’s complement system
b) 2’s complement system
c) 10’s complement
d) None of the Mentioned
View Answer

Answer: b
Explanation: A serial subtractor can be obtained by converting the serial adder by using the 2’s
complement system.

2. The hexadecimal number (4B)16 is transmitted as an 8-bit word in parallel. What is the time
required for this transmission if the clock frequency is 2.25 MHz?
a) 444 ns
b) 444 s
c) 3.55 s
d) 3.55 ms
View Answer

Answer: a
Explanation: Because the clock pulse of 4-bit transmit the data of 8-bit word in parallel mode
and this transmission done at 2.25 MHz frequency. We know that: f=1/t and we can find the time
required for this transmission by the clock pulse.

3. Internally, a computer’s binary data are always transmitted on parallel channels which is
commonly referred to as the
a) Parallel bus
b) Serial bus
c) Data bus
d) Memory bus
View Answer

Answer: c
Explanation: A computer’s data is always in the binary form which is stored in the bus that
transmit the data on any channels. It doesn’t matter that it’s in parallel or serial.

4. What is the frequency of a clock waveform if the period of that waveform is 1.25sec?
a) 8 kHz
b) 0.8 kHz
c) 0.8 MHz
d) 8 MHz
View Answer

Answer: c
Explanation: By using the formula of frequency, we can find the frequency of clock waveform.
Time period(t) of the waveform is = 1.25microseconds
f=1/t
Where ‘t’ is the time taken by the clock waveform;
f=(1/1.25)
so, f=0.8 MHz.

5. Why is parallel data transmission preferred over serial data transmission for most
applications?
a) It is much slower
b) It is cheaper
c) More people use it
d) It is much faster
View Answer

Answer: d
Explanation: Parallel data transmission preferred over serial data transmission for most
applications because it is much faster.

6. With surface-mount technology (SMT), the devices should:

a) Utilize transistor outline connections
b) Mount directly
c) Have parallel connecting pins
d) Require holes and pads
View Answer

Answer: b
Explanation: Surface-mount technology (SMT) is a method for producing electronic circuits in
which the components are mounted or placed directly onto the surface of printed circuit boards
(PCBs). An electronic device so made is called a surface-mount device (SMD). In the industry it
has largely replaced the through-hole technology construction method of fitting components with
wire leads into holes in the circuit board. Both technologies can be used on the same board for
components not suited to surface mounting such as large transformers and heat-sinked power
semiconductors.

7. In the most applications, transistor switches used in place of relays?

a) They consume less power
b) They are faster
c) They are quieter and smaller
d) All of the Mentioned
View Answer

Answer: d
Explanation: Transistors are of less consuming power, faster, quieter, smaller and its
implementation is too easy. So, in most applications transistor switches are more preferred.

8. What can a relay provide between the triggering source and the output that semiconductor
switching devices cannot?
a) Total isolation
b) Faster
c) Higher current rating
d) Total isolation and higher current rating
View Answer

Answer: d
Explanation: A relay provide total isolation and higher current rating between the triggering
source and the output that semiconductor switching devices cannot provide.

9. The serial format for transmitting binary information uses

a) A single conductor
b) Multiple conductors
c) Infrared technology
d) Fiber-optic
View Answer

Answer: a
Explanation: A conductor accepts the whole data and arrange it in a serial manner, which is
transmitted as binary information.

10. Serial communication can be sped up by

a) Using silver or gold conductors instead of copper
b) Using high-speed clock signals
c) Adjusting the duty cycle of the binary information
d) Using silver or gold conductors instead of copper and high-speed clock signals
View Answer
Answer: b
Explanation: For any serial data transmission there is required of continuously data supply and if
the input supply (i.e. high speed clock signals) in high amount the speed of serial communication
can be increased.

Digital Circuits Questions and Answers – BCD Adder

This set of Digital Electronics/Circuits Multiple Choice Questions & Answers (MCQs) focuses on
“BCD Adder”.

1. The decimal number system represent the decimal number in the form of
a) Hexadecimal
b) Binary coded
c) Octal
d) Decimal
View Answer

Answer: b
Explanation: Binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where
each decimal digit is represented by a fixed number of bits, usually four or eight.

2. 2^9 input circuit will have total of

a) 32 entries
b) 128 entries
c) 256 entries
d) 512 entries
View Answer

Answer: d
Explanation: 2^9 input circuit would have 512(2*2*2*2*2*2*2*2*2 = 512) entries.

3. BCD adder can be constructed with 3 IC packages each of

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
View Answer

Answer: c
Explanation: BCD adder can be constructed with 3 IC packages. Each of 4-bit adders is an
MSI(Medium scale Integration) function and 3 gates for the correction logic need one SSI package.

4. The output sum of two decimal digits can be represented in

a) Gray Code
b) Excess-3
c) BCD
d) Hexadecimal
View Answer
Answer: c
Explanation: The output sum of two decimal digits can be represented in BCD(Binary-coded
decimal).

5. The addition of two decimal digits in BCD can be done through

a) BCD adder
b) Full adder
c) Ripple carry adder
d) Carry look ahead
View Answer

Answer: a
Explanation: The addition of two decimal digits in BCD can be done through BCD adder. Every input
inserted, in addition by the user converted into binary and then proceed for the addition.

6. 3 bits full adder contains

a) 3 combinational inputs
b) 4 combinational inputs
c) 6 combinational inputs
d) 8 combinational inputs
View Answer

Answer: d
Explanation: 3 bits full adder contains 8 combinational inputs.

7. The simplified expression of full adder carry is

a) c = xy+xz+yz
b) c = xy+xz
c) c = xy+yz
d) c = x+y+z
View Answer

Answer: a
Explanation: The simplified expression of full adder carry is c = xy+xz+yz.

8. Complement of F’ gives back

a) F’
b) F
c) FF
d) undefined variable
View Answer

Answer: b
Explanation: Complement means inversion. So, complement of F’ gives back F.

9. Decimal digit in BCD can be represented by

a) 1 input line
b) 2 input lines
c) 3 input lines
d) 4 input lines
View Answer

Answer: d
Explanation: Decimal digit in BCD can be represented by 4 input lines. Since, it is constructed with
4-bits.

10. The number of logic gates and the way of their interconnections can be classified as
a) Logical network
b) System network
c) Circuit network
d) Gate network
View Answer

Answer: a
Explanation: The number of different levels of logic gates is represented in a fashion which is known
as logical network.