2014-01-11

Notes for Digital VLSI Design with Verilog

Course Notes and Errata

for the 2008 edition of

Digital VLSI Design with Verilog

A Silicon Valley Technical Institute Advanced Course

by John Michael Williams

[email protected]
2014-01-11

NOTE:

The new 2nd Edition is available as of June 2014.

Course notes for it are downloadable at Scribd.

Copyright 2014, John Michael Williams.

Licensed free to Silicon Valley Technical Institute for training-course use. All other
rights reserved.

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Notes for Digital VLSI Design with Verilog

Table of Contents
Introduction............................................................................................................................. 1

Course Description.................................................................................................................... 1
Prerequisites.................................................................................................................. 3
Class Organization and Materials..............................................................................3
Proprietary Information and Licensing Limitations................................................5
Textbook...................................................................................................................................... 6
Textbook Errata (edition of 2008)............................................................................................ 6
Supplementary References..................................................................................................... 12
Supplementary Textbooks......................................................................................... 13
Interactive Language Tutorial..................................................................................13
Recommended Free Verilog Simulator.....................................................................13
VCS Simulator Summary (distributed separately).............................................................13
DC Synthesizer Lab 1 Summary (distributed separately).................................................13
DC Synthesizer Command Reminder (distributed separately).........................................13
Course Grading Policy............................................................................................................. 14
Getting Ready for Class Attendance.....................................................................................15

Week 1 Class 1...................................................................................................................... 16

Introduction to this Course.................................................................................................... 17

Week 1 Class 2...................................................................................................................... 18

Parameter and Conversion Lab 3.......................................................................................... 19

Nonblocking Control Lab 4..................................................................................................... 21

Week 2 Class 1...................................................................................................................... 23

Simple Scan Lab 5................................................................................................................... 23

Week 2 Class 2...................................................................................................................... 27

PLL Clock Lab 6....................................................................................................................... 28

Week 3 Class 1...................................................................................................................... 30

Memory Lab 7........................................................................................................................... 31

Week 3 Class 2...................................................................................................................... 32

Counter Lab 8........................................................................................................................... 33

Week 4 Class 1...................................................................................................................... 35

Strength and Contention Lab 9............................................................................................. 36
PLL Behavioral Lock-In Lab 10............................................................................................. 37

Week 4 Class 2...................................................................................................................... 38

FIFO Lab 11............................................................................................................................. 39

Week 5 Class 1...................................................................................................................... 42

Scheduling Lab 12................................................................................................................... 45

Week 5 Class 2...................................................................................................................... 46

Netlist Lab 13........................................................................................................................... 47

Week 6 Class 1...................................................................................................................... 48

Concurrency Lab 14................................................................................................................. 49

Week 6 Class 2...................................................................................................................... 50

Generate Lab 15....................................................................................................................... 52

Week 7 Class 1...................................................................................................................... 54

Serial-Parallel Lab 16............................................................................................................. 54

Week 7 Class 2...................................................................................................................... 56

Component Lab 17................................................................................................................... 57

Week 8 Class 1...................................................................................................................... 62

Connection Lab 18................................................................................................................... 63

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Notes for Digital VLSI Design with Verilog

Hierarchy Lab 19..................................................................................................................... 64

Week 8 Class 2...................................................................................................................... 66

Timing Lab 20.......................................................................................................................... 67

Week 9 Class 1...................................................................................................................... 68

Timing Check Lab 21.............................................................................................................. 69

Week 9 Class 2...................................................................................................................... 71

Sequential Deserializer I Lab 22.......................................................................................... 72

Week 10 Class 1.................................................................................................................... 77

Concurrent Deserializer II Lab 23........................................................................................ 77

Week 10 Class 2.................................................................................................................... 83

SerDes Lab 24.......................................................................................................................... 83

Week 11 Class 1.................................................................................................................... 89

Scan and BIST Lab 25............................................................................................................. 90
Tested SerDes Lab 26.............................................................................................................. 92

Week 11 Class 2.................................................................................................................... 96

SDF Lab 27............................................................................................................................... 97

Week 12 Class 1.................................................................................................................... 98

Scope of the Final Exam......................................................................................................... 99
Continued Lab Work (Lab 23 or later)..................................................................................99

Week 12 Class 2.................................................................................................................. 100

24.1.6 SystemVerilog [completely replaces Textbook section 24.1.6]...........................100

Some Features of SystemVerilog............................................................................101
New variable type logic............................................................................................ 102
New bit type............................................................................................................... 102
Unbased, unsized ' literals......................................................................................102
New gated event control iff......................................................................................102
Variants of the always block...................................................................................103
New timescale alternatives.....................................................................................103
New loop commands................................................................................................. 104
New interfact type.................................................................................................... 105
New assertion language........................................................................................... 107
24.1.7 Verilog-AMS............................................................................................................... 108
Introduction............................................................................................................... 108
Relationship to Other Languages...........................................................................108
Analogue Functionality Overview..........................................................................109
Analogue and Digital Interaction...........................................................................109
Example: VAMS DFF.............................................................................................. 110
Benefits of VAMS...................................................................................................... 111
Continued Lab Work (Lab 23 or later)................................................................................111

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Notes for Digital VLSI Design with Verilog

Introduction
This Course Note Book is provided as a supplement to the required Textbook. This
Note Book describes course-related matters, summarizes the day-by-day lectures and
labs, and includes tool-related updates. All EDA tools change rapidly, so any textbook,
including ours, will be somewhat obsolescent as soon as it has been published.
These Notes soon will be incorporated in a future edition of the Textbook.
At present, all references in the Textbook and this Note Book are to IEEE Std 13642005 for verilog and not to the later SystemVerilog Std document -- unless otherwise
stated. Except (a) for inclusion of existing C or C++ code, or (b) for complex assertion
composition, SystemVerilog and verilog 2005 differ very little, as explained in detail in
the final lecture below.
The Textbook soon will be available in print as the second edition of
Digital VLSI Design with Verilog. Some changes in the second edition
are:
Many minor typographical errors have been corrected, as have been several
other errors newly discovered in the text and figures.
Major upgrades in the second edition are:
Modified Day 1 presentation making it more useful to verilog beginners
Dozens of new figures
Expansion or clarification of explanations on almost every page
Upgrade of the simulation figures to be in color
New coverage of the features of SystemVerilog and VerilogA/MS
A new summary introduction to each chapter and lab exercise
IEEE Stds references include SystemVerilog as well as verilog
A new, optional lab checklist for recording learning progress
Any corrections or updates of the second edition will be posted on Scribd.
There will be no more updates to Scribd concerning the first edition.

Course Description
This hands-on course presents the design of digital integrated circuits, using the
verilog digital design language as described in IEEE Standard 1364 (2001 and after).
By a balanced mixture of lectures and labs, the students are introduced to language
constructs in a progressively more complex project environment. During the course,
students are familiarized with the use of the Synopsys Design Compiler to synthesize
gate-level netlists from behavioral, RTL, and structural Verilog code. The synthesis
constraints most useful for area and speed optimization are emphasized. Almost all the

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Notes for Digital VLSI Design with Verilog

class project work is done in the synthesizable subset of the language; logic simulation is
treated as a verification method in preparation for synthesis.
The Synopsys VCS simulator, or optionally [tbd] the Mentor QuestaSim simulator,
will be used in class; the majority of the labs are small enough to be worked with the
demo-limited Silos simulator which comes on the CD-ROM included with the Thomas
and Moorby or Palnitkar supplementary textbooks cited in the required Textbook.
Instruction in simulation tools will be minimal in this course, which is focussed on the
verilog language and on those constructs permitting logic synthesis.
Other course topics include design partitioning, hierarchy decomposition, safe coding
styles, assertions as designer aids, and design for test.

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Notes for Digital VLSI Design with Verilog

Course Topic List (partial):

Lecture and Lab: Modules and hierarchy; Blocking/nonblocking assignment;
Combinational logic; Sequential logic; Behavioral modelling; RTL modelling;
Gate-level modelling; Hardware timing and delays; Verilog parameters; Basic
system tasks; Timing checks; Generate statement; Simulation event scheduling;
Race conditions; Synthesizer operation; Synthesizable constructs; Netlist
optimization; Synthesis control directives; Verilog influence on optimization; Use
of SDF files; Test structures; Error correction basics.
Hands-on Projects: Shift and scan registers; counters; memory and FIFO
models; digital phase-locked loop (PLL); serial-parallel (and v-v) converter;
serializer-deserializer (serdes); primitive gates; switch-level design; netlist backannotation.

Prerequisites
A bachelor's degree in electrical engineering or the equivalent, with digital design
experience. Familiarity with programming in a modern language such as C.

Class Organization and Materials

The course is intensively hands-on. There will be 12 weeks of instruction, two 3-hour
lecture meetings per week, for a total of 72 hours in class, plus another 4 hours per week
of mandatory lab. The instructor will be present for a minimum of 2 of the 4 hours per
week of mandatory lab. Attendance will be taken on all these days, which total more
than 110 hours over the twelve weeks of the course.
In addition, the lab computers will be made available for additional time, as requested
by the attendee. Many lab exercises will be held during lecture meeting time; others will
be scheduled or continued outside class in the dedicated lab time.
A brief quiz will be held every lecture day except during the first and last weeks; and,
there will be a final exam. Homework will be assigned in the form of Textbook and
outside readings. During the course, students will be allowed as much additional access
to training computers as they require for course study, homework, or labs.

Required Textbook
The Textbook for this course is Digital VLSI Design with Verilog (see below for
citation). The Textbook contains explanations, homework readings, and all the lab
instructions. The CD which ships with the hardcopy edition of the Textbook contains the
original versions of the answers which are provided in the Labxx working directories.
It is not recommended that you purchase the PDF edition of the Textbook for this
course; you will want a hard copy anyway, to take marginal notes; and, viewing it onscreen will make your lab work much more difficult than if you had the capacity to page
through a book independent of what your computer was doing. If you did get the PDF
edition, you could read it on your own laptop computer during lecture or lab, but you will
not be permitted access to any computer during the (open-book) final exam, so notes in
your computer will be unavailable.

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Notes for Digital VLSI Design with Verilog

Textbook CD-ROM
Page xx (twenty) of the Textbook briefly suggests how to use the contents of the CDROM which accompanies it. As a suggestion, a good working environment in which to
organize the contents of the CD-ROM would be set up as shown in the following figure:

If you create the DC and VCS directories as suggested, you will have used everything in
the CD-ROM misc directory, so you will not need a misc directory in your working
environment.
The majority of the exercise answer subdirectories which depend upon the
tcbn90ghp_v2001.v simulation library contain a zero-length copy of that .v file. This
was done to reduce the space occupied by the answer CD-ROM. Whenever you
encounter a zero-length file named tcbn90ghp_v2001.v, you should replace it with a
full-length version from your VCS directory (see above) or from the misc data directory
on your CD-ROM.
The _vimrc file in the CD-ROM misc directory is a convenient startup file for the vim
text editor, which is the recommended text editor for verilog. The _vimrc file should be
renamed to .vimrc and copied to your home directory ("~"), if running Linux or Unix. If
you are running Windows, _vimrc should be copied to the startup directory which you
have configured for vim.

Course Note Book

The Course Note Book is a printout of these Notes provided to each attendee; it may be
used as an aid to the taking of notes during lecture. Bring your Course Note Book and
Textbook to every class and lab. Always read the lab instructions in the Textbook at
least once before the day on which the lab is scheduled. The Note Book will be updated
as necessary during the course to accommodate additional lecture material and tool
software improvements (mainly in the area of synthesis).

Class Attendance
Commitment to attendance at all lectures and labs is advised: This course is not an
easy one; any missed mandatory session should be made up as soon as possible. The
school provides for as many as three makeup lecture sessions during the course; and, a
total of two missed sessions (lecture or lab), not made up, is allowed. Attendance not
meeting these criteria means that a certificate will not be granted.

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Notes for Digital VLSI Design with Verilog

Proprietary Information and Licensing Limitations

This Course Note Book includes no proprietary information beyond that which is
copyrighted by the present author. However, during the course, students will be exposed
to features of the Synopsys and Mentor Graphics tools which may be considered
proprietary in other ways. Proprietary information generally may include anything
provided to users directly by the manufacturer. In addition, licensing provisions may
limit republication of specific performance details. To avoid including such information
in the Course Note Book, and to make the Course Note Book as portable among different
vendor tools as possible, the following approach has been adopted:
VCS: Almost all options convenient to run the VCS simulator are entered manually
according to a separately-distributed sheet, or are set up in a shell command alias. The
lab exercise answers and exercises generally are compatible with Aldec's or any other
vendor's simulator. However, the later lab exercises will be too big to be run on the
limited-capacity demo version of Silos provided with the supplementary textbooks named
in the References.
Design Compiler: Instruction on the operation of the DC synthesizer will be
presented almost entirely in lab; a handout sheet will be provided with a summary of
invocation options and synthesis constraints. Students may use these constraints in
their lab work as will be explained by lab instructions during the course.
QuestaSim: This Mentor Graphics tool, formerly named ModelSim, may be available
in the future upon student request; if so, information on its operation will be provided on
a separate handout sheet.
Publishing of operational performance details of VCS, Design Compiler, or QuestaSim
may require written permission from Synopsys or Mentor, and students are advised not
to copy, duplicate, post or publish any of their work showing specific tool properties
without verifying first with the manufacturer that trade secrets and other proprietary
information have been removed. This is a licensing issue unrelated to copyright, fair
use, or patent ownership.
The same applies to the TSMC library files available for viewing by attendees but
not distributed. These front-end libraries are designed for synthesis, floorplanning, and
timing verification and may contain trade secrets of TSMC. Do not make copies of
anything from the TSMC libraries, including TSMC documentation, without special
permission from TSMC and Synopsys.
The verilog simulation models in the files, LibraryName_v2001.v, are copyrighted but
not otherwise proprietary and are available for copying, study, or modification in the
context of this course. These models are simple but somewhat inaccurate; they are
intended for training use, only, and they never should be used for design work.
Verilog netlists produced by the synthesizer are not proprietary, although the Liberty
library models compiled for use by the synthesizer are proprietary and owned by
Synopsys. Evaluations of netlist quality in association with mention of Synopsys or
Design Compiler may be considered proprietary and should not be published or
distributed without special permission. The timing in back-annotated netlists may be
considered proprietary by Synopsys or TSMC.
Bottom line: Use what you know and understand, not what you copy.

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Notes for Digital VLSI Design with Verilog

Textbook
Williams, J. M. Digital VLSI Design with Verilog. Springer, 2008. This is the required
textbook and lab exercise book for the course. ISBN: 978-1-4020-8445-4.

Textbook Errata (edition of 2008)

Updates and additional explanations are among the weekly chapters below. The
known minor errors are as follows (a few lengthy corrections are with the weekly notes):
1. p. ix, Preface: Change "owner" to "co-owner" (the other co-owner of the school is Kevin
Lashkari).
2. p. xx in the Introduction: In 2.1 Contents of the CD-ROM, the last sentence of the
third paragraph misspells the name of the Mentor simulator, which should be
QuestaSim.
3. p. xxi, in References: Delete the entire first reference ("Anonymous"): Accellera no
longer has a SystemVerilog draft standard posted; it is now by IEEE, as described in
the Supplementary References below.
4. p. 6, in Lab 1: The caption of Figure 1.7 misspells the name of the Mentor simulator,
which should be QuestaSim.
5. pp. 9 - 10 in Lab 1: The figure labelled 1.9 is of the hierarchical (not ungrouped)
netlist which was synthesized earlier in the lab; there is no design_vision schematic
for the ungrouped (flattened) netlist, so the last paragraph on p. 9 is not correct.
6. p. 13: In the paragraph beginning "It usually is . . .", the literal expression in quotes
should be "1'b0", with the single-quote character (') in a fixed-width font such as
Courier.
7. p. 26: In the second sentence of the third paragraph, the bolded tick symbol should be
in a fixed-width font such as Courier, thus: ". . . delimiting tick symbol ('), . . .".
8. p. 29, Lab 3, Step 1: The verilog module name on the 2nd line includes a space; it
should be, ParamCounterTop.v.
9. p. 30, Lab 3, Step 2A: After the second declaration, there is an extra ", X". Delete
this, leaving "... B = -8; X = A + B; ...".
10. p. 40: In the second D latch code example, in the else branch, "ena1_n" should be
ena_n.
11. p. 44: In Section 3.1.2, the last bullet should be,
begin with a letter (alpha), underscore ('_'), or backslash ('\').
12. p. 45: The section header was wrapped by mistake. It should be, "3.1.5 BackusNaur Format (BNF)".
13. p. 46: In the paragraph above Latches and Muxes, the assignment in the second
from the last sentence includes a spurious space; it should read, "Zreg = A&B;".
14. p. 48: In the final paragraph, the asynchronous control names are garbled and should
be the same as in the preceding code example. The beginning of the first sentence
should read, "In this model, priority is given to Preset_n over Clear_n ...".
15. p. 53: Change the second sentence in the first paragraph after Figure 3.6 to read,
". . ., we shall install the muxes so that they switch the flip-flops out of the design".

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Notes for Digital VLSI Design with Verilog

16. p. 68: In the second paragraph, 4th line, the units are wrong, and there is a period
('.') missing. The line should read, "...of about 350 MB/s. A parallel ...".
17. p. 70: Change the paragraph below Figure 4.8 to read, ". . .; the horizontal grids in
Fig. 4.8 are spaced vertically at about 300 mV divisions".
18. p. 71: In the second paragraph, second line, there is an extra "of"; the correct wording
should be, ". . . we can create a netlist, . . .".
19. p. 73: The first begin in the code example is capitalized (Microsoft Word bug); it
should be "begin".
20. p. 75: In the first paragraph in Step 3, the reference should be to figure 4.10, not
"figure 3.10".
21. p. 76: In the last line of the code example, the "2'h00" should be 2'b00.
22. p. 77: In the second sentence following the code example, for consistency with the
code example, the second sentence should begin, "So, "HiBit'b1" would not be a legal
increment expression."
23. p. 85: In the paragraph below the second code example, the first few words should be,
"To declare a memory, ...".
24. p. 86: In the first sentence, it should be, "... more than three ...".
25. p. 86: The last bullet on the page no longer is correct. It should be changed to,
Many simulators such as the Silos demo version can not display a memory
storage waveform; new VCS, QuestaSim, and Aldec can.
26. p. 90: In the last paragraph, the end of the first sentence should be changed to, "... for
p1 and the rest of the 8 bits.".
27. p. 94: Two of the framing-error examples are garbled. There are ten bits per frame,
so the correct framing should appear this way:
40'b_xXxxxxxxxP_xXxxxxxxxP_xXxxxxxxxP_xXxxxxxxxP
The Rx framing error lagging should appear this way:
40'b_XxxxxxxxPx_XxxxxxxxPx_XxxxxxxxPx_XxxxxxxxPx
The Rx framing error leading is correct as printed.
28. p. 95: In the second sentence of Step 2, the module name should not have spaces:
"Mem1kx32".
29. p. 96: The first line on tip should read, ". . . given in the preceding . . .".
30. p. 96: The Fig. 5.4 label's module name should not have spaces: "Fig. 5.4 The
Mem1kx32 RAM schematic".
31. p. 97: In the $display of the code example, the format-specifier quote characters
should be double-quotes, thus: $display("...", $time, . . .);. Of course,
". . ." represents a format specifier.
32. p. 101: Figure 6.1 caption is missing a period ('.') after the word "values".
33. p. 113: In section 7.1.1, 3rd paragraph, there is a period instead of a comma: It
should read, "... assignment of '#'), there is ...".
34. p. 121: In the Symbol/Type list at the top of the page, the last symbol on the left is
reversed: It should be, "<<< shift (arith)".

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Notes for Digital VLSI Design with Verilog

35. p. 141: In the code example, the commented offset numbers and the 64-bit packet
should line up vertically this way:
//
60
50
40
30
20
10
0
// 32109876 54321098 76543210 98765432 10987654 32109876 54321098 76543210
64'b01100001_00011000_01100010_00010000_01111001_00001000_01111010_00000000;

36. p. 149: The last paragraph before Section 8.1.3 refers to a file "FindPattern.v" in
the Lab11 directory. This file can be found instead in the discussion of Lab11 below.
37. p. 159: The normal one of the five simple states at the top of the page should refer to
a 4-state FIFO, not a "4-register" FIFO. Similarly, the Fig. 8.13 text should describe a
FIFO with five or more storage states.
38. p. 170: The figure caption for Fig. 9.1 should call the clock Clk, not "C1K".
39. p. 173: The figure caption for Fig. 9.2 has two periods after the word Queue (instead
of one).
40. p. 176: In Case 2, step 9, the case, of course, should be Case 2, not "Case 1".
41. p. 179: In the lab Step 1, left code example, the second always block has two '$'
typoes: It should be, "always@(a) b <= a;".
42. p. 190: In the first paragraph after Fig. 10.4, the second sentence should be, "With X
= 1, if In goes to 0, q and qn both go to 1; if In then returns to 1, there is a latched
value, but it is indeterminate, because if either q or qn shifts to 0 sooner than the
other, it can clamp or reverse the other to its original 1 value."
43. p. 192: At time 7 in the truth-table, the !D value should be 0, not "1".
44. p. 203: In the next-to-last text paragraph, the third sentence should begin with, "If
one input bit never toggles, then each change of CheckInBus will spawn a new forkjoin block event in memory, ...".
Also, the last text paragraph should be preceded by this new one:
"The always-block example above also suffers from this problem, but to a lesser
extent."
45. p. 205: Delete the words, ", for temporary use, even", in the first sentence of the
second paragraph on this page. See the Supplementary Note on this section for an
explanation and a rewrite of the last paragraph on this page.
46. p. 206: The beginning of the first sentence in the first text paragraph should be
changed to say, "Variables declared in a task, like those in any other named block, are
static and hold their most recent value . . .".
Also, the third sentence in the first paragraph should begin, "This last holds . . .".
Also on this page, the last two sentences of the third text paragraph should read this
way:
"Task local variables are static reg-type variables shared among all calls of a given
task; so, of course, they share the same declaration. Sometimes this sharing may be
desirable, because it allows different running instances of the task to communicate
with each other."
47. p. 224: The first code example contains an incorrect always block. It should be the
same as the others, namely,
always@(Abus) #1 temp <= &Abus;

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Notes for Digital VLSI Design with Verilog

48. p. 225: In the first line of the Lab Procedure, "generate" should not end with a space
before ".".
49. p. 225: The second sentence in Step 4 should read, "Below the instructions in Step 4
F, is a slightly . . .".
50. p. 226: The Lab 15, Step 4C instruction following Figure 12.9 should be changed: Do
add a 33rd bit for parity; however, leave the 33rd bit unused for now.
51. p. 228: The figure caption to Fig. 12.11 should mention that the waveforms are for a
synthesized netlist simulation, not for a simulation of the verilog source.
52. p. 232: In the middle of the second paragraph, there is an extra "or": Change it to,
"...; or, instead of such a flag, we might provide ...".
53. p. 250: The first sentence of the second paragraph in MOS Switchesis
grammatically incorrect, beginning with the semicolon. It should be changed to, . . .
more negative, and an N-channel transistor (nmos) conducts . . ..
54. p. 257: The schematic in Fig. 14.8 shows a fourth trireg connecting the output, but
the waveforms in Figs. 14.8 and 14.10 are for a design in which that trireg has been
omitted. These figures are corrected in the Supplementary Notes below.
55. p. 259: The second parameter example in 15.1.1 contains an unnecessary "-".
56. p. 275: In the first code example, delete the if (FastClock==1'b1) as redundant.
57. p. 286: In the first paragraph, second sentence in 16.2.4, specparam is misspelled.
58. p. 288: The first paragraph after the last code example on this page should read, "In
the first statement above, assume that Clk clocks in D to Q1; ...".
59. p. 289: In Timing Lab 20, Lab Procedure, 1st paragraph, all occurrences of
"SpecIt" should be in Courier (fixed-width) font.
60. p. 291: For clarity, the first sentence in Step 3B should be rephrased to, "Change the
delay in the specify block to . . .". Also, in the second paragraph of Step 3B, delete, ".
. . and, in a change from x, the longest delay is used."
61. p. 298: In 17.1.3.3, in the explanation of $recovery, the middle of the first sentence
should be, "... control, such as a set or clear, to effective ...". Also, the last sentence in
the $setuphold discussion should be, "See the explanation in the section below on
negative time limits."
62. p. 299: Figure 17.1 is incorrect in regard to $removal; it and the explanation of
$removal should be corrected as in the Supplementary Note below. The second
sentence in the $removal explanation, continued onto this page, should say, "... how
long after that edge does an asynchronous control have to remove itself in order for the
clock edge to be ignored?"
In 17.1.3.3, the last sentence on $recrem should be, "See the discussion below on
negative time limits." [also corrects an extra period ('.')]
63. p. 303: The first sentence in 17.1.7 should have the word notifier as shown here (in
italicized proportional font, not italicized fixed-width font).
64. p. 303: In the middle of the paragraph beginning "PATHPULSE", the sentence
mentioning the "type" of a timing path should be changed to, "It changes the inertial
delay behavior of the timing path involved."

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Notes for Digital VLSI Design with Verilog

10

65. p. 307: The 3rd paragraph is Step 6 should say, "Add a specify block after the
module header declaration in DFFC, setting . . .."
66. p. 312: In the caption to Fig. 18.1, the final sentence should be changed to, "None of
the PLL, FIFO, and DesDecoder will synthesize correctly, but all will simulate
usably."
67. p. 317: In Fig. 18.7, the ClockIn to the "B" two-bit counter should not be labelled
"(delayed)". The paragraph before this figure should be ignored.
68. p. 323: At the bottom of the page, the third editting instruction should be:
Rename the testbench module to PLLTopTst.v.
69. p. 327: In the paragraph beginning, "Prepare to set . . .", change the last sentence to,
"Assign a default value of 5 (for 25 = 32 words)."
70. p. 330: In the second code example, the last line of the port map has an incorrect
underscore. It should be, ", .Empty(FIFOEmpty)".
71. p. 342: In Fig. 19.3, the input port should be named ClkW, not the "CkW" which is
shown in a Supplementary Note for that page.
72. pp. 351-352: For improved readability in both the incrRead and incrWrite tasks,
the first else in each of these should have expressions reversed to "if
(ReadAr==OldReadAr)" and "if (WriteAr==OldWriteAr)".
73. p. 356: In Step 9, first paragraph after the first code example, change the second
sentence to read, "Start by removing the SerValid gate . . ..".
74. p. 358: The 4th bulletted item should end with a period '.'.
75. p. 361 ff: Throughout Chapter 20 (Week 10, Class 2) and Lab 23, "serdes" should be
spelled "SerDes", and "deserializer" should be "Deserializer", when referring
specifically to the class project design.
76. p. 378: In the middle of the third paragraph, the reference to a "cell array" should be
"cell vector", for consistency with verilog terminology.
77. p. 383: In Lab 25, Step 2, the final words in the 1st paragraph should be separated:
"... our larger SerDes design."
78. p. 399: In the last line on this page, there is an extra blank before the comma
following "Deserializer".
79. p. 401: The "Loose Glitch Sinks Chips" pun should be in a Gothic typeface, such as
Windows MariageD:
80. p. 402: In Step 8A, second paragraph, the scan-insertion commands are in
Lab25_Ans/Step01_IntScan/... instead of in "Lab25_Ans/IntScan/...".
81. p. 406: In the last sentence of the first paragraph below Figure 22.1, the reference to
SDF punctuation should be proportional-font parentheses enclosing fixed-width singlequoted parentheses, thus: " . . . ( '(' and ')' ) . . .". The single-quotes and the inner
parentheses should be in fixed-width font (such as Courier).
82. p. 409: The verilog code example is displayed with the wrong quote characters; it
should read, initial $sdf_annotate("Intro_TopNetlist.sdf");
83. p. 409: In the SDF code example, the wrong quote characters appear: It should be
written, (CELLTYPE "ctype").

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84. p. 415: In the bulletted list of omitted topics, "design_vision" has been split into
two words.
85. p. 416: In the system task and function tabulation, $readmemb and $readmemh
should not be boldface; they were mentioned but never exercised.
86. p. 427: In the bulletted SystemVerilog feature list, the `timescale should be backquoted in fixed-width font, not single-quoted, thus:
timeunit and timeprecision declarations instead of `timescale.

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Supplementary References
Note: Active-HDL, Design Compiler, Design Vision, DVE, HSPICE, Liberty, ModelSim,
NanoSim, QuestaSim, Silos, VCS, and Verilog (capitalized) are trademarks of their respective
owners.

Anonymous. IEEE Std 1800-2012: Standard for SystemVerilog. Verilog is a proper

subset of SystemVerilog and ceases to be an independent standard with the Std
1364-2005 edition. After 2010, all updates to the LRM for verilog have been in
IEEE Std 1800, only. Happily, this means little further change in verilog per se.
The complete SystemVerilog manual currently (2013-08) is available free for
personal users at http://standards.ieee.org/getieee/1800/download/18002012.pdf.
Anonymous. SystemVerilog. Background and basic extensions of verilog, with
examples, at http://en.wikipedia.org/wiki/SystemVerilog (2013-08-10).
Anonymous. SystemVerilog Introduction. An overall introduction and complete details
of the language are posted online at http://www.systemverilog.in
/systemverilog_introduction.php (2013-08-11).
Anonymous. Verilog-AMS Language Reference Manual, Draft v. 2.3.1 of June, 2009.
Accellera. Available for download (free for individuals) at the Accellera web site.
This is the current language standard. This document is the one which should be
used to resolve disputes or clarify understanding of the language; it contains many
examples and detailed explanations. Presumably, IEEE eventually will produce a
Std document more or less along the same lines.
Bansal, et al. Circuit Design Hint: "Calculating Corner-Independent Timing Closure",
online at Embedded.com (http://www.embedded.com/columns
/technicalinsights/220900615, 2009-10-27).
Kundert, K. S. and Zinke, O. The Designer's Guide to Verilog AMS. Boston: Kluwer
Academic, 2004. Kluwer now is a subsidiary of Springer.
This is the only textbook available on the subject, as of March 2009. It includes an
excellent chapter on top-down design and its strength is in the mixed and analogue
features. It contains a VAMS language specification which now is somewhat out of
date; for example, the syntax is verilog-1995, only. There are a few small mistakes
(many corrected by errata posted at the authors' web site).
Plank, J. S. "A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like
Systems", Software Practice & Experience, 27(9), pp. 995 - 1012, September 1997.
Available online as Technical Report CS-96-332, Department of Computer Science,
University of Tennessee (See erratum at
http://www.cs.utk.edu/plank/papers/CS-03-504.html , 2007-10-03).
Shah, Ankit. Whats new in Systemverilog 2009? New constructs and examples for the
2005 and 2009 updates at
http://testbench.in/SystemVerilog_2009_enhancements.html (2013-08-10).
Thompson, D. "The benefits of FireWire on PCI Express". EETimes online, 2011-09-06.
Posted at http://www.eetimes.com/design/microcontroller-mcu /
4219628/The-benefits-of-FireWire-on-PCI-Express .

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Notes for Digital VLSI Design with Verilog

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Wood, B. "Backplane tutorial: RapidIO, PCIe, and Ethernet". DSP Designline, January
14, 2009 issue. Posted at http://www.dspdesignline.com/howto
/showArticle.jhtml;articleID=212701200 (2009-01-14).

Supplementary Textbooks
The Thomas and Moorby and Palnitkar textbooks are referenced many times in our
Textbook for optional, supplementary exercises and readings. These may be useful to
clear up understanding of specific topics presented during the course. Each of these
books includes a Simucad Silos Verilog-2001 (MS Windows) simulator on CD-ROM,
with Silos simulation projects. This is a capacity-limited demo version of the Silos
simulator, but it will work with many of the smaller lab exercises in this course.
References to the Thomas and Moorby textbook are for the 2002 (4th) edition. Since
then, a new edition has been published (using verilog 2001 headers throughout); the page
and section numbers may differ somewhat from those given in our Textbook.

Interactive Language Tutorial

Evita Verilog Tutorial. Available in MS Windows environment. This is a free
download for individual use. Sponsored by Aldec at http://www.aldec.com. The
language level is verilog-1995 only. When downloading, mention the course unless you
want sales followup.
This interactive tutorial includes animations, true-false quizzes, language reference,
search utility, and a few minor bugs and content errors. It is very easy to run and may
be useful especially for understanding course content from a different perspective.

Recommended Free Verilog Simulator

In addition to the Evita free tutorial, which is somewhat out-of-date, Aldec provides a
free, downloadable Verilog-2001 simulator which runs in MS Windows; this is a version
with generous but limited capacity and is highly recommended.
However, for more than a 20-day unlicensed trial, it is necessary to have the Windows
machine connected to the internet in order for the Aldec site to inspect the machine and
create the license.

VCS Simulator Summary (distributed separately)

DC Synthesizer Lab 1 Summary (distributed separately)
DC Synthesizer Command Reminder (distributed separately)

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Course Grading Policy

Completion of the course with passing score of 65% or above means award of a
Certificate of Achievement; otherwise, a Certificate of Attendance may be awarded if no
more than 2 of the 36 scheduled meetings were missed. The score is a weighted sum of
quiz score plus final exam score, with quiz weighting as below.

Quizzes
There will be a quiz every scheduled lecture day, except during the first and last weeks
of the course. The total of 20 quizzes primarily are meant to be instructional.
Generally, quizzes will include material presented in the current or most recent lab or
lecture.
Each quiz will be brief, about 15 minutes, and will count 10 points, for a total of 200
points over the whole course. Quizzes are teaching as well as testing instruments, so
poor performance on quizzes need not mean very much for an enrollee's final status.
No makeup will be allowed for any missed quiz.
Quiz weighting rule: Round the quiz average percent up to the next 10%; then, for
every 10% above 50%, or any quiz missed, add 1% to the baseline 5% weight of the
quizzes.
Examples:
1. An enrollee takes every quiz and averages 95%: 95 --> 100. The quizzes
therefore equal 5% + 5 x 1% = 10% of the total course score. The final exam
contributes 90%.
2. Every quiz is missed: 0 --> 0. The 0% quiz average will be weighted as 5% + 20
x 1% = 25% of the total course score. The final exam contributes 75%.
3. Every quiz is taken and the quiz average is 34%: 34 --> 40. The 34% quiz
average then contributes 5% of the total course score.
4. 1 quiz is missed and the quiz average is 65%: 65 --> 70. Then, the 65% counts
as 5% + 2 x 1% + 1 x 1% = 8% of the total course score.

Final Exam
The final exam will be a two-hour, open-book comprehensive exam scheduled after the
final class lecture day of the course. The exam will be paper-and-pen; no electronic
assistance. Enrollees will be expected to answer content-related questions and to code
verilog. A makeup may be taken for the final, if the scheduled final exam should be
missed for good reason.

Quiz or Exam Information Sharing

All enrollees or others exposed to the course are on their honor not to share any
content (questions or answers) of any quiz or exam with anyone.

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Getting Ready for Class Attendance

At the time of this writing, the Textbook is about five years old. Before doing anything
else,
1. Use the preceding "Errata" in these Notes to fix all Textbook errors.
2. Use the "Supplementary" material below in these Notes to update the
various parts of the Textbook indicated.
Modification of the Textbook may be done with sticky notes, or by writing corrections
on the Textbook pages.
If you are attending the course, it is strongly recommended to read each Textbook class
lecture and lab at least once before the scheduled day.

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Week 1 Class 1
Today's Agenda:
Introductory Lecture
Topics: Course content and organization.
Summary: This is a verilog language course. It is heavily lab-oriented and its
goal is netlist synthesis, more than simulation, as a content-related skill.
Homework reading assignments are of utmost importance, but neither labs nor
homework are graded. Daily quizzes (after the first week) and the final exam
are graded.
Introductory Lab 1
This introduces tool operation of the synthesizer and simulator. It is meant to be
executed by rote; explanations will follow.
Lab Postmortem
After having seen a verilog design through the tool flow, the enrollee is explained
the basic language constructs which were involved.
Reality-Check Self-Exam
This is a quiz to help enrollees understand how well prepared they are for the
course. It is not collected or graded.
Lecture: Verilog vectors and numerical expressions
Topics: Vector notation and numerical constants.
Summary: Verilog vector declarations and assignment statements are presented.
Numerical expressions in hexadecimal, binary and other bases are described.
Simulation delay expressions and verilog timescale specifications are
introduced.
Verilog Operator Lab 2
This exercises basic vector assignments and associated simulation delays. It also
exercises simple boolean operators and shows how a verilog module header
may be written either in ANSI standard format or in the older, verilog-1995,
"K&R C" format.
Lab Postmortem
After lab Q&A, vector extensions and reduction operators are explained.
Advantages of the ANSI module header format are given. Module timescale
and time resolution are discussed.
Lecture: VCD and SDF files
Summary: Simulator VCD files and synthesizer SDF file formats are described
briefly and their purposes explained.

Note: The old first-day lecture has been removed. It is assumed that students in the
future will obtain a copy of the Textbook before the scheduled first day has begun.

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Introduction to this Course

The course is on the verilog language, as exercised by concentrating on logic synthesis
with the Synopsys Design Compiler. Simulation will be to verify the verilog for
synthesis rather than to teach simulation techniques.
The grading policy is explained at the beginning of this Course Note Book. You are on
your honor not to share any content (questions or answers) of the quizzes or any exam
with anyone, whether they are enrolled in this course or not.
Read the Course Note Book section(s) and Textbook chapter for each day
before the day the class is held. This will give you the opportunity to formulate
questions and deepen understanding before the presentation. Don't put off this reading!
Except for the introductory lab today, reading lab instructions for the first time in the lab
may be difficult, error-prone, and discouraging.
Basic Ground Rules:
Attendance at lecture will be recorded each class day, and each mandatory lab day, for
quiz-weighting purposes and also to fulfill administrative requirements. The instructor
will be available during all lecture sessions and for at least two hours of each mandatory
lab session.
Course Note Book sections will be updated as necessary as the course proceeds and
will be available in hardcopy at least two weeks in advance. Updates to the current Note
Book primarily will reflect changes in tool operation or performance.
Lecture. Lectures usually will not be very long, so nonemergency breaks are
discouraged. Please do interrupt if the lecture presentation has you lost. However,
please save detailed, elaborative, or speculative questions for lab.

Communication inhibits learning. Please do not use lecture

time to work at the cell-phone or other computer.
Lab. Take a break any time during lab. The lab machines are for your use any time
during the course, except during lecture.
Labs often are cumulative: Don't discard results from your labs; save them where you
completed them or in a backup subdirectory.
Homework. Neither lab work nor assigned homework is graded.

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Week 1 Class 2
Today's Agenda:
Lecture: More language constructs
Topics: Traditional module header format. Comments, procedural blocks,
integer and logical types, constant expressions, implicit type conversions and
truncations, parameter declarations, and macro (`define) definitions.
Summary: We expand on the previously introduced, basic verilog constructs
allowed within a module. The emphasis is on procedural blocks and vector
value conversions. Verilog parameters are introduced as the preferred way of
propagating constants through the modules of a design; the main alternative,
globally `defined macro compilation, also is presented.
Type Conversion Lab 3
A trivial design illustrates the use of `define to control parameters, and the use
of comments. We exercise constraints to synthesize for area and for speed.
We also do exercises in signed and unsigned vectors, and in vector assignments
of different width.
Lab postmortem
This is mostly lab Q&A; also, the use of vector negative indices is discussed.
Lecture: Control constructs; strings and messages
Topics: The if, for, and case; the conditional expression; event controls; the
distinct contexts for blocking and nonblocking assignments. The forever
block and edge event expressions. Messaging system tasks. Shift registers.
Summary: Procedural control and the basic if, for, and case statements are
introduced. The relationship of if to the conditional ("?:") is described, with
warning about 'x' evaluations. Blocking assignments for unclocked logic;
nonblocking assignments for clocked logic. The forever block is presented but
its use is not encouraged. posedge and negedge for sequential logic are
presented. Assertions based on $display, $strobe, and $monitor are
advocated as good design practice. Finally, a shift register is presented briefly
to prepare for the next lab session.
Nonblocking Control Lab 4
After flip-flop and latch models, verilog for a serial-load and parallel-load shift
register is coded, simulated, and synthesized. A simple procedural model of a
shift-register is given.
Lab postmortem
In addition to lab Q&A, some thought-provoking questions about synthesis and
assertions are asked.

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Supplementary Note on Textbook p. 23, verilog comment examples: In the code

at the bottom of the page, the boolean operators may be replaced for simplicity with
bitwise ones in all three assign examples: Just change "&&" to &, and "||" to |
everywhere.

Supplementary Note on Textbook p. 26, width adjustment: Steps 1-4 in the

middle of the page hold for most of the binary operators. However, according to IEEE
Std 1364, Section 5.4.1, logical and reduction operators are treated specially: Such
expressions are evaluated first; then the width is adjusted to that of the destination
(LHS), as shown in the code examples on the same page. For example, for reg[3:0] A,
B; reg Z; Z = A && B;, A and B each are evaluated true or false as 4-bit vectors;
then, the logical and is taken. Likewise, if reg[3:0] Z; reg A, B; Z = A && B;,
the and of A and B is evaluated; then, the result is lengthened for assignment to Z.

Supplementary Note on Textbook p. 27. A macro also may be called a

compiler directive. In verilog, they almost always merely are defined or assigned a
text value to be substituted. In principle, a macro could be used, as in C, to execute code
during simulation, but not all tools will accept executable substitutions.

Supplementary Note on $display. Add a new paragraph above the first code

example on p. 28: "The $display system task is like printf in C or C++: It formats a
message to be printed to the terminal window of the simulator. It is ignored during
netlist synthesis. We shall discuss details of $display later today."

Parameter and Conversion Lab 3

Topic and Location: Simple use of defined macro values and parameters in
synthesis. Type conversions, truncations, and numerical interpretation of vector values.
Work in the Lab03 directory for these lab exercises.
Preview: In this lab we present a small verilog design consisting of a counter and a
bit-converter; the latter represents hardware which reformats the counter's output by
padding it with zeroes to a configurable width. This design is parameterized already,
and the student merely changes the macro controlling the parameter values and
synthesizes the design. Basic constraints for netlist optimization then are exercised.
The lab then changes topic to elementary signed and unsigned arithmetic operations to
be checked by simulation. Finally, some elementary exercises are simulated on
truncation and widening of verilog vectors.
Deliverables: 1. An area-optimized netlist and a speed-optimized netlist synthesized
in Step 1. 2. A second set of Step 1 area and speed optimized netlists with the
Converter padding value changed. 3. One or more new verilog modules in a file named
Integers.v, with assignment statements as described in Step 2. 4. A variety of
assignment statements in one or more modules in a file named Truncate.v, to fulfill
Step 3.

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Supplementary Note on Textbook p. 29, Lab 3, Step 1: This particular synthesis

.sct file begins with numerous EDIF-specific commands, just to show how a synthesizer
might have to be configured to generate an EDIF netlist for fabrication purposes. Such
commands will be omitted in all our subsequent labs.
Also, if you simulate the ParamCounterTop design, ignore the Textbook instruction to
"use the DC macro": The `ifdef DC construct already has been added.
Finally, the following two paragraphs should be added after the paragraph beginning,
"Don't bother simulating, . . .":
"In this and all subsequent labs, to run the synthesizer, use the lab-specific .sct
synthesis script file provided for you. When none is provided, you should create your
own by copying an existing .sct file and modifying it in a text editor. Such modification
generally will include changes in the names of the verilog input files, the name of the
synthesis library (working directory), and the names of log files and synthesized netlists.
The .sct constraints will have to be modified with special attention to the intended
design functionality.
"Hardly anyone in practice writes down a synthesis script file except by starting from a
copied template."

Supplementary Note on Textbook p. 30, Lab 3: In new VCS, vector display

formats are associated with variables, not with displayed traces; so, it is not possible to
view a variable in more than one radix at a time.

Supplementary Note on Textbook pp. 32 - 33 discussion of clocked logic and clock

generators:
Here are examples of code paired with equivalent schematics:
always@(posedge Clk)
Q <= D

always@(negedge Clk)
Q <= D

initial Clock = 1'b0;

...
always@(Clock)
#10 Clock <= !Clock;

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Supplementary Note on clock gating and reconvergence. While the simple and
gate shown in Figure 2.2 (Textbook p. 36)
illustrates the point, with the logic shown, an
asynchronous ShiftEna could cause a glitch on
the gated clock, with unpredictable results. A
realistic clock gate would use a transparent latch
which was enabled by the inactive edge of the
clock to be gated, as shown to the right.

A glitch-proof gated clock assumed active high.

Of course, the additional delay of the latch would make the reconvergence delay longer,
possibly requiring more design effort to avoid it.

Nonblocking Control Lab 4

Topic and Location: Models and assertions for D flip-flops, D latches; also for shift
registers, serial- and parallel-load, built using the flip-flop models.
Work in the Lab04 directory. Create subdirectories under Lab04 if you want.
Preview: Nonblocking assignment statements are used for clocked sequential logic
elements such as flip-flops. In this lab, we model single flip-flops with various features
such as asynchronous preset or clear. We also model latches to see how this is done. We
then use the flip-flop models to construct a shift register with serial load of data. This
shift register is tested by simulating it. Then, we modify the shift register by adding
multiplexers so that it can be loaded all bits in parallel. This last design is synthesized
for area and for speed. Finally, a vastly simpler procedural shift register is presented
and subtleties of its design are explored in simulation and synthesis.
Deliverables: Step 1: A verilog source module with three different D flip-flop models.
Synthesized netlists of this module optimized for area and speed. Step 2: A simulatable
verilog source model. Step 3: A source module with three different latch models and
synthesized netlist; plus, assurance that latches were synthesized as expected. Step 4:
A structural, serial-load shift register model in at least two different files which
simulates correctly. Step 5: A structural parallel-load shift register model in at least
three different files; this should simulate correctly and should be synthesized to two
different netlists, one optimized for area and the other for speed. Step 6: Two
simulation models of a procedural shift register, one using nonblocking assignments and
the other blocking.

Supplementary Note on Step 1 of Lab 4: Add a new paragraph on p. 37 at the

end of Step 1: "Because these three always blocks will coexist in the same module, their
procedural variables (regs) will have to be declared with three different names. Also, to
put the three regs into the (hardware simulation) design, each one will have to be wired
to a module output port with its own continuous assignment statement."

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Supplementary Note on Fig. 2.5 of p. 40: A minor improvement to this figure

would be to reverse the two top inputs to the leftmost mux, like this:

22

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Week 2 Class 1
Today's Agenda:
Verilog Lecture
Topics: Variable reg and net types; constants; basic simulation and relation to
synthesis; basic system tasks & PLI. Internal scan.
Summary: This time we study a variety of features of the verilog language. We
begin by explaining reg and net variables again, and we distinguish several of
the types of net available in verilog. We mention BNF format for clarifying
syntax. We then return to sequential logic synthesis, using latch and mux
similarities to illustrate how combinational logic should be modelled. We
introduce the basics of clock simulation and point out some simple ways of
avoiding race conditions. We wrap up with a brief presentation of internal and
boundary scan, which increase observability of design state in the hardware.
Simple Scan Lab 5
Using the combinational Intro_Top design of the first lab of the course, we add a
JTAG port, register all inputs and outputs using flip-flops, install muxes, and
link the flip-flop muxes to form a scan chain. Finally, we add an assertion to
be sure the scan mode operates correctly.
Lab Postmortem
We discuss glitches and scan-chain operational refinements.

Simple Scan Lab 5

Topic and Location: An internal-scan chain formed from muxed flip-flops.
Preview: We modify the original Lab01 demo design, Intro_Top, so that it includes
some design-for-test (DFT) logic as follows: We add a JTAG port and then insert
sequential components (flip-flops) on every I/O. Thus, we convert our purely
combinational Intro_Top design into a synchronous one. After that, because our design
now includes sequential elements, we can replace these elements with scannable ones.
We do this first by adding muxes to "short-circuit" the data flow away from the flip-flops,
under control of the mux select state. We then chain the flip-flops together, two muxes
for each flip-flop, so that one select state connects all flip-flops into a shift register, and
the other select state just leaves the flip-flops on the I/O's in the design. Finally, we add
an assertion to report misuse of the chain when the design is in the scan state.
Deliverables: Step 1: A single verilog module, correctly simulating, with seven
independent D flip-flops connected separately to the module I/O ports; also, two
synthesized netlists, one optimized for area and the other for speed. Step 2: A correctly
simulating verilog model of a flip-flop with synchronous clear. Step 3: A simulation
model and synthesized netlists as in Step 1, but with D latches instead of flip-flops;
results of inspecting the netlists for correctness. Step 4: Two or more verilog module
source files making up a correctly simulating serial-load shift-register. Step 5: Three or
more verilog module source files making up a correectly simulating parallel-load shift
register; also, two netlists (synthesized for area and speed). Step 6: A procedurally-

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modelled serial-load shift-register in a single verilog source file (testbench may be in a

separate file); one synthesized netlist, optimized any convenient way.

Supplementary Note on procedural blocks: On p. 45, change the 3rd item in the
bulletted list of block contents to:
procedural control statements (if; for; case; forever)

Supplementary Note on pp. 45-46, BNF: The example should be replaced with a
better one as follows:
". . .. For example, suppose for simplicity's sake that the BNF for a logical operator
was,
logic_op ::= boolean_op | bitwise_op
boolean_op := && | || | !
"Then, from this we may deduce that a logical operator always will be a bitwise
operator or a boolean &&, ||, or !. An attempt to use subtraction (-) as a logical
operation then would be an error easily recognized from the BNF given in this example."

Supplementary Note on modelling sequential logic: On p. 48, the first sentence

in the first paragraph on "Clocks" should be revised to: "A clocked block in verilog is an
always block with an event control containing an edge expression, posedge or
negedge."

Supplementary Note on asynchronous controls, p. 49: Add a new paragraph just

above the section, "Race conditions": "When one or more asynchronous controls is
present in a clocked block, the clock always will have the lowest priority."

Supplementary Note on synthesizable coding: On p. 50, add three new items to

the beginning of the bulletted list:
Don't assign to the same variable in more than one always block.
Don't mix blocking and nonblocking assignments in a single always block.
Generally, avoid coding for level-sensitive sequential constructs (latches);
use flip-flops instead.

Supplementary Notes on the Scan Lab Introduction:

A. On p. 52, the last sentence of the paragraph beginning, "First, we'll add ...",
should be clarified by rewording it as "... with its original functionality intact,
except for slower operation because of having to wait for clock edges on all
inputs and outputs."
B. On p. 53, the second sentence in the first paragraph below Fig. 3.6 should be
reworded to, "... we shall install the muxes so that they bypass the flip-flops
entirely."

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Supplementary Note on Textbook Lab 5 Step 2, p. 54: When this Step is

complete, the original Intro_Top design, from Lab 1, should have been changed so that
it's schematic would look like this:

Supplementary Note on Textbook Lab 5 Step 7: The new VCS shows the
assertion messages like this:

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Supplementary Note on Textbook Lab 5 Optional Step 9: Add a new last

paragraph at the bottom of p. 58: "Give your flip-flops instance names beginning with
"FF", for example, FFX, FFY, and FFZ; this is for consistency with the synthesis .sct file
provided for you in your Lab05 directory. If you use other instance names, you will have
to edit the set_max_delay command in the .sct file accordingly.

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Week 2 Class 2
Today's Agenda:
Lecture on SerDes
Topics: Serial vs parallel data transfer, PCI Express, PLL functionality.
Serializer-Deserializer and PLL design.
Summary: We introduce our class project, a full-duplex serializer-deserializer
(serdes), by discussing serial bus transfer advantages and the performance
specifications of a PCI Express serdes lane. We then look at the serializer and
deserializer ends of a serdes on a block level. We also see how a PLL works on
a block level. We decide to start our project by designing and implementing
the PLL which will be instantiated at each end of each serial line.
PLL Clock Lab 6
After designing and testing a digital PLL, we sketch out and simulate a
preliminary, generic parallel-serial converter. We finish with a parallel-toparallel frame encoder which may be used to prepare data for serialization.
Lab Postmortem
We discuss simulator time resolution and digital formats, comparator features,
and our choice of frame encoding.

Supplementary Notes on the Textbook section Introduction to SerDes and PCI

Express:
For further insight into serdes, read the Wood (2009) article cited in the References
above.
The standard document for PCIe version 3 was finished in 2012; the specified speed is
8 Gb/s per direction per lane, compared with 2.5 Gb/s and 5 Gb/s for versions 1 and 2,
respectively. The packet format will be changed so that very complex deserialization
algorithms will permit a format overhead of only about 2 bits per 130 bit data packet.
Because of lab time limitations, our serdes does not perform any packet
acknowledgement, making our serdes perhaps a bit more like Ethernet than PCIe.

Supplementary Note on the PLL comparator: On p. 64, in the waveforms of

Figure 4.3, a '+' means that the HiCount is incremented on that ClockIn edge; a '0'
means that it is reset to 2'b0 on the opposite edge.

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PLL Clock Lab 6

Topic and Location: PLL simulation and synthesis, parallel-serial data conversion,
and framing of data for serialization.
Begin this lab by logging in and changing to the Lab06 directory.
Preview: In preparation for our serdes class project, we implement a verilog PLL
composed of VFO, clock comparator, and counter-multiplier modules. For a rough grasp
of format conversion problems, we then complete a provided sketch of a generic parallelserial conversion module. Finally, we look into a way of preparing parallel data into
frames for later serialization.
Deliverables: Step 1: Four .v module files with modules and port declarations;
modules are named PLLsim, VFO, ClockComparator, and MultiCounter. A fifth
testbench file which instantiates the top-level module, PLLsim, for simulation. Step 2:
A verilog macro `include file named PLLsim.inc which contains VFO operating
characteristic definitions. A working VFO simulation model provided with a temporary,
fudged testbench input which emulates ClockComparator input. Step 3: A verilog
model of the ClockComparator, to be simulated later. Step 4: A verilog model of the
MultiCounter, to be simulated later. Step 5: Simulation of the completed PLLsim
module which verifies that our PLL will track its input clock frequency, however coarsely.
Step 6: A completed generic parallel-serial model based on the incomplete verilog model
provided, and which simulates correctly. Step 7: A correctly simulating frame encoder;
synthesized netlists of this encoder which attempt optimization for area and speed.

Supplementary Note on the Lab 6 procedure: Figure 4.10 should be modified

slightly to make it obvious that the AdjFreq wire is a 2-bit bus:

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Supplementary Note on last part of Lab 6: The format of our class project
SerDes serial packets will be:
64'bxxxxxxxx00011000xxxxxxxx00010000xxxxxxxx00001000xxxxxxxx00000000
The last part of Lab 6 is to just to perform a reformat of 32 bits of data to the above
kind of 64-bit packet:
Data3

Data2

Data1

Data0

becomes
Data3

Pad3

Data2

Pad2

Data1

Pad1

Data0

Pad0

This can be done procedurally, if you wish; or, by continuous assignment:

assign Packet[63:56] = Data3;
assign Packet[55:48] = Pad3;

... etc. ...

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Week 3 Class 1
Today's Agenda:
Lecture on memories and verilog arrays
Topics: Memory chip size descriptions, verilog arrays, parity checks and data
integrity; framing for error detection,
Summary: We look into how the storage capacity (in bits) of a memory chip can
be described, and then we show how to model memory storage by verilog
arrays. We then study parity, checksums, and error-correcting codes (ECC) as
ways of tracking data integrity in stored memory contents -- or, in data storage
in general. We then show how parity may be used in 10-bit serial data frames
to extract a serial clock.
Lab on RAM models
We show how to model a simple single-port RAM in verilog and then to
instantiate it in a wrapper to give it bidirectional I/O ports.
Lab Postmortem
We discuss hierarchical references in verilog, the concatenation operation, and
some RAM details.

Supplementary Note on the Textbook, p. 85: The paragraph beginning "To

declare a memory . . ." merely states in words what the immediately preceding block of
code shows.

Supplementary Note on the simple RAM model, p. 87: Parity checking can be
added this way:
module RAM (output[7:0] Obus, output ParityErr
, input[7:0] Ibus
, input[3:0] Adr, input Clk, Read
);
reg[8:0] Storage[15:0]; // MSB is parity bit.
reg[7:0] ObusReg;
// Parity not used for data.
//
assign #1 Obus = ObusReg;
assign ParityErr= (Read==1'b1)? (^Storage[Adr]): 1'b0;
//
always@(posedge Clk)
if (Read==1'b0)
Storage[Adr] <= {^Ibus, Ibus}; // Store parity bit.
else ObusReg <= Storage[Adr];
// Discard parity bit.
endmodule

Supplementary Note on ECC: Concerning Section 5.1.6, Textbook, p. 90, see the
Plank reference in these Notes for an example of how to generate Reed-Solomon ECC for
multiple-error recovery. While reading this reference, keep in mind that matrix
multiplication by a vector makes each term in the product vector dependent on all terms
in one matrix row and on every term in the multiplier vector. Also, note that the errors
being corrected in the Planck paper always have been errors localized exactly in the

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system (e. g., by identified crash of a specific hard disc) before the ECC is invoked.

Supplementary Note on the "toggle bit" explanation, Textbook, p. 94. To expand

upon the discussion of the lagging frame error, consider the following three specific
data bit-patterns, each formatted in error:
A. Data = 8'b0000_0000: Tx formats the serial frame as 10'b0000_0000_01, in
which the LSB is the inverted MSB toggle bit and the preceding bit is the parity (with
toggle bit ignored). With a lagging 1-bit frame error, Rx drops the MSB as part of the
previous frame and calculates parity based on this pattern, 10'b0000_0000_1x. The 'x'
is the ignored LSB. The resulting parity of '1' equals a parity error.
B. Data = 8'b1000_0000: Tx formats the frame as 10'b1000_0000_10; Rx receives
10'b0000_0001_0x and calculates a parity error.
C. Data = 8'b0000_0001: Tx formats the frame as 10'b0000_0001_11; Rx receives
10'b0000_0011_1x and again calculates a parity error.

Memory Lab 7
Topic and Location: Single-port RAM and a simple way to make memory I/O ports
bidirectional.
Preview: We exercise various kinds of verilog array assignment. Then, we use an
array to design a single-port static RAM 32 bits wide and 32 addresses deep, with parity.
We add a for loop in our testbench to check the addressing and data storage of this
model; we use the simulator memory or $display() to look inside the memory. Finally,
we modify the RAM from two, unidirectional input and output data busses to a single,
bidirectional input-output data bus. We use the concept of a "wrapper" module to
combine the original data busses. Finally, we synthesize the bidirectional, single-port
RAM.
Deliverables: Step 1: A verilog module in a file with the specified declarations and
assignments; simulated. Step 3: A corner-case-correct single-port RAM simulation
model with parity and an assertion which reports any parity error. Step 4: A testbench
including a for loop with exhaustive testing and display of data storage by the RAM
model. Step 6: A modified, correctly-simulating RAM model with one, bidirectional data
bus. Step 7: Two synthesized verilog netlists of the bidirectional RAM model, one
optimized for area and the other optimized for speed.

Supplementary Note on Section 5.2.2 Additional Study, p. 99: Since this web
site was visited last, Wagner's The Laws of Cryptography with Java Code has been
published in PDF format, with the Hamming code presentation as one chapter. It is
available at http://www.cs.utsa.edu/~wagner/laws or at
http://openpdf.com/ebook/java-cryptography-pdf.html (2010-04-07).

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Week 3 Class 2
Today's Agenda:
Lecture on counters and the verilog for them
Topics: Kinds of counter by sequence. Counter structures discussed: ripple,
synchronous, one-hot, ring, gray code.
Summary: After defining what we mean by a "counter", we examine typical
terminology used to describe HDL modelling in general. Then, we examine
several kinds of counter typically used in hardware design: Ripple,
synchronous (carry look-ahead), one-hot, ring, and gray code.
Counter Lab
We write, simulate, and synthesize several different kinds of counter, showing
how the rarely-used wor net may be applied in one of them. We finish by
using our old PLL clock output to drive three of them in the same design.

Supplementary Note to Section 6.1: A binary up-counter can be programmed to

count just ten, instead of 16, values in at least two different ways:
1. Program the wrap-around. This is the most common way and gives a count over
the numerical values 0..9:
always@(posedge Clk, posedge Rst)
if (Rst == 1'b1)
Count <= 4'h0;
else begin
if (Count < 9)
Count <= Count + 1;
else Count <= 4'h0;
end

2. Preload the counter to bias the wrap-around. This gives a count over any ten
contiguous, ascending values. For example, for the ten highest values,
reg[3:0] Count;
always@(posedge Clk, posedge Rst)
if (Rst == 1'b1 || Count == 4'hf)
Count <= 4'h6;
else Count <= Count + 1;

Supplementary Note on ripple counter noise: In Section 6.1.4.1, the last

paragraph, final sentence should say that the instantaneous power consumption and
noise are reduced, when compared with a synchronous counter of the same width and
clock speed. Of course, the total power also would be less for the ripple counter.

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Counter Lab 8
Topic and Location: We write verilog counter models, simulate them, and
synthesize them to compare performance of the synthesized netlists. We also create a
new design in which our old PLL is used to clock three different counter structures.
Work in the Lab08 directory for this lab.
Preview: We start with verilog for a ripple counter, using flip-flop models from
previous labs. We synthesize a netlist from the ripple-counter model and compare its
simulation speed with a netlist synthesized from a synchronous-counter model. We also
write a behavioral verilog model of a counter and simulate and synthesize it. After this,
we replace or expressions in the synchronous-counter model with a wor net, to see how a
wired or works. Finally, we create a new model by instantiating our old PLL and one
each of the ripple, synchronous, and behavioral counters in a single, top-level module
named ClockedByPLL; we end the lab by simulating this model.
Deliverables: Step 1: A correctly-simulating ripple counter and two synthesized
netlists, one optimized for area and the other for speed. Also, a record of the fastest clock
speed at which this verilog source model will count correctly. Step 2: The same as Step
one, but for a synchronous counter. Also, a dual-netlist simulation, using speedoptimized synthesized verilog netlists for the ripple-counter of Step 1 and the
synchronous counter of this Step. Step 3: A behavioral verilog counter, and netlists
synthesized for area and speed. A behavioral counter modified to count down and
simulated correctly. Step 4: The synchronous counter model of Step 2 with or gates (or
expressions) replaced by wor nets. Step 5: A correctly simulating model in which a PLL
instance supplies the clock to drive a ripple counter instance, a synchronous counter
instance, and a behavioral counter instance.

Supplementary Notes: Lab Procedure Update:

Testing counter speeds: Use
`timescale 1ns/10ps and check the VCS
waveforms on each negative edge of the clock:

Step 2. You will have to use different module names for the DFF's in the
synchronous vs. ripple counters, to get VCS to compile their synthesized netlists together
in the second part of this Step. The reason is that if "DFFC" is used to synthesize both
netlists, each netlist will have a declaration of a "DFFC"; and, the new VCS will reject the
idea of multiple declarations of the same module, even if both are identical.
So, begin this Step by copying your standard DFFC.v to a new name, for example,
DFF.v. In the new copy, change the module name to match that of the file, viz., to DFF.

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Then, use DFF, not DFFC, in your synchronous counter. If you do this, after synthesis
the ripple counter netlist will contain a declaration of a DFFC, and the synchronous
counter netlist will contain a declaration of an otherwise identical DFF; this resolves the
name conflict.

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35

Week 4 Class 1
Today's Agenda:
Lecture on strength, contention, and operator precedence
Topics: Verilog drive and charge strength, race conditions, and operator
precedence in expressions.
Summary: Verilog charge strength and drive strength are defined and ranked in
order to show how contention among different logic levels is resolved. Then,
race conditions which lead to contention are discussed. Finally, the
precedence of verilog operators is presented, so that the logic in complicated
expressions may be handled correctly.
Lab on strength and contention
Verilog drive strengths and race conditions are simulated. Some of this lab is
optional; if you have the Silos simulator provided with Thomas and Moorby or
Palnitkar, you should be able to do the optional parts at home.
Lab Postmortem
Simulation of contention.
Lecture on PLL synchronization
Topics: Named blocks, and behavioral and patterned extraction of serial clocks.
Summary: Named blocks are presented to provide means of terminating
execution of a procedural loop. Then, the general problem of transmitting a
clock with serial data is solved, for purposes of the class serdes project, by
specifying 32 bits of inert padding for every 32 bits of data transmitted. An
unsynthesizable behavioral (procedural) PLL is described as an optional
digression but is not used. The lecture leaves for lab the detailed development
of a patterned verilog solution for PLL clock extraction.
Lab on PLL synchronization
This lab exercises some sophisticated procedural code for serial clock extraction.
It then shows how a combinational-logic bit swizzle can be equally effective and
much simpler than a purely procedural solution.
Lab Postmortem
Extraction of a serial clock: How to deal with loss of synchronization?

Supplementary Note on assign/deassign, p. 116: Along with defparam, these

constructs are strongly discouraged in recent IEEE Std 1800 releases up through 2012
and are likely to be removed from future Std documents.

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Strength and Contention Lab 9

Topic and Location: Verilog three-state primitives, contention between different
drive strengths, race conditions, and bitwise vs logic operators.
Do the nonoptional work of this lab in the Lab09 directory. The Silos simulator may
be used at home for the optional Steps of this lab, a wire strength exercise. If you do
these optional Steps, you may want to bring in copies of your results and keep them in
Lab09 for synthesis in optional Step 5 and for possible later reference.
Preview: The optional Steps use two decoders in one module to apply all possible
pairs of verilog strengths, at opposite levels, to a single module output bit. A testbench
counter guarantees exhaustive exercise of all possible contentions. The lab returns to
nonoptional Steps with coding examples of race conditions. A final exercise shows the
important difference between bitwise and logical operators in verilog.
Nonoptional Deliverables: Step 1: A 4-to-1 decoder modelled by a case statement,
which handles unknown input bits and simulates correctly; then, two of these
implemented in one always block in a module named Netter. Step 6: A race condition
simulation model. Step 7: A simulation model showing the difference between '&' and
'&&' when applied to vector operands.
Optional Deliverables: Requires Silos or a similar old-style simulator. Step 4: The
Netter model from Steps 2 - 3, with all bufif1 outputs tied together to a single net,
driving a one-bit module output port. Step 5: A correctly simulating Netter model
demonstrating correct contention output; synthesized netlists for area and speed.

Supplementary Notes on drive strength, Section 7.1.1.1: There is a fifth drive

strength named highz (= weaker than weak), as shown in the table on p. 115 of the
Textbook. A net driven with a level 'z', as in the expression 1'bz, would be resolved to a
'z' (unknown) if also driven with a highz0 or highz1.
Drive strength applies only to net contention, when there is a connection of more than
one driver to a net; otherwise, the strength of a driver is irrelevant to the logic level being
driven. Although drive strength can be associated with a net when it is declared,
resolution of strengths only occurs when a net is driven by at least one continuous
assignment or verilog primitive gate. Module instance outputs always drive only with
strong strength.
Also, an unknown level can have any strength as a result of contention, depending on
the strength of the contending drivers. However, the usual logic level 'x' , as in the
expression 1'bx, always has strong strength, as indicated in the table.

Supplementary Note concerning Step 2: Netter should have a 4-bit input port

Sel[3:0] and a 1-bit output port named XYout. The simulation testbench should
include a 4-bit counter.

Supplementary Note concerning Steps 1 - 5: VCS will not simulate either the
verilog source or the synthesized netlists correctly for these Steps: For the source, VCS is
not designed to distinguish strengths in contention and simply will produce unknowns

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('x'). As for the netlists, DC does not synthesize gates capable of reliable resolution of
contention, and the synthesis libraries don't include such gates, anyway. Contention
almost always is an error in VLSI design, except only contention vs. 'z' -- which VCS and
DC handle correctly. The only reason for running VCS on the verilog source in these
Steps is for a good syntax check.

PLL Behavioral Lock-In Lab 10

Topic and Location: Reorganization of PLL modules; behavioral extraction of a
serial clock from a serial stream.
Work in the Lab10 directory.
Preview: We'll develop here some understanding which will help us later in our
serdes class project. We first copy over our PLL model from Lab08, renaming some
things and isolating the PLL from its Lab08 counters. Then, we'll edit a copy of the
FindPattern model (developed in the Textbook) so that it works to detect serial packet
boundaries in a faked, constant serial stream test pattern. We shall not yet hook the PLL
to the packet-boundary detector; extraction of the packet boundaries and thus of the
serial embedded clock will be completed later.
Deliverables: Step 1: A cleanly isolated and renamed PLLTop module representing
our fully functional PLL model of Lab08. Step 2: A correctly simulating counter clocked
by PLLTop. Step 3: A behavioral model which simulates correctly the extraction of our
packet boundary patterns for the fixed test-pattern serial stream supplied.

Supplementary Note concerning Step 3: FindPatternBeh is a simulation

model, only. It can not be synthesized.

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Week 4 Class 2
Today's Agenda:
Lecture on FIFO state-machine design
Topics: Tasks, functions, fork-join blocks, state machines, and FIFOs
Summary: After introducing tasks and functions, we describe the procedural
concurrency of the fork-join block. We then discuss the best use of verilog in
state machine design. After that, we describe operation of a FIFO in detail,
focussing on the read and write address controls. We end by describing how to
code a FIFO controller state machine in verilog.
Lab on FIFO design
After a warmup on tasks, a simple FIFO state machine is coded.
Lab Postmortem
FIFO design across clock domains; gray code counters.

Supplementary Note on tasks and functions. On Textbook p. 147, add a new

last paragraph to 8.1.1.1: "Statements to be run by a task or function must be placed
between its begin and end keywords. Local variable declarations (reg, integer, real)
must appear before the begin. A task exits, returning nothing, after its last statement
has been executed; a function returns the value assigned to its name (or, the last
expression assigned, if nothing is assigned to its name).

Supplementary Note on FindPattern.v on p. 149: See the end of todays notes.

Supplementary Note concerning fork-join. On Textbook p. 150, the two code

examples could be improved by substituting the following two:

Here, OutBusReg is updated 4 ns after clock, and the change in DataBus[3] is not
seen until the next clock:
always@(posedge Clk)
begin
#1 DataBus[0] <= 1'b0;
#2 DataBus[1] <= 1'b1;
#3 DataBus[2] = 1'b0;
#4 DataBus[3] <= 1'b1; // OutBusReg misses this one.
#1 OutBusReg = DataBus; // Updated after DataBus[2].
end

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With this fork-join, OutBusReg is updated with all changes 5 ns after clock:
always@(posedge Clk)
begin
fork
#1 DataBus[0] <= 1'b0;
#2 DataBus[1] <= 1'b1;
#3 DataBus[2] = 1'b0;
#4 DataBus[3] <= 1'b1;
join
#1 OutBusReg = DataBus; // Updated after DataBus[3].
end

Supplementary Note on the verilog FIFO, p. 160, add a new last sentence to the
second paragraph after the incrRead code example: "Another reason to encapsulate the
address increments in tasks would be to handle address wrap-arounds for a register file
with a number of words not equal to a power of 2."

FIFO Lab 11
Topic and Location: Task coding, and the design of a FIFO in verilog.
Do all work for this lab in the Lab11 directory.
Preview: We start off with a minor modification to add a task to a previously
completed module. Then, we code a useful, generic error-handling assertion, using a
task to make it easily available in any verilog design. After that, we code a simplified
verilog FIFO state machine controller based on today's lecture. Finally, we connect our
previously coded verilog RAM model to our state machine to make a fully-functional (but
imperfect) FIFO.
Deliverables: Step 1: A modified FindPatternBeh module, using a task to collect
repeated lines of code. Step 2: Simulation of a task containing the error handling
assertion specified. Step 3: A correctly simulating FIFO state machine controller (minus
register file), and. if DC permits, two synthesized netlists, one optimized for area and the
other for speed. Step 4: The same as Step 3, but with a register file attached.

Supplementary Note concerning Step 2. The example file containing the

ErrHandle code is named ErrHandleTask.v.

Supplementary Note concerning Steps 3C and Step 4. Ignore all synthesis

instructions: This first-cut FIFO will not synthesize because the latest version of DC
does not synthesize a task which contains an event control. Older versions reported a
warning but proceeded with synthesis. It also should be noted that this FIFO design is a
prototype and includes several design weaknesses which will be overcome later.

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============== FindPattern.v, as mentioned in the Textbook p. 149:

// FindPattern: Uses verilog code developed in the Textbook to search for and identify
// the frame pattern to be used in the SerDes design.
//
// For simplicity, a fixed 64-bit vector is searched for the pattern, rather than a
// real-time serial stream.
The vector is initialized and then kept constant.
//
// -----------------------------------------------------------// 2013-08-02 jmw: v. 1.0 Rewrote v. 1.6 of original FindPatternBeh.v to implement Textbook
//
Sect. 8.1.2 "Function for Synthesizable PLL Sync" solution.
//
The original Lab11 implementation apparently has been lost.
// ============================================================
//
`timescale 1ns/100ps
//
module FindPattern ( output Found, input StartSearch );
//
// If there's time, try changing this:
reg[63:0] VecHi =
/*
The numbers in this comment help identify bits in this vector:
*
'a'
pad 3
'b'
pad 2
'y'
pad 1
'z'
pad 0
*
60
50
40
30
20
10
0
* 32109876 54321098 76543210 98765432 10987654 32109876 54321098 76543210 */
64'b01100001_00011000_01100010_00010000_01111001_00001000_01111010_00000000;
integer PadHi = 7;
integer PadWid = 8;
integer AdrHi = 63;
integer OffSet = 63; // Just 64 bits in above testcase stream.
// The 4 x 8 = 32 bits predefined pad-bytes:
localparam pad_00 = 8'b000_00_000;
localparam pad_01 = 8'b000_01_000;
localparam pad_10 = 8'b000_10_000;
localparam pad_11 = 8'b000_11_000;
//
// The function, as in Section 8.1.2 of the Textbook:
//
function
checkPad (input[63:0] Stream, input[7:0] pad, input[63:0] iX);
reg OK;
// Flags pattern match
integer i
// i is the data stream offset.
, j; // j is the pad-byte pattern offsed.
begin
i = iX;
// Init to stream MSB to be searched.
OK = 0;
// Init to failed state.
begin : For // Capitalized, this is NOT a verilog keyword.
for (j = PadHi; j >= 0; j = j - 1)
begin
if (Stream[i] == pad[j])
OK = 1;
else begin
OK = 0;
disable For; // Capitalized: break the for loop.
end
i = i - 1;
end // for loop.
end // For.
checkPad = OK;
end
endfunction
//
reg FoundPads; // Flags successful find of 64-bit frame padding.
assign #1 Found = FoundPads;
//
always @ (posedge StartSearch)
if (
checkPad( VecHi, pad_11, OffSet - (1*PadWid) )
&& checkPad( VecHi, pad_10, OffSet - (3*PadWid) )
&& checkPad( VecHi, pad_01, OffSet - (5*PadWid) )
&& checkPad( VecHi, pad_00, OffSet - (7*PadWid) )
) FoundPads = 1;
else FoundPads = 0;
//
//
endmodule // FindPattern.

40

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// =======================================================
`ifdef DC
`else
module FindPatternTst;
//
reg StartSearchStim;
wire FoundWatch;
//
initial
begin
#0
StartSearchStim = 1'b0;
#5
StartSearchStim = 1'b1;
#100 StartSearchStim = 1'b0;
#5
StartSearchStim = 1'b1;
#100 $finish;
end
//
FindPattern FindPatternInst1( .Found(FoundWatch), .StartSearch(StartSearchStim) );
//
endmodule //FindPatternTst.
`endif

41

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Week 5 Class 1
Today's Agenda:
Lecture on rise-fall delays and the verilog event queue
Topics: Regular and scheduled delays, rise vs. fall, event controls, and the verilog
simulation event-scheduling queue.
Summary: We describe regular vs. scheduled (intraassignment) delay statements
inline in the verilog code, which represent gate-to-gate or module-to-module
delays, only. We then see how to specify different rise and fall delays, and
different delays for high-impedance, in these statements. After that, we look
into how the verilog language requires a simulator to queue up, evaluate, and
schedule assignments to variables. We finish with the two different verilog
event controls, '@' and 'wait'.
Lab
Delay statements and event scheduling.
Lab Postmortem
Q & A on the event queue, lab results, and some fine points on delays.

Supplementary Notes concerning types of delay expression. On p. 169 of the

Textbook, the last sentence before the code example refers only to procedural delays and
should say, "For procedural statements, the possibilities are,". What the Textbook
describes as scheduled delays are not allowed in continuous assignments.
Also, the Textbook terminology, "scheduled delays", is nonstandard; the IEEE Std 1364
(Section 9.7.7) uses intraassignment delays to refer to this construct.

Supplementary Note concerning multivalue wire delays. On p. 171 of the

Textbook, it is mentioned that the time to 'x' uses the shortest available delay, whether 2valued or 3-valued. More specifically, when the transition is from 'x', the specified delay
to the target level is used; only when the transition is from 'x' to 'z' and just two values
are given, the shorter delay is used.

Supplementary Notes concerning Textbook p. 172, it should be emphasized that

one cannot create contention with single procedural assignments, alone.
A. The first code example on p. 172 is irrelevant and should be replaced.
Instead of this example, consider the following one, which points out how blocking
assignments are affected by #0 delays. The following is poorly written and
unsynthesizable, but it is legal verilog:

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...
reg x, y, z;
//
always@(x) z = x;
always@(y) z = y;
//
initial
begin
z = 1'bz;
#2 x = 1'b0;
y = 1'b1;
#5 $finish;
end

The way that this is written, y will be updated to 1'b1 at time 2 after x is updated to
1'b0, which will leave z at 1'b1. However, changing the first always block to
always@(x) #0 z = x;
will cause z to be left at 1'b0 at time 2. Why should a zero delay do this?
B. The third example on p. 172 will not be simulated correctly by any simulator
available to the class. This is because modern designers rarely if ever write delayed
nonblocking assignments; so, modern simulators usually ignore the possibility and treat
delayed nonblocking assignments as delayed blocking assignments.

Supplementary Notes on section 9.1.2 concerning the stratified event queue.

A. Reading of always blocks. The concurrent always always causes its block to be
read. The verilog designer controls this behavior by using the '@' event control
immediately after the always to halt reading of procedural code until the event
expression is fulfilled by a change (or edge) in the signal(s) named.
In addition, to prevent the simulator from hanging up on every procedural event,
rereading of each always block is suppressed (disabled) in two main ways:
1. Rereading of all always blocks is disabled each time the active stratum is being
processed. Rereading is reenabled each time the simulator completes execution of all
events in the active stratum, before moving new events from other strata into the active
region.
2. Rereading of each always block is disabled while the statements in that particular
block are being read.
Concerning the second way, recall these examples:
always@(Clk) #10 Clk = !Clk;
Clk is updated while always is disabled; always only runs once.
always@(Clk) #10 Clk <= !Clk;
Clk is updated while always is enabled; always runs on every update.

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B. Initialization before simulation time is set to 0. In Figure 9.2, the block pointing to
the "set t = 0" block should say, "Read past [all] event controls fulfilled", not just levelsensitive ones. Statements not preceded by a procedural delay and controlled by edgesensitive event controls will be executed here. Use a #0 delay in an initial block to
ensure initializations which must be present at time 0 (this is the only use of #0 if one is
coding in the recommended style).
The corrected Fig. 9.2:

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Scheduling Lab 12
Topic and Location: Event scheduling by the simulator and rise-fall delay
statements.
Do this work in the Lab12 directory.
Preview: We start with a few simple puzzles, asking when different events will be
scheduled to occur. We then look into problems caused by mixing blocking and
nonblocking assignments. We revisit the Week 2 Class 1 latch-synthesis problems
caused by omission of variables from a sensitivity list. Finally, we look at statements to
schedule different delays on rising vs. falling edges.
Deliverables: The first three are observational and require no deliverable in fixed
form: Step 1: Eight answers to the questions posed. Step 2: Three answers. Step 3:
Simulation of the file provided; your comments on the results. Step 4: A synthesized
verilog netlist containing instances of the two modules provided. Step 5: A completed
module which simulates the statements given with the three delay values provided.

Supplementary Note on the answers provided: None was given for Steps 1 & 2;
see below. The other answers are somewhat expanded from those explicitly required in
the Textbook. Note that "rise" and "fall" refer to changes, not to initial assignments.
Step 1 SchedDelayA: First rise a = t 5; b = same. Last change a = t 6; b = same.
SchedDelayB: First rise a = t 0; b = same. Last change a = t 6; b = same.
Step 2 SchedDelayC: A. t = 1; B. Predictable (continuous assigns); C. a = 1'b1.

Supplementary Note on Step 4 latch inference. In the TSMC synthesis library

being used, latch components all are named beginning with an 'L'. For example, an
"LHQxx" in the netlist would be a transparent latch.

Supplementary Note on the Step 5 bus delays. According to the IEEE LRM,
1364-2005, vector assignments must be simulated with a single delay, not bitwise.
But, the LRM Section 6.1.3 gives this three-part rule for multivalue delays:
(a) If the RHS makes a transition to 0, the falling delay shall be used.
(b) If the RHS makes a transition to z, then the turnoff delay shall be used.
(c) In all other cases, the rising delay shall be used.
However, this rule is ambiguous, because "makes" can be interpreted bitwise or to
mean the numerical value in the vector. Both Aldec and VCS seem to treat vector delays
consistent with the numerical value interpretation: Thus, they require a numerical value
of 0 for case (a), all bits 'z' for case (b), and any other pattern for case (c). Other
simulators may use the transition on the LSB, only.

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Week 5 Class 2
Today's Agenda:
Lecture on verilog built-in gates and net types
Topics: Verilog built-in elementary gates, net types, implied wires, and a port
and parameter review.
Summary: A netlist consists of gate instances and wiring. Here, we enumerate
the elementary logic gates which are built into the verilog language, pointing
out their input and output port organization. We then enumerate all verilog
built-in net types useful in VLSI design, saving switch-level constructs for
later. We mention the `default_nettype control, and we then discuss the
rationale for verilog rules for mapping of net and reg types to a port. We point
out that parameter and delay values both may be preceded by '#' but that they
should not be confused.
Lab
We construct several verilog netlists by hand, and we simulate and synthesize
them.
Lab Postmortem
After general Q&A, we discuss synthesis results for our netlist counter vs one
built with behavioral flip-flops.

Supplementary Note concerning built-in gates on p. 185: The last paragraph

should make it clear that the built-in gates' port lists do not include names: Change the
first sentence of the last paragraph to: ". . .leftmost pin(s); they are not allowed named
port lists; and, they are allowed . . .".

Supplementary Note concerning pullup and pulldown gates. On Textbook p.

186, a new sentence should be added after the first one: "Representing a tap into one of
the chip power rails, the strength of a pullup or pulldown gate is source strength."

Supplementary Note on implied wire names, Textbook Section 10.1.2. Add a

new paragraph after the second code example on p. 186: "Implied wires (one bit wide,
only) also may be used to interconnect pins of instances in a netlist, thus permitting portmapping without explicit wire declarations.

Supplementary Note on structural use of wires, Textbook Section 10.1.4. It is

legal in verilog to drive an input port from inside the module, using a continuous
assignment statement to create an inside-outside contention. In other languages, such
as VHDL or SystemVerilog, driving a port declared as input is not legal except by
connection from outside the module.

Supplementary Note on port and parameter syntax in Textbook section 10.1.5,

p. 188: Add a new sentence just before the last one: "Also, the parameter declaration or
value-list always immediately follows the identifying module name."

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Netlist Lab 13
Topic and Location: We construct by hand several verilog netlists and simulate and
synthesize them.
Work in the Lab13 directory.
Preview: Using elementary combinational gates, we construct a netlist
representation of a D flip-flop, connect several of our flip-flops in a synchronous counter,
and simulate and synthesize the verilog to library gates. We also construct a similar
counter from behavioral D flip-flops, to compare the synthesis result.
Deliverables: Step 1: A correctly simulating model of a D flip-flop consisting of a
hand-entered netlist of verilog primitive combinational gates. Step 2: A correctlysimulating synchronous counter created by replacing the behavioral D flip-flops of the
Synch4DFF Lab08 exercise with your flip-flops of this Step 1. Step 3: Four synthesized
netlists: One each, optimized for area and speed, from the old Synch4DFF counter and
from your new counter made from structural D flip-flops.

Supplementary Note on Step 3 optional netlist simulation. The optional last

operation should be tried with the speed-optimized Synch4DFFGates netlist, only. You
may wish to try simulation with and without SDF back-annotated delays. Recent
versions of DC should produce a working netlist with simulation timing from our training
library (tcbn90ghp_v2001.v); however, SDF timing may be required.
If you run the netlist simulation with correct timing, you will be able to zoom in VCS to
see the SR latch's internal process of reset: For example,
4'b1111 --> 4'b0111 --> 4'b0101 --> 4'b0100 --> 4'b0000.

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Week 6 Class 1
Today's Agenda:
Lecture on procedural control and concurrency
Topics: Procedural control constructs, procedural concurrency, and verilog name
space.
Summary: We deepen our understanding of the procedural control constructs
forever, repeat, while, case, and the use of the case equality operator.
We also study casex and casez, but we warn against them. Then, we change
topic somewhat to revisit procedural control of concurrency by fork-join
blocks. We end with a few new observations on the scope of verilog names.
Lab on concurrency
After exercises in common procedural control constructs, we design a watchdog
device which runs concurrently with the CPU it guards.
Lab Postmortem
We review the problem of casex and devise a bubble-diagram for our watchdogCPU design.

Supplementary Note on the CheckToggle examples of pp. 203 and 206. These
examples are to illustrate task instance concurrency and are not synthesizable; they do
not exemplify good modelling. A simpler and better way to solve the bit-checking
problem concurrently and synthesizably would be,
// Use bit-selects:
always@(InBus[0]) TempToggledReg = 2'h0;
always@(InBus[1]) TempToggledReg = 2'h1;
always@(InBus[2]) TempToggledReg = 2'h2;
always@(InBus[3]) TempToggledReg = 2'h3;
always@(posedge CheckInBus) #1 ToggledReg = TempToggledReg;

A procedural solution, using a for loop over InBus[i], i = 0 to 3, also would be

efficient and synthesizable.

Supplementary Note on the example at the top of p. 206. The error message in
the code example comment, as well as part of the last paragraph on p. 205, are wrong: It
is not an error; a variable declared in an always block will retain its value between block
executions.
VCS will simulate the example at the top of p. 206 correctly as an up-counter. It
should be mentioned that ClockCount is local to the named always block and can't be
accessed directly by simple name; it can be accessed from outside the Ticker always
block by hierarchical name, as will be studied in the next Chapter.
The last paragraph on p. 205 should be rewritten thus:
"Notice in the next example that the count will be preserved, even though the counter
storage was declared local to the always block."

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Concurrency Lab 14
Topic and Location: Procedural control constructs, concurrency in procedural code,
and a watchdog-CPU design.
Do this lab in the Lab14 directory.
Preview: We do a few elementary exercises with forever, repeat, while, and
case. Then, we take on a fairly complex design which requires concurrent execution of a
watchdog device and another device, in this case a CPU.
Deliverables: Step 1: A simple module containing a correctly simulating forever
loop. Step 2: The same design with a repeat loop added. Step 3: The same design
with a while loop added. Step 4: A new, small design of an encoder implemented with a
case statement. Step 5: A correctly simulating design containing a minimal emulation
of a CPU and a concurrently-running watchdog.

Supplementary Note on Step 5, Fig. 11.2, p. 208: The "t" in the various
"t_(command)" actions stands for task. It is suggested that each "t" action be
implemented as a separate task instance; however, the assignment (p. 209, B) only
requires one task to be used.

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Week 6 Class 2
Today's Agenda:
Lecture on hierarchical names and generate blocks
Topics: Hierarchical names, arrayed instances, compiler macroes vs. conditional
generates, looping generates.
Summary: We lay groundwork by presenting in detail the rationale for
hierarchical names in verilog. We then show how to create arrays of instances
wherever a single instance could be used, assuming the connectivity is fairly
simple. After that, we introduce the generate statement. First, we discuss
the conditional generate, which may be compared with conditional
compilation using verilog macro definitions. Next, we discuss the unique
looping generate, which allows creation of arrays of instances, and of wiring
of any complexity among them. We expand on the looping generate construct
by stepping through the design of a very large decoder.
Lab
After brief exercises in arrayed instances, we use generate to design a RAM,
which we then substitute into our previous FIFO design.
Lab Postmortem
We discuss indices in arrayed instances and generate; then, we compare the
effect of writing a certain generate block three different ways.

Supplementary Note for p. 214, summarizing the two kinds of generate:

Conditional generate: (a) Modifies design structure and thus possibly functionality;
(b) No unrolling of instances or of structure involved.
Looping generate: (a) Creates new design structure; (b) Multiple levels of loops are
allowed; (c) Unrolled by synthesizer; like arrayed instances; (d) More flexible than
arrayed instances; may include any concurrent statement (but not a nested
generate block).

Supplementary Note on the generate examples on p. 215. The generate and

the conditional compilation examples use port mapping by position in order to fit on the
printed page; this is not a recommended design practice. They also assume that the
Mux32bit module has been declared with an unused input port for Ena; this would make
it possible for unused wiring in the module to be connected and not dangling. Equally
valid would be the following example, which assumes that other conditional generates
in the module have eliminated or rerouted the Ena wire:
localparam Latch = 1;
. . .
generate
if (Latch==1)
Mux32bit Mux01 (OutBus, ArgA, ArgB, Sel, Ena); // As in Textbook.
else Mux32bit Mux01 (OutBus, ArgA, ArgB, Sel);
endgenerate

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Supplementary Note on Figure 12.4, p. 218. To clarify the scope of the

generate, there are eight instances each of a DFFa, a not, and a bufif1 generated. An
improved figure would be as follows:

Supplementary Notes on the RTL code on p. 220. Two comments on the RTL
decoder model at the top of this page: (a) The block name, Decoder, is not required; and,
(b) the delayed blocking assignment causes the delays to accumulate, so that
AdrEna[1023] is not assigned until 1024 ns after each Address change. Another good
reason not to put delays in procedural code. Also, keep in mind that the delays in the
preceding generate example are structural, not procedural.
A different and efficient way to implement a large decoder procedurally would be,
parameter NumInputs = 10;
parameter NumOutputs = 1<<NumInputs;
input[NumInputs-1:0] Address;
reg[NumOutputs-1:0] AdrEna;
//
always@(Address)
begin : Decode
AdrEna = 'b0;
#1 AdrEna[Address] = 1'b1;
end

This does not match the generate loop structure, but it does not cumulate delays.

Supplementary Note on Figure 12.7, p. 221. The heavier arrow paths represent
enables, not addresses.

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Generate Lab 15
Topic and Location: Synthesis comparison of arrayed instances and generated
instances; coding of a RAM using generate; and, use of a generate'd RAM in a FIFO.
Work in the Lab15 directory, and be sure to save the results of Step 1 and Step 2
separately, so they can be compared in Step 3.
Preview: First, we ensure that the alternative construct, arrayed instances, can be
used by doing a small design from the Textbook with them; we save synthesis results for
later comparison. Next, we do a very similar design using generate, again saving
synthesis results. Then, we compare area and speed optimizations for one of the designs
previously synthesized. After these warm-ups, we provide requirements for a new RAM
design which is to be coded using generate. Once this RAM has been simulated
superficially, we include it in a FIFO (from a previous lab) and simulate and synthesize
the result.
Deliverables: Step 1 and 2: A synthesized netlist. Step 3: Two synthesized netlists,
one optimized for area and the other for speed. Step 4: A correctly simulating RAM
design, according to requirements given in the lab instructions. Step 4: A correctly
simulating FIFO which uses the generated RAM of Step 3; also, two, and, optionally,
three, synthesized netlists of the FIFO design.

Supplementary Note concerning Step 1. The example is the second code

example on p. 219.

Supplementary Note concerning Step 2. The example is the code example on p.

217.

Supplementary Note concerning Step 3. On p. 225, for speed optimization,

instead of the Textbook instruction to use "no area constraint", set the area to 0 and run
the compile with a -map_effort high option.
Supplementary Note concerning Step 4, pp. 225 - 226. To clarify the purpose of
Steps 4C - 4E:
Step 4C: Use flip-flops to generate a memory word storing 33 bits.
Step 4D: Use Step 4C memory words to generate a 4-word memory.
Step 4E: Be sure that both generates (4C and 4D) are under control of
parameters, not literal constants.

Supplementary Note on Figure 12.10, p. 226. The Textbook recomments

starting with a four-word RAM, as shown. In the Textbook, the decoder connected to
Write_Addr is drawn for simplicity as though clocking the flip-flops. However, for
accuracy, a clock should be shown supplied to the decoders, which gate the clocks to the
flip-flops. The clock inputs to each of the flip-flops are relatively unimportand and can
be ignored here.

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A better representation would be to show the flip-flops with the enable inputs (see Lab
4; Week 1 Class 2) which would be supplied by the decoders:

Supplementary Note concerning Step 5, pp. 228 - 229. After the simulation, the
rest of this Step is a set of exercises on synthesis constraints.
Also, the last sentence in Step 5, on p. 229, perhaps should repeat the reason why the
FIFO netlist at this point is incorrect: Among other things, the FIFO state machine
includes tasks with event controls; this causes DC to skip entirely any synthesis of the
FIFOStateM module.
One final comment: A single, full synthesis of this FIFO, with or without generate
assistance, very likely would take a considerable time to finish, perhaps more than an
hour on a fast machine. This means that synthesis of this FIFO alone, which generally
would be expected to require multiple reruns to tune the size and gate speeds, might take
a week or more and probably would not be as good as a commercially available IP model.

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Week 7 Class 1
Today's Agenda:
Lecture on serial-parallel conversion (deserialization)
Topics: Generic requirements for serial-parallel conversion; uses of functions and
tasks.
Summary: We briefly discuss serial-parallel conversion as a generic problem and
then move on to specific the usefulness of verilog functions and tasks in
simplifying this kind of conversion. Continuation of our serdes class project is
reserved for the lab work.
Lab on serial-parallel conversion
We first do two related, generic deserializer designs; then, we move on to recall
our serdes class project. We implement a first cut on the required Deserializer
module of our project.
Lab Postmortem
We discuss reusability issues of our class serdes deserializer.

Supplementary Note concerning Textbook p. 233: Verilog function

declarations are not allowed to contain nonblocking assignments.

Supplementary Note concerning Textbook p. 236: In the header for Section

13.2.1, the abbreviation "ECO" stands for Engineering Change Order and is used widely
in the industry. On a big project, design changes have to be approved by the authority
issuing the ECO. An ECO is a formal modification (update or correction) to the design
specifications.

Serial-Parallel Lab 16
Topic and Location: A generic serial-parallel converter, a modification sensitive to
bit-patterns in the serial stream, and a first-cut at the Deserializer module of our class
serdes project.
Do this work in the Lab16 directory.
Preview: We first do two related, generic deserializer designs: A generic serialparallel converter which ignores content of the incoming serial stream, and then a
modification of it which requires use of bit-patterns in the serial stream to control
functionality. After the generic designs, we move on to coding what will become the first
cut at the Deserializer of our serdes class project.
Deliverables: Step 1: A correctly simulating deserializer which converts an incoming
serial stream to registered (parallel) 32-bit words. Step 2: A modification of the Step 1
design which controls the deserialization process based on serial content. Step 3: A
correctly simulating Deserializer which produces registered 32-bit words from a serial
stream arriving in the packet format required by our serdes project.

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Supplementary Note on function and task, p. 234. In the second code block, the
"ParValidReg" is the same as the "ParValidFlagr" of the second code block on the
previous page. The Unload32 task briefly lowers the ParValid flag each time it
updates the parallel bus.
The same always block calls the task and lowers the ParValid flag on reset; this is
consistent with synthesizer requirements, although any delay on an assignment in the
task will be ignored by the synthesizer.

Supplementary Note on the Lab Preface, p. 235. It is crucial to understand the

two clocks involved in the deserialization. The PLL comparator's two clocks are:
1. The PLL's own 32 MHz free-running serial clock, which is divided down to 1 MHz
for input to the ClockComparator; and,
2. The DesDecoder's 1 MHz clock, created by toggling on extracted packet
boundaries from the incoming stream of serial data.
If the two 1 MHz clocks were perfectly in phase, deserialization could be perfect.

Supplementary Note on Lab Step 1. On p. 238, the generic deserializer

description is the one in section 13.1.1.

Supplementary Notes on Lab Step 3. In the paragraph on p. 240 beginning

with "The synchronization loss . . .", the last sentence should be revised to read, "Either
way, synchronization loss should have no effect on ParClk: In this lab Step, your
DesDecoder should include an oscillator which runs freely at exactly 1 MHz and is
(re)synchronized whenever a packet has been identified. You may test your
deserializer's resynchronization by varying slightly the serial input rate from your
testbench." In our SerDes class project, eventually we will design a PLL which contains
a free-running oscillator performing the same function as this oscillator, but with an
adaptive frequency.
The next (third from bottom) paragraph on p. 240 is meant to say, "Deserialization
should be halted whenever synchronization is lost; at this point, incompletely deserialized
data (fewer than 32 bits) should be discarded. Deserialization should be resumed with
the first data byte following resynchronization. Resynchronization may be by either of
the preceding two criteria previously described -- your choice: Either (a) because the
sequence of four successive pad-byte counts is correct; or, (b) because a good pad_00 was
detected 64 bits after the previous (good) pad_00."
The last paragraph on p. 240 should end with the following: "Otherwise stated, there
should be a testbench serial clock SerClk, but the deserialization should be done solely
on a 1 MHz clock extracted from the serial data stream. Instead of a PLL-generated 32MHz clock, provide your own 32 MHz clock ( = SerClk) directly to the DesDecoder, and
let the DesDecoder extract its own 1 MHz clock. If you want to serialize parallel data in
your testbench, to supply the DesDecoder, just create a 32-MHz clock in your testbench
and feed it to a counter to create a 1 MHz clock, which of course, then, will be perfectly in
phase with SerClk."

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Week 7 Class 2
Today's Agenda:
Lecture on UDPs, timing triplets, and switch-level models
Topics: User-defined primitives, timing triplets, switch-level primitives and nets,
trireg nets.
Summary: We present the basics of verilog user-defined look-up table primitives
(UDPs) and how to use them for simple component modelling. We then pass to
a review of two- and-three-value delay specifications to introduce the second
dimension of delay timing, the min:typ:max triplets which may be used in
place of single delay values anywhere. We then enumerate the switch-level
primitives and explain their drive strength parameters. We end with the
switch-level trireg net, which may be used to model decay transition time of a
capacitor.
Lab
We model a combinational and sequential UDP first; then, we model several
devices at switch level, including a trireg delay line.
Lab Postmortem
Q&A, and two little questions.

Supplementary Note on delay pessimism. On p. 246, the paragraph on

"Functional edges" also should mention that when a '1' or '0' occurs before any other level,
the change will be a negedge or posedge event, respectively. Changes strictly between
'x' and 'z' are level-sensitive events but are not edge events.
The first paragraph on p. 247 of the Textbook is incorrect and should be ignored. The
delay from an 'x' to another level is given by the delay to that level; pessimism does not
apply. Unspecified delays involving 'z' are treated the same way as those involving 'x'.
Likewise, the last few sentences in the last paragraph on p. 247 should be changed to:
"For changes involving 'x' or 'z', the simulator may proceed "pessimistically": A delay to
'x' or 'z' uses the shortest (= most pessimistic) specified value. A recovery from 'x' or 'z'
uses the delay as ordinarily specified."

Supplementary Note on Section 14.1.4: Switch-level primitives. Switch-level

primitives, like UDP's, are not synthesizable.
Supplementary Note on charge strengths. The table on Textbook p. 250 is from
IEEE Std 1364 Table 7.7 and gives some properly-named strengths, with *0 or *1 names;
these strengths are used to resolve contention. The charge strengths are applied only
to trireg net declarations, and they generally are written without a level: large,
medium, or small.
Tools should refuse to accept charge strength declarations such as "(strong1,
medium0)" when the level is appended. This is because, according to IEEE Std 1364,
Section 4.4.1, the only legal use of charge strengths is for declaration of trireg nets.
Incidentally, the default strength of a trireg net is medium.

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Supplementary Note on the cmos switch primitive, pp. 250 - 252. Because a

cmos is a superposition of a pmos and an nmos, a reasonable,

functionally correct, schematic representation would be as
shown in the Textbook, p. 251, Figure 14.2, but without the
inverter.

Viewed in terms of the analogue electronics, this would

make a cmos a pass gate without any amplification and with
some finite resistance. In digital logic, there is no such thing
as resistance, and a cmos would drive its output in simulation
with the same strength as its input.

A
cmos switch

However, when used in a gate such as an inverter, the elements of a cmos would be
rearranged so that the pass-gate "input" and "output" were connected between supply
and ground, as shown in Textbook Figure 14.3. In this arrangement, the inputs of the
pmos and nmos switches would be tied to the power supply rails. The output of such an
arrangement then always would be at strong strength, because, differing from the
Textbook rules on p. 150, switches always reduce supply strength inputs to strong
output strength.

Supplementary Note on trireg nets. On p. 253, Section 14.1.5, add a new last

sentence to the paragraph beginning, "A delay value may be assigned . . .": "A
generated or arrayed structure including trireg nets thus could be used to model the
refresh behavior of a dynamic RAM."
Also, in the paragraph beginning, "If a trireg net has no delay, . . .", add a new
sentence before the last one: "This resembles procedural behavior and so explains the
peculiar name, trireg, of this construct."

Component Lab 17
Topic and Location: UDPs, switch-level models, trireg models.
Do the work for this lab in the Lab17 directory.
Preview: This lab does not involve any synthesis. We start by modelling a
combinational UDP and then a sequential UDP. We model a switch-level inverter using
n and p MOS switches. We examine a cmos switch. Next, we model a mux using pass
transistor switches. We complete our study of switch-level components by modelling
simple nand and nor gates. We simulate a delay line built on trireg nets.
Deliverables: Steps 1 and 2: Correctly simulating UDP component models. Step 3:
A correctly simulating MOS-switch inverter component. Step 4: The Step 3 model with
a cmos output added; a completed lab truth table for the cmos. Step 5: A mux built
from pass transistor switches and simulated correctly both with tranif and rtranif
primitives. Step 6: A module containing a correctly simulating switch-level model of a
nand and a nor gate; a second version of this module using the Step 3 switch-level
inverter to create and and or gates. Step 7: Two versions of a trireg pulse-delay line,
one with rnmos primitive components, and the other with rtran primitive components.

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Supplementary Note for revision of Step 7. First of all, this Step should be
optional.
The Textbook Step 7 uses delays which do not clearly present the behavior of this
design. Also, VCS currently (2009) never will simulate triregs correctly when
connected to rtrans; so, the waveforms shown in Textbook Figs. 14.9 and 14.10 should be
ignored.
Instead, use the schematic given in Fig. 14.8 modified by replacing the small trireg
driven by the input buffer with a large trireg. Change the delays as follows, naming
the triregs Tri01 - Tri04, from left to right:
Name
Tri01
Tri02
Tri03
Tri04

Drive Strength
large
large
medium
small

Delay
(19, 23, 50)
(21, 29, 53)
(9, 13, 17)
(5, 7, 11)

These delays will make the expected simulation easier to understand; however, VCS
(2009) will not simulate this design correctly. Assigning a delay of 1 to each rnmos, the
generally expected result would be as follows:

With rnmos switches, each with delay of 1, and with Ena = 1:

If In goes from x to 0, Out will be 1'b0 after 23+1+29+1+13+1+7 = 75.
If In then goes to 1, Out will be 1'b1 after 19+1+21+1+9+1+5 = 57.
If In then goes to 0, Out will be 1'b0 after 23+1+29+1+13+1+7 = 75.
(a) If In then goes to x, Out will be 1'bx after 19+1+21+1+9+1+5 = 57.
(b) If In stays 0 and Ena goes to 0:
Tri01 -> 1'bx@50 (this is the one decay delay)
=>Tri02->1'bx@51+21=>Tri03->1'bx@73+9=>Tri04->1'bx@83+5.
So, Out will be 1'bx after 88.
Resistance happens to be of no importance here -- just the delays. The delay of the input
bufif1, if not zero, should be added to those above.
The result of a Step 7 simulation in VCS is similar to the one in the Textbook and is
shown below, followed by several QuestaSim simulation details. Again, it should be

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emphasized that QuestaSim is an enhancement of an older tool (ModelSim) which was

widely in use long before synthesis became a major goal of gate-level design.

Revised Fig. 14.9: VCS simulation of RCnet, with rnmos components (incorrect -- output oscillates).

Revised Fig. 14.10: VCS simulation of RCnet, with rtran components (incorrect).

The QuestaSim simulator (v. 6.5 of 2008) does a better job with switch-level constructs:

Revised Fig. 14.9: QuestaSim simulation of RCnet, with rnmos components (overall view).

Further details on the QuestaSim simulation follow:

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Revised Fig. 14.9: QuestaSim simulation of RCnet, with rnmos components (buffer disable closeup).

Revised Fig. 14.9: QuestaSim simulation of RCnet, with rnmos components (buffer reenable closeup).

Revised Fig. 14.10: QuestaSim simulation of RCnet, with rtran components (buffer disable closeup).

60

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Revised Fig. 14.10: QuestaSim simulation of RCnet, with rtran components (buffer reenable closeup).

61

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Week 8 Class 1
Today's Agenda:
This time we'll do some review of parameters and parameter passing. We'll also look
into some problems concerning design hierarchy.
Lecture on parameter types and module connection
Topics: Parameter types, port and parameter mapping, and defparams
Summary: We examine in some detail the typing of parameter declarations, and
ANSI and traditional port and parameter mapping. We mention defparam, a
construct to be avoided, and localparam, a construct devised to prevent use of
defparam.
Connection Lab
We exercise port and parameter declarations, as well as a hierarchical design
comparing `defines with parameters to parameterize bus widths.
Lab Postmortem
We look into possible confusion of parameters with delays in component
instantiation.
Lecture on hierarchical names and design partitions
Topics: Hierarchical names, verilog identifiers, design partitioning, and
synchronization across clock domains.
Summary: We review and extend our coverage of verilog hierarchical names,
generalizing to a discussion of the scope of identifiers in verilog. Then, we
present various criteria which might be used to decide how a design should be
partitioned into modules and module hierarchy. We dedicate some of the
discussion to the problem of data which crosses independent clock domains and
the related problem of how to synchronize the clocking of such data.
Hierarchy Lab
We experiment with hierarchical truncation and extension of mismatched bus
widths. Then, we use a small design to see the benefit of latching module
outputs.
Lab Postmortem
We point out a conflict between rules of thumb (a) to use continuous assigns to
lump module simulation delays and (b) to latch all outputs.

Supplementary Note on sized parameters. p. 261: Declaring a parameter with

an index range is required if the parameter is to be used in a verilog concatenation
expression: Concatenations must have an explicit width.

Supplementary Note on parameter overrides. p. 262: Whether a module header

has been declared in ANSI or traditional form, any parameter declared within a module
can be overridden in instantiation, the same way as parameters in the header. This is
another good reason to use localparam declarations for parameters not intended to be
overridden.

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Supplementary Note on defparam. Section 15.1.7, p. 262: This construct has

been retained in IEEE Std 1364, but its use has been discouraged in all Std versions
through 1364-2012. As explained in the Textbook, defparam should be avoided: Use
parameter or localparam instead.

Connection Lab 18
Topic and Location: Traditional and ANSI port mapping, instantiation of parameter
overrides, hierarchical comparison of `define vs parameter override.
Do this work in the Lab18 directory.
Preview: We start with a simple exercise in reformatting a module header. Then, we
do a few simple but perhaps unusual parameter overrides. After that, we view in VCS
the hierarchy in a skeleton design with configurable bus widths, first using `define and
then using parameters.
Deliverables: Step 1: A compilable rewrite of a traditional-port module. Steps 2 - 4:
Compiling versions of a design with various parameter overrides. Step 5: Compilation of
the given design with macro bus widths in correct order. Answers for the two questions
asked. Step 6: A compiling rewrite of the design of Step 5, but with parameter overrides
in place of `defines.

Supplementary Note concerning Step 2. To bring up two hierarchy windows in

the new VCS gui, to match the old-VCS figures shown in the textbook, first set up the one
shown on the left, more or less arranged the same way and displaying the same data.
Then, open a second hierarchy window by opening [Window]/[New Top Level
Frame]/[Hierarchy + Data] and double-picking NANSI_01 in the hierarchy.
The result should resemble this:

Also, as is visible in the preceding figure, the new VCS gui will display parameters
and their values. In addition, to see the values in the [Data] window pane, it is
possible just to pick [] in the "Value" column.

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Supplementary Note concerning synchronization in Fig. 15.7. p. 272: This

figure can be interpreted most simply as a representation of an oscilloscope display,
showing a transition between '0' and '1' of a typical receiving gate. Increasing the
horizontal sweep speed spreads out and flattens the voltage trace. No matter what the
applied voltage, in a short-enough time interval, the voltage will have negligible effect in
moving the potential of the gate from '0' to '1' or vice-versa. Thus, no transition will
occur in a short-enough interval. If such a transition-less input is clocked (say, as the D
input of a flip-flop), the receiving device's Q may not be able to change state quickly.
We assume that an independently-running clock has provided an input data value of
intermediate, indeterminate digital value. Viewed as a representation of a data input
voltage near the input gate balancing point, for a high-enough clock frequency, no
reasonable potential will be able to move the output either to a '0' or a '1' before the next
clock.
There is an equivalent geometrical, statistical interpretation: At a low clock
frequency, the input data will be sampled very rarely near the balancing point in any
given interval of time. At low frequency, the slope of the transition curve, its rate of
movement away from the balancing point, will be very high, as indicated in the leftmost
t0 interval. At a higher frequency, say 100 times higher, the slope at t1 will be 100
times less, and at 10,000 times the original frequency, the slope will be approaching zero,
as shown in the interval t2. In effect, the voltage applied to clock in a distinct digital
value will be reduced approximately proportionally to the frequency.
Thus, whatever the balanced-error rate at frequency f0, this rate will grow with
increasing frequency f approximately as f/f0.

Hierarchy Lab 19
Topic and Location: Bus routing in a module hierarchy, synchronization across
clock domains.
Do this work in the Lab19 directory.
Preview: We create a skeleton hierarchy of module ports and then see how bus-width
mismatches are handled across hierarchical boundaries. We then write a testbench
which clocks two 3-bit counters at different clock speeds. We examine glitching across
the two clock domains and see how latched outputs ameliorate the glitching problem,
even in a digital simulator which has no capability to represent different voltages.
Deliverables: Step 1: An empty hierarchy acceptable to the simulator compiler.
Step 2 - 5: Answers to the questions, checked by the simulator. Step 6: A correctly
simulating ClockDomains testbench.

Supplementary Note concerning Step 3. On Textbook p. 274, if you followed

the instructions, the design now would have two top-level modules, Wide and Narrow, in
the order shown in Step 1. Even though Narrow will have been made impossible in Step
3 as described in the Textbook, new VCS will issue no error and simply will ignore
Narrow while compiling Wide correctly.

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To make this example work and get a fatal error from new VCS, before performing
Step 3, instantiate Narrow in Wide, mapping the Narrow output port to OutWide and
the Narrow input port to InWide.

Supplementary Note concerning Step 4. Before starting this Step, comment

out the Narrow instance which you added in Wide according to the preceding Step 3
Supplementary Note.

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Week 8 Class 2
Today's Agenda:
Lecture on verilog configurations
Topics: Libraries and configs.
Summary: We explain the relation of a library to a design and enumerate the
major keywords for a config. There is no lab exercise or example available
because of lack of vendor implementation.
Lecture on timing arcs and specify delays
Topics: Timing arcs within modules, specify blocks, path and full delays.
Summary: We build on the library concept to cover verilog delays within a
module, especially a module for a library component. We elaborate on the use
of lumped vs distributed delays on a path. We present specify blocks and
their delay statements, including specparams, leaving timing checks for a
later class.
Lab
We study details of specify-block delays, concentrating on resolution of conflicts
among overlapping paths. We write out an SDF file after a synthesis.
Lab Postmortem
We discuss simulation of conflicting delay specifications.

Supplementary Notes on specparams, p. 286. Add a new sentence to the end of

the paragraph beginning, "When creating . . .": "The reason that this is a good practice is
that specify blocks are used in models of small devices; the specparams then would be
named for specified performance parameters on a datasheet for such a device."

Although a parameter may be referenced to define a specparam, it is illegal in verilog

to reference a specparam to define a parameter.
Also, although the Textbook mentions in Section 16.2.4 that a specparam may be
assigned a multivalued delay of the form "(x,y,z)", the IEEE Std 1364, Section 4.10.3,
merely states that a specparam may be assigned "any constant expression". So, before
defining a specparam with multivalued delays, check your tool for the implementation.

Supplementary Notes concerning path delays, p. 287.

A. In Section 16.2.5, although the discussion refers only to "ports", a specify block
equally may reference nets within the module.
B. On p. 287 and following: Because specify blocks often are used in simulation
models of library components (which themselves never are synthesized), six or more
delays on a path occasionally may be required. Also, the special level of simulation
timing implied by numerous conditional delays might be useful in switch-level modelling,
but it primarily would be applied in high precision gate-level models or models of small IP
blocks.

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C. A new last paragraph on p. 287 should be added: "For paths on which delay
pessimism must be overridden, up to twelve different delays are allowed, counting to- and
from-x as well as to- and from-z. See the next Section."

Supplementary Notes on conditional and edge-dependent path delays. In

Section 16.2.6, p. 288, it should be mentioned that, although individual statements which
are conditional can not include logical alternatives, a specify block default may be
assigned for paths in a module for which the stated conditions and edges do not apply.
This default is introduced by the ifnone condition. For example,
specify
if (!Clr) (posedge Clk *> Q,Qn) = (3, 4);
if (!Clr) (A, B *> Q, Qn)
= (5, 5);
...
ifnone
(A, B *> Q, Qn)
= (1, 2); // For Clr asserted.
endspecify

It is illegal in verilog to assign an ifnone condition to a path also covered by an

unconditional delay statement.

Supplementary Note concerning multivalue delays on p. 289. In the last

paragraph before 16.2.7, keep in mind that overriding delays to 'x' or 'z' prevents the
simulator from applying the principle of delay pessimism previously introduced (Week 7,
Class 2). The syntax of multipath delays is given in IEEE Std 1364, 14.3.1, as well as in
the Thomas and Moorby section cited in this last paragraph.

Supplementary Note concerning specify conflicts, Sections 16.2.7 and 16.2.8, p.

289: It should be emphasized that an SDF delay, if applied, supersedes and replaces any
of the kinds of delay described here.

Timing Lab 20
Topic and Location: Path delays and conflicts; SDF for a netlist.
Do this work in the Lab20 directory, using the verilog provided.
Preview: We use a small hierarchical design to study assignment of delays to
component internal paths. We especially show how delays on multiple paths, potentially
conflicting, are resolved in simulation. We synthesize a netlist and write out SDF to see
the effect of the specify delays.
Deliverables: Step 1: A testbench counter for the SpecIt design which compiles in
the simulator. Step 2: Correctly simulating distributed and lumped delays in SpecIt.
Step 3: Various correctly simulating delays using a specify block in SpecIt. Step 4:
A correctly simulating full-parallel path conflict, using specparams in a specify block.
Step 5: Simulation and synthesis delays, and SDF delays, for a SpecIt netlist.

Supplementary Note concerning Step 4B. p. 292: The instruction to "Use only
rise and fall delays" just means not to use posedge or negedge expressions.

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Week 9 Class 1
Today's Agenda:
Lecture on timing checks and pulse controls
Topics: Relation to assertions, the twelve verilog timing checks, pulse filtering
and delay pessimism.
Summary: This will complete our study of timing issues in verilog, as well as of
the allowed contents of a specify block. We start by discussing the
relationships among timing checks, assertions, and system tasks. After
introducing the time-stamp/time-check rationale, we present the 12 timing
checks and their default arguments. After describing conditioned events and
timing-check notifiers, we explain verilog simulator pulse handling, inertial
delay, the PATHPULSE task, and pessimism reduction in the specify block.
Lab on timing checks
We exercise the timing checks and pulse-filtering features of specify blocks.
Lab Postmortem
We entertain a Q&A session only, this time.

Supplementary Notes on $setuphold (p. 298) and $recrem (p. 299) advice to

see "below": These references are to Textbook section 17.1.4 on negative time limits.

Supplementary Note on $recovery and $removal. p. 298 f.: To clarify the

difference, $recovery pertains to an asychronous control event and the next clock edge
following it; the timestamp is on the asynchronous control. Contrariwise, $removal
pertains to the clock edge immediately preceding an asynchronous control event; the
timestamp is on the clock.
Thus, Figure 17.1 should be corrected as follows:

Supplementary Note concerning the data checks. p. 300: The $nochange

timing check has been implemented in later releases of VCS (e. g., v. 2008-09).

Supplementary Note concerning pulse filtering. p. 303: In the alternatives (a)

and (b), a simpler statement of the results would be as follows:
(a) the pulse is wider than the error limit: The delay is imposed on the output, with
the input width preserved;

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(b) the pulse width is between the error limit and the rejection limit: The leadingedge delay is imposed, and the output changes as though the input pulse had
been narrowed to a width equal to the rejection limit; or,
(c) [as-is].
p. 304: Figure 17.5: Some readers may find this figure simpler with the time scale
reversed, as follows:

Supplementary Note concerning improved pessimism. p. 305: None of

pulsestyle_onevent (the usual default behavior), pulsestyle_ondetect,
showcancelled, nor noshowcancelled seem to be implemented in any commonly-used
simulator. Example usage is shown in the SystemVerilog (2012) section on "Negative
pulse detection".

Timing Check Lab 21

Topic and Location: Timing checks and pulse filtering.
Work in the Lab21 directory. A subdirectory named PLLsync has been prepared for
you there; it contains the entire PLLsync design from Lab10 (Week 4 Class 1).
Preview: We start with our old, unsynthesizable PLL design, not to continue the
serdes project, but to use it as an example for the lab. After seeing how it runs for a long
simulation, we add a specify block to the design so we can install timing checks. We
use the PLL to study timing checks for the very common setup and hold constraints, as
well as recovery, removal, width and period. We then switch to a simpler D flip-flop
design, add a specify block to it, and systematically study pulse filtering and all the
timing checks in the language runnable by our simulators.
Deliverables: Steps 1 - 4: specparam-controlled $setup, $hold, $recovery, and
$removal checks simulated in PLLsync. Step 5: $width and $period checks
simulated in PLLsync. Step 6: Various simulations of a D flip-flop (DFFC), with
PATHPULSE filtering controls. Steps 7 - 10: Various timing check simulations, using
DFFC.

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Supplementary Note concerning Step 6. p. 307: In this Step, new VCS will
print a warning for each PATHPULSE error, as well as displaying an 'x' in the waveform.
Also, a $nochange timing check has been added for this Step in the Lab21_Ans
directory, just to show what the message looks like.

Supplementary Note concerning Step 8B. p. 309: To clarify the third sentence,
the reference to "10 ps" is to the clock period, not the half-period delay in the clock
generator.

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Week 9 Class 2
Today's Agenda:
Lecture on sequential deserializer of our serdes
Topics: Redesign of PLL for synthesis. Blocks to complete for the Deserializer.
Summary: The "sequential" Deserializer is because our FIFO doesn't yet have a
dual-port RAM; reads and writes have to be mutually exclusive (sequential; not
concurrent). We review the status of our project and decide to complete the
Deserializer block in the next lab. In the current lab, we prepare by
redesigning the PLL to make it synthesizable and then setting up a new,
permanent directory structure for the FIFO, PLL, and Deserializer components
(the deserializing decoder and serial receiver).
Lab on first-cut Deserializer
Much of the work is in renaming and connecting blocks. However, we spend
some effort in redesigning our PLL so it will operate about the same as before
but will be synthesizable. We connect the PLL and our (single-port RAM)
FIFO and then set up a divide-by-two clock for parallel data. We then connect
the serial input in a testbench and simulate. In addition to redesigning the
PLL, we make many small modifications to everything else. Finally, we
synthesize for an idea of the design size and speed.
Lab Postmortem
We focus on synthesis constraints and don't worry about the design functionality
at this time.

Supplementary Note on the VFO Figs. 18.2 and 18.3, p. 313: Keep in mind that
our VFO both (a) receives an external 1 MHz ParClk and (b) generates its own internal
~32 MHz ClockOut.

Supplementary Note on the library delay cell, p. 314, 3rd paragraph: Rewrite
the first sentence to say, ". . . available as the simple, small, noninverting delay-cell
buffer DEL005 in our synthesis target library . . .".
Supplementary Note on the ClockComparator. p. 316: To clarify the abstract

example's relation to the SerDes class project, a new paragraph should be added after the
code example: "The VarFreq vector, of course, will be the same as ClockCounterN,
controlled by the AdjFreq output of the ClockComparator block."

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Sequential Deserializer I Lab 22

Topic and Location: Completion of a first-cut Deserializer; synthesis.
Work in the Lab22 directory.
Preview: We reorganize and update our PLL design to make it synthesizable. We
copy in our old PLL, FIFO, and old Deserializer files and organize them so they may be
used easily throughout the rest of the serdes project. We install parameters for block
reuse. We do considerable port renaming and other, minor modifications to connect all
our previous blocks. We simulate when the Deserializer has been assembled fully;
and, finally, we do some serious synthesis, attending to design rules and constraints.
This is a long and complex lab, realistic in what it does but more verbose than the
usual commercial design process.
Deliverables: Step 1: A reorganized and renamed PLL design in its own
subdirectory, Lab22/PLL. Step 2: A synthesized-netlist simulation attempt proving
that the old PLL is not correctly synthesizable. Step 3: A redesigned PLL which
simulates correctly. Step 4: A netlist simulation verifying that the new PLL synthesizes
correctly.
Step 5: A new Deserializer.v and DeserializerTst.v, file in Lab22, with
sketched-out ports and parameters as described.
Step 6: A parameterized and correctly simulating FIFO module in Lab22/FIFO, with
a testbench in a separate file.
Step 7: Two new subdirectories, Lab22/DesDecoder and Lab22/SerialRx, with
contents and instantiations described, capable of being loaded into the simulator.
Step 8: A divided-by-two parallel-output clock generator in Deserializer.
Step 9: Completion of SerialRx by instantiation of the PLL; connectivity checked by
loading into the simulator.
Step 10: A correctly simulating DesDecoder, slightly modified from a previous lab
and with a testbench in a separate file.
Step 11: An expanded DeserializerTst testbench in Lab22 which allows some sort
of simulation of a completed Deserializer instance. Step 12: A Deserializer which
correctly simulates some sort of storage and retrieval of data in the FIFO, and which can
pass on some sort of serial data for parallelization.
Step 13: Two synthesized netlists of this first-cut Deserializer, one optimized for
area and the other for speed.

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Supplementary Note concerning Step 1. p. 324: At the end of Step 1, your

completed testbench should be somewhat like the one in the Lab22_Ans subdirectory for
Step 2:
`include "Deserial.inc"
module PLLTopTst;
reg ClockStimIn, ClearStim, SamplePLLr;
wire PLLClockWatch;
//
always@(ClockStimIn)
#`HalfPeriod32BitBus ClockStimIn <= ~ClockStimIn;
//
always@(posedge ClockStimIn, posedge ClearStim)
begin : Sampler
if (ClearStim==1'b1)
SamplePLLr = 1'b0;
else begin
#50 SamplePLLr = 1'b1;
#100 SamplePLLr = 1'b0;
end
end
//
initial
begin
#0
ClearStim
= 1'b0; // #0 only required if 1'b1 init.
#0
ClockStimIn = 1'b0; // ditto.
#1
ClearStim
= 1'b1;
#9
ClearStim
= 1'b0;
ClockStimIn = 1'b1; // Forces a phase change.
#465
ClearStim
= 1'b1;
#500
ClearStim
= 1'b0;
#50
ClearStim
= 1'b1;
#500
ClearStim
= 1'b0;
#25000 $finish;
end
//
PLLTop PLL_U1( .ClockOut(PLLClockOut), .ClockIn(ClockStimIn)
, .Sample(SamplePLLr), .Reset(ClearStim) );
//
endmodule // PLLTopTst.

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Supplementary Note concerning Step 4. p. 325: A complete schematic of the

synthesizable PLL might be helpful here:

Fig. 18.14a. Block-level schematic of the synthesizable PLL, with connection details. Some Reset lines omitted.

Supplementary Note concerning Step 5. pp. 325-327: The Deserializer of

this step was introduced in Fig. 13.4 of Textbook p. 238 and Fig. 18.1 of Textbook p. 312.

Supplementary Note concerning Step 6. pp. 327-328: The parameters AWid

and DWid not only simplify a great deal of the code in the FIFO modules, but they also
make it more convenient to change the size of the various FIFO elements; for example,
they make it easier to change the FIFO size to one of 8 or 16 words instead of 32 -- or to
change the FIFO word size from 32 to 16 or 64 bits.

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Supplementary Note concerning Steps 7 - 9. pp. 328-332: These steps include

some extremely detailed instructions. In part, especially in Step 7, they suggest a
general approach to the rearrangement, duplication, and renaming of multiple module
instances. This approach may be useful whenever redesign of a system including large,
multiple instances becomes necessary.
For the rest of this course, we shall be providing detailed instructions which, for
literal implementation, would be quite time-consuming. These instructions are
intended primarily to provide important reading and coding experience for users with
little prior practice in writing verilog or SystemVerilog.
If the reader wishes to skip this part of the lab, it would be reasonable to read the Step
9 Supplementary Notes (just below) and then replace all Lab22 data entirely by copying
the Lab22_Ans_Step10 contents to the working Lab22 directory, saving only the
Lab22_Ans directory and the Deserializer.sct and tcbn90ghp_v2001.v files
already there. After the replacement, it would be a good idea to spend some time
reading all the new .v, .vcs, .sct, and .inc files before jumping ahead to Step 11.

Supplementary Notes concerning Step 9. pp. 331-332: The end of the first
sentence in the 2nd paragraph of p. 331 of this Step might be better phrased as, ". . .
design module; keep the testbench module, which originally was at the bottom of the file."
p. 332: In Step 9, the last bulletted paragraph, after the code example, there is a
reference to "if (SerValid==YES)": This simply should be "if (SerValid==1'b1)".
The "YES" is taken from my answer code for the DesDecoder, in which "localparam
YES = 1'b1;" is defined. Later, in Lab24, Week 10 Class 2, both "YES" and "NO" will be
defined as part of the exercise and located in a new include file, SerDesFormats.inc.
The actual readability value of these words is minimal, but they do show how parameters
can be used to conceal the literal values of numerical constants. The FIFO state
machine state codes and the packet pad values are other, better, examples.
p. 332: Add a new last sentence to Step 9: "Further modifications to make the
DesDecoder synthesize correctly will be done later in the course."

Supplementary Note concerning Step 10. The new VCS may produce a first
working source simulation with different output values than those shown in the
Textbook.
Also, the on-disc answers for this Step include some changes in the source verilog
(different from the Textbook CD) which have been made to prevent the new VCS from
setting certain signals to 'x' where the old VCS did not. The main change is to comment
out the FIFO state machine assignment of 1'bz to the ReadCounter when the FIFO is
in its empty state.

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Supplementary Note concerning Step 11. pp. 333-335: In the on-disc answers
given, loose-end Step A, p. 333, was done already by Step 10.
The specific data I/O values in the on-disc answers will differ from those in the
Textbook (p. 334) for the new VCS. For example, the first valid word out with new VCS
might well be 32'h0573_8705, as shown in the next figures, corresponding not-quitecorrectly to the ParWordIn value 32'h0573_870a at simulation time 61,947 ns.

The New VCS display of the first operating Deserializer.

Zoomed-in view of the New VCS Deserializer output (not quite correct).

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Week 10 Class 1
Today's Agenda:
Lecture on concurrent deserializer lab
This brief lecture merely introduces the lab, which includes simulation and
synthesis, the latter primarily as a verification tool.
Lab
We debug our first-draft Deserializer and make many small changes to modify
the memory so it will operate as a dual-port. We change our FIFO state
machine so it can take advantage of the dual-port memory.
Lab Postmortem
We stop for Q&A and discuss a few verilog debugging techniques.

Supplementary Note concerning the concurrent Deserializer: The schematic

of Fig. 19.1, p. 337, may be compared with that of the sequential Deserializer in the
lower half of the schematic of Fig. 18.1, p. 312. The PLL which is displayed on p. 312 as
PLL_RxU1 in Deserializer.v/*SerialRx_U1 is especially noteworthy.
The clock speed for the FIFO's is 1/2 MHz, as was mentioned in the Textbook at
several previous points and is detailed on p. 133 (Week 4 Class 1). Two clocks at 1-MHz
means (1 MHz)/2 = 1/2 MHz per FIFO clock.

Supplementary Note concerning dual-port memory: On Textbook p. 338, a final

paragraph should be added to Section 19.1.1: "A dual-port memory need not have two
different clocks, but it must provide simultaneously for two different memory addresses."

Concurrent Deserializer II Lab 23

Topic and Location: Dual-ported RAM and concurrent FIFO read and write
controls.
We'll work in the Lab23 directory this time.
Preview: We push down our old Lab22 Deserializer into a subdirectory for this lab, in
anticipation of having a Serializer next-door later in the course. We check for obvious
bugs in the first-cut Deserializer FIFO, and then we modify the FIFO memory for
dual port operation. After the memory works for simultaneous read and write, we
change the FIFO state machine so it can honor simultaneous read and write requests.
We then modify the FIFO design further, and the DesDecoder, so that the
Deserializer can be synthesized and be more or less functional.
Deliverables: Step 1: Copy of the Lab22_Ans Deserializer, checked by load into
the simulator. Step 2: Correctly simulating FIFO at corner cases. Step 4: Modified
RAM model (DPMem1kx32), now dual-ported, checked by load into simulator. Step 5:
Independent read & write for most of DPMem1kx32. Step 6: Some general
improvements. Step 7: Correctly simulating empty, full, and normal state FIFO
controller, for simultaneous FIFO read and write. Step 8: A FIFO which simulates

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correctly both in source and as a synthesized verilog netlist. Step 9: A correctly

synthesizable DesDecoder. Step 10: A synthesizable complete Deserializer.

Supplementary Note concerning Step 2. On p. 340, the filename listing, and the
sentence following, mention "default.cfg": New VCS does not use this file; instead, it
saves state in a .tcl session script.

Supplementary Note concerning Step 3. On pp. 340 341, this Step mostly is
preliminary discussion. The one important change in this Step is to wire ChipEna
permanently high; the changes which actually will enable simultaneous read and write
are in Step 4.

Supplementary Note concerning Step 4. In p. 341, next-to-last paragraph,

AddrR means "Read Address", and AddrW, "Write Address".
Change the wording of the p. 342 last sentence in the
second paragraph after Figure 19.4 to be, ". . . output latches,
reconvergence (Week 1 Class 2, Section 2.3.5) of the internally
gated clocks will not be a concern."
Also, replace Fig. 19.3, p. 342, with the one on the right,
which has "ClkW" spelled correctly:
As explained on p. 343, our new naming convention means
that anythingReg will be renamed to anythingr.
After completion of this Step, the FIFO states will simulate
the same way in both old and new VCS without modification.

Supplementary Note concerning Step 5. On p. 344, first and second lines of

text, "references" are the identifiers (module names) in the files in the Deserializer
directory. It should be noted that the read-address task shown is unsynthesizable
mainly because of its "@(posedge ClkR)" control.

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Supplementary Note concerning Steps 7 - 8. On p. 346 ff., the common

organization of each state in the FIFO state machine combinational block will be as
follows, keeping in mind the transition limitations of the empty and full states:
always@(*)
...
case (CurState)
...
stateX: begin
1. Check for read & write requests.
Update read & write addresses.
Issue memory read & write commands.
2. Check for updated addresses.
Assign NextState.
end
stateY: begin
...
endcase

Supplementary Note concerning Step 8B. On p. 349, making the state clock
generator synthesizable is a problem. Using the receiving-domain clock as the state
clock would work but would risk a variety of machine race conditions on certain sendingdomain clock phases.
Using "always@(ClkR, ClkW) StateClockRaw = !StateClockRaw; " would not
synthesize correctly, because neither ClkR nor ClkW are used in the statement. To avoid
danglers, hypothetically one might try using any available edge on either domain, as in,
"always@(posedge ClkR, negedge ClkR, posedge ClkW, negedge ClkW)". However,
event controls using both edges of the same variable are not synthesizable.
The "!(ClkR && ClkW)" solution in the Textbook reduces the clocking problem to one
of glitch filtering. Some experimentation shows that a plain and, "(ClkR && ClkW)",
actually works better than the book nand; so, this is used in the lab answers. However,
any logical operation does imply that for certain very improbable ClkR vs. ClkW phases,
the state clock would stop -- temporarily, assuming that at least one clock could drift in
phase. Watchdog logic could avert this, but why complicate this FIFO, which is a
training exercise, further?

Supplementary Note concerning Step 8C, pp. 350 - 355: New incrRead and

incrWrite blocks are developed on pp. 351 & 352; their purpose is to replace the original
and unsynthesizable @(posedge Clk) statements in the old incrRead and incrWrite
of FIFOStateM.v. The use of the new blocks, minus their deleted fork-join's, is
shown on p. 353.
After completion of the changes in this Step, we have a clocked "combinational" state
machine block, but with blocking, not the usual nonblocking, assignments. This is so
that the statements in this block still are updated in order as they are run. The usual
setup and hold functionalities of nonblocking assignments in a simple clocked model are

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not relevant here, because we can be confident that everything will have settled to its
final condition by the time the next posedge of StateClock arrives.

Supplementary Note concerning Step 8C optional synthesis, p. 354: New DC

(ca. 2010) will take only 15 minutes but the netlist will not simulate correctly unless SDF
timing back-annotation is used. The next two figures show the SDF simulation
waveforms.

Overall view of the new DC netlist simulation (with SDF timing back-annotation) of Step 8C.

Closeup of the Step 8C simulation.

The FIFOTop.sct file for this Step contains suppress_message* statements. These
shorten the screen and .log report warning messages as we increase design and .sct
complexity. Otherwise, eventually, the warnings would consume all the .sct runtime
screen display, making error messages disappear.

Supplementary Note concerning optional Step 8D, p. 355: Depending on

synthesis constraints, the DesDecoder ParClk may stay stuck at 1'b0. Also, whether
the training-library (tcbn90ghp_v2001.v) or SDF delays are used will determine the
exact way that the netlist simulation fails.

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The Decode4 task, rewritten as a negedge always block, may be done this way:
always@(negedge SerClock, posedge Reset)
begin : Decode4
if (Reset==YES)
begin
DecodeReg = 'b0;
doParSync = NO;
SyncOK
= NO;
UnLoad
= NO;
end
else begin : PacketFind // Look for packet alignment:
UnLoad
= NO;
doParSync = NO;
if ( FrameSR[7:0]==PAD0 )
begin : FoundPAD0
SyncOK = YES;
if ( FrameSR[23:16]==PAD1 && FrameSR[39:32]==PAD2
&& FrameSR[55:48]==PAD3 )
begin // All pads indicate all frames aligned:
DecodeReg = { FrameSR[63:56], FrameSR[47:40]
, FrameSR[31:24], FrameSR[15:8] };
UnLoad = YES;
end
else // Found a PAD0, but rest failed; so, synchronize:
begin
doParSync = YES;
SyncOK = NO;
end
end // FoundPAD0.
end // PacketFind.
end

As mentioned previously, for variety, in the above always block we write YES (=1'b1)
or NO (=1'b0).
The procedural complexity of this decoder requires blocking assignments. By
generating the parallel clock on a posedge of the serial clock and using all DesDecoder
results only on the negedge, race conditions easily are avoided.

Supplementary Note concerning Step 9, pp. 355 - 357. This Step is important;
and, except for the "fancy" localparam expression on p. 357, it should not be considered
optional.

Supplementary Note concerning Step 9, p. 357. The new Unload32 block

mostly differs from the original by including assignments to the new ParValidTimer.
Supplementary Note concerning optional Step 10. The latest DC (Feb 2010)
synthesizes a netlist in about 45 minutes which will simulate poorly but correctly without
SDF back-annotation; however, some 2008 and 2009 DC versions would not succeed with
any constraint set discovered by the author.
In your on-disc answers for this lab, there is a directory named OldDC_GoodNetlist
which contains files which were synthesized by an older version of DC (2007). You can
use new VCS to simulate the old netlist correctly: If you do this, you will be able to see
that the ParOutWatch value 32'h3cf1_1979 was serialized from the input at about
time 251,737 ns.

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Because each Deserializer main subblock (FIFO, PLL, and DesDecoder) now
synthesizes correctly, a mixed RTL-netlist simulation of the entire design is possible by
putting together the synthesized subblock netlists instead of trying to synthesize a single
netlist from the whole verilog design. For a mixed simulation, you may leave
Deserializer.v and SerialRx.v in source form and create a new
DeserializerSubNets.vcs file containing this:
DeserializerTst.v
Deserializer.v
./DesDecoder/DesDecoderNetlist.v
./FIFO/FIFOTopNetlistSDF.v
./PLL/PLLTopNetlist.v
./SerialRx/SerialRx.v
-v tcbn90ghp_v2001.v

The answers for this Step include synthesis scripts to synthesize the subblocks. With
current (2010) versions of DC, the SDF timing only is required for FIFO; the other
modules will simulate without back-annotation.
In the .sct file mentioned above, you will notice a considerably increased number of
detailed assignment statements, along with an (expected) increased number of
supress_message* statements. The increase in complexity is normal as the design
increases in complexity, which causes correct synthesis to require more and more
complex and detailed constraints.

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Week 10 Class 2
Today's Agenda:
Lecture on the Serializer and SerDes
Topics: Serializer submodules, assembly and checkout of the SerDes.
Summary: The brief lecture is used to outline the functionality of the
SerEncoder and the SerialTx, and to point out the reorganization of the
project files.
Lab
The Serializer model is completed, and it is attached to the Lab23
Deserializer to form a complete serdes. We simulate and synthesize the
result.
Lab Postmortem
We look into possible incompatibilities of our Ser and Des. We also question
where assertions and timing checks should be installed.

SerDes Lab 24
Topic and Location: Design and simulation of a Serializer; assembly, simulation,
and synthesis of a serdes.
Do this work in the Lab24 directory.
Preview: We reorganize our files from previous labs so that the PLL, FIFO,
Deserializer, and new Serializer are in the same working directory. Then, we
design the Serializer to share packet pad definitions and otherwise to be compatible
with our Deserializer. We connect the Deserializer and Serializer together
with a single serial wire, and we demonstrate correctness by simulation.
Deliverables: Step 1: Copied previous Lab23 answer files. Step 2: Reorganized
design files as shown by successful load into the simulator. Step 3: A correctly
configured and assembled Serializer, to the extent of successful load into the
simulator. Step 4: Completed connections for the SerialTx. Step 5: Completed
SerEncoder. Step 6: A correctly simulating Serializer. Step 7: A correctly
assembled, completed serdes project. Step 8: Synthesized, simulated unit netlists for
the completed serdes' PLL, FIFO, DesDecoder, and SerEncoder.

Supplementary Note concerning Lab24 Step 1. On p. 363, in the top paragraph,

the "unit test" files are the testbench files for the individual modules in FIFO, PLL, and
DesDecoder.

Supplementary Note concerning Lab24 Step 3. On p. 364, the code example

named "SerDesFormats.inc" again introduces various localparams which in general
provide a naming advantage for the PADs but not much advantage for 1'b1 or 1'b0.
On p. 365, first paragraph, ParInClk should be connected to both FIFO clock inputs.

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Supplementary Note concerning Lab24 Step 7. On p. 368, before connecting the

Serializer and Deserializer instances and simulating, use VCS to verify that the
unconnected Serializer and Deserializer hierarchies, now residing in SerDes, are
as expected (shown in the next figure).

The unconnected hierarchies.

The connected hierarchy.

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In new VCS, using the on-disc answers, the deserialized packet with data
32'h462d_f78c appeared on the parallel-data input bus at time 28,598 ns:

Overall Step 7 source simulation of the SerDes.

85

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Closeup of the Step 7 source simulation, showing the output just described.

Supplementary Note concerning Step 8. The DesDecoder, SerEncoder, and

PLL netlists should take less than 20 minutes each on a 1 GHz machine, without holdfixing.
Synthesis in new DC of a good FIFO netlist took over 12 hours on a 1 GHz machine;
the long run was because of the special need explicitly to fix hold times (as well as the
usual setup times). By compiling with hold-fixing but without design rules, a good
synthesis of the FIFO block should take less than a half-hour.
See the Lab24_Ans *.sct files for details. Especially relevant to a quick FIFO
synthesis is FIFO/FIFOTop_Hold_wDesRule.sct., which is refered to in the first new
paragraph ("Likewise . . .") on p. 370.

Supplementary Note concerning Step 8, optional part on p. 370. Using the

latest DC, ignore the Textbook instructions to simulate with the zero-timing
tcbn90ghp.v training library; instead, use the tcbn90ghp_v2001.v library. The
latter library includes delays which will be overridden by SDF timing wherever available.
The DC-generated SDF omits some delays, so a few paths in the netlist still require
nonzero timing, which will be supplied by default by tcbn90ghp_v2001.v.

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Supplementary Note: New Optional Step 9 (not in Textbook). If you performed

the optional part of Step 8 in which you created SDF files for each major component of
the SerDes, you can quite easily simulate the entire SerDes hierarchy in a mixed RTLnetlist configuration. This would be how any large design would be synthesized and
simulated during development.
To do this, create a SerDesSubNets.vcs file with the following contents:
./SerDesTst.v
./SerDes.v
./Serializer/Serializer.v
./Serializer/SerEncoder/SerEncoderNetlistSDF.v
./Serializer/SerialTx/SerialTx.v
./Deserializer/Deserializer.v
./Deserializer/DesDecoder/DesDecoderNetlistSDF.v
./Deserializer/SerialRx/SerialRx.v
./FIFO/FIFOTopNetlistSDF.v
./PLL/PLLTopNetlistSDF.v
-v tcbn90ghp_v2001.v

The *SDF.v netlist files are the ones with $sdf_annotate(), which you used during
the optional SDF-based simulation in Step 8. The other files are unsynthesized verilog
source -- they could be synthesized hierarchically to netlists and then editted for
individual use, but this would be somewhat time-consuming and unnecessary, in view of
the fact that they are simple enough to assume that synthesis easily would have created
netlists which would simulate successfully.
During simulation of the design subnetted as above, the new VCS command window
will report the SDF annotation as follows:

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An example of the overall SerDes waveform display is as follows:

The two time markers are set at 567,572.27 ns, when parallel data word
32'h22d500c5 was clocked out of the Ser_U1 FIFO, and at 745,427.73 ns, when that
word was clocked onto the Des_U1 ParOut bus.
The next figure is a closeup of the time around which the 32'h22d500c5 word arrived
on the Des output:

There remain a few netlist glitches, but the SerDes clearly is operating more or less
correctly.

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Week 11 Class 1
Today's Agenda:
Lecture on DFT
Topics: Basics of DFT, observability, coverage, boundary scan, internal scan, and
BIST.
Summary: After introducing DFT as a methodology, we relate it to assertions
and then explain the terms, observability and coverage. We then introduce
boundary scan, internal scan, and BIST as the major DFT techniques.
Lab 25 on DFT
We recall an optional Lab05 insertion of internal scan by the synthesizer and also
show how to attach I/O pads in a verilog design for automated synthesizer
insertion of boundary scan. We put a memory in a wrapper and attach a BIST
module to it.
Lab Postmortem
We discuss the effect of the BIST on memory die size.
Lecture on full-duplex SerDes
Topics: Implementation parameters for connecting two of our SerDes into a fullduplex lane.
Summary: We give special FIFO depth requirements for our full-duplex system,
and we discuss addition of DFT functions.
Lab 26 on a DFT, full-duplex SerDes
After putting together a working, full-duplex serdes, we add assertions, timing
checks, and automated internal scan.
Lab Postmortem
We discuss the effect of the scan elements on SerDes size.

Supplementary Note concerning corner cases, p. 378. In Section 21.1.5, an

instructive article on setup and hold corners in a netlist is the one by Bansal, et al, cited
in the References near the beginning of these Notes.

Supplementary Note concerning boundary scan and internal scan, pp. 379 - 382.
These were introduced briefly in Week 2 Class 1, in Textbook Section 3.1.8, and in Lab05
pages 50 - 59.

Supplementary Notes concerning internal scan, p. 381. In the caption to Fig.

21.3, the scan clock may be considered identical to the clock shown.
Also, the final paragraph on p. 381 refers to "unobservable" gates; these, of course,
would be nonfunctional ones such as those discussed in the preceding paragraph.

Supplementary Notes concerning BIST. On p. 383, add new paragraphs and a

figure after the first paragraph, as follows:
"There is a variety of ways to implement BIST and BISR (Built-In Self Repair) of onchip memories. For repair, the usual way is to manufacture the memory with one or two
spare rows (addressable words) or columns (bit-offsets within all words), depending on

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the hard error rate expected. Then, BIST is run during manufacture to identify defective
bits. Knowing the location of the defects, if any, the tester programs a within-chip or
within-board register with the spares to be substituted. Then, either the spare row(s)
and column(s) are substituted by permanent "burned-in" logic, or on-chip logic is
programmed dynamically by shifting in a substitution configuration (as in programming
an FPGA)."
"Defects are rare enough so that almost all memories can be repaired by substitution of
just one or two spare rows or columns. The next figure illustrates the statistics for this:"

The graph (a) is for a typical memory with 0.002 defects/mm 2; graph (b) is for a defect rate 1/10 as great.
The upper curves show the improvement in BIST pass rate gained by having one spare row or column
available vs. none; the lower curves show the improvement by having two spare rows or columns vs. just
one. Clearly, there is little expected benefit in providing for more than two spare rows or columns.
The statistic is Yield/Area. After figure 7 of the Mentor Memory Repair Primer of November 2008.
Reproduced with permission of Mentor Graphics, Inc.

Also, in the next-to-last paragraph in Section 21.1.8, the last sentence should say, ". . .
soft errors caused by the Solar wind and cosmic rays . . .".

Scan and BIST Lab 25

Topic and Location: Automated internal scan review; automated boundary scan
insertion; manual BIST design, insertion, and synthesis.
Do these exercises in the Lab25 directory.
Preview: We recall our Lab05 optional automated scan insertion exercise and now
complete it, if it was not done during Lab 5. We then manually add I/O pads to the old
Intro_Top design in order automatically to insert boundary scan elements. After this,
the lab is dedicated to attachment of a BIST module to our DPMem1kx32 RAM: We decide
on the BIST test protocol and then detail how to create a wrapper module to enclose the
RAM and BIST, and the test interface. We then implement the BIST by using a supplied
"IP" BIST module and synthesize the result.

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Deliverables: Step 1: Completed Step 9 of Lab05. Step 2: A modified Intro_Top

design with boundary scan automatically synthesized. Step 3: A synthesized netlist for
the RAM module alone. Step 5: A wrapper module correctly connected as verified by
load into the simulator. Step 7: Completely connected Mem and BIST modules, as
verified by load into the simulator. Step 8: A correctly simulating, completed memory
with BIST. Step 9: A synthesized netlist of the memory with BIST, to be compared in
size with the one from Step 3.

Supplementary Notes on Lab 25:

Step 2A. On p. 384, the pad model wrapper file is tpdn90g18_3PAD.v, which

should have been symlinked in the VCS directory to tpdn90g18tc_3PAD.v. The CDROM (misc directory) version, tpdn90g18tc_3PAD_NonTSMCProprietary.v, also
should work as well; it may be copied to the VCS directory (and may be renamed to
tpdn90g18tc_3PAD.v).

Step 2C. The detailed instructions on p. 384 are to provide some experience with
inserting and connecting pads in a design; they may be skipped if such experience is
unnecessary. At the end of this Step, you may simulate the design if you wish. It
should function as the familiar Intro_Top of previous labs; however, the undriven
ScanOut pad output will remain unknown.
Step 2D. On p. 385, the TAP controller can be implemented by means of DC
commands too time-consuming for this course. The final netlist can be simulated
without TAB; however, the scan-mode scanned output data will not be meaningful.
VCS can be used to view the netlist schematic: Select "Topper01 (Intro_Top)" in
the control window hierarchy view, and then pick the "and gate" icon just above. This
may take a minute, but the result will be better-arranged than the one from
design_vision. Tool details are in your DC_Synth_Lab01_Summary.pdf handout.
The remainder of this lab exercise includes some detailed file rewriting. If the
user is not planning to work with BIST development and has sufficient experience with
verilog, Steps 3 - 8 may be skipped to conclude with the Step 9 synthesis exercises. In
any case, it would be instructive to read the Lab25_Ans answers provided for all the
steps of this lab.

Step 6. On p. 389, ClkRw and "Resetw" are named "*w" because they have been

declared wires.

Step 8. On p. 390, the second-to-last paragraph suggests rewriting some of the

provided answer as a task. If you do this, your task may be called under as many as six
different test conditions, using the test number as the (single) task input.

Step 9. Using the latest 2011 version of DC, synthesis of the memory with BIST and
with timing constraints but without set_fix_hold, takes about 15 minutes on a 1 GHz
machine; the resulting netlist simulates correctly with the approximate delays given in
tcbn90ghp_v2001.v.

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Tested SerDes Lab 26

Topic and Location: A full-duplex serdes; addition of assertions and timing checks,
synthesis of the netlist, and synthesizer insertion of internal scan.
Work in a new subdirectory of the Lab26 directory for these exercises. The
instructions will say how to name files and subdirectories in it.
Preview: We first implement a full-duplex serdes by instantiating two of our previous
unidirectional SerDes. We use parameters to size the FIFOs at the two ends of the lane
differently, emulating different system characteristics. Once the instances are
connected, we simplify their interfaces to accommodate the full-duplex lane, which we
synthesize. We make a new copy of our fully functional SerDes, and, after adding an
assertion pro forma, we insert a few timing checks and experiment with them to tune
them according to the desired SerDes performance. We then make a second new copy in
which we use the synthesizer to insert internal scan.
Deliverables: Step 4: Fully connected and parameterized full-duplex instances, as
proven by loading into the simulator and examining the hierarchy. Step 5: A simulating
copy of the full-duplex SerDes, with FIFO-warning assertions. Step 6: Four timing
checks in DesDecoder, tuned properly by simulation as described in the lab procedure.
Step 7: A synthesized, constrained netlist for the original SerDes (without assertions or
timing checks). Step 8: A new SerDes netlist with internal scan inserted automatically
by the synthesizer.

Supplementary Notes on Lab 26:

This lab again includes considerable file rewriting, which may or may not be
instructive to a user already skilled in verilog. Steps 1 - 4 may be skipped, using the
provided Step04_FullDup answer to run the SerDes simulation described in the last
two paragraphs of p. 398.
After this simulation, if skilled in the use of verilog assertions and timing checks, the
user may read the Step 5 and Step 6 instructions carefully and then simulate a new copy
of the SerDes, with assertions and timing checks, the copy being made from the answer
in Step06_FullDupChk.
Steps 7 and 8 of this lab are new and important and should not be skipped.

Step 3: On p. 395, in the middle of the second paragraph after the second code
example, the cautionary sentence is meant to be read as, "Do not rename the FIFO
parameter; just change the name of the value assigned to it in SerDes.v. For example,
in SerDes.v, 'Serializer #( .DWid(DWid), .AWid(AWid) ) ...' will become,
'Serializer #( .DWid(DWid), .AWid(TxLogDepth) ) ...'"

Step 4: The source verilog simulation is the same in new VCS.

In the code example on p. 398, the SerLineXfer ports are just for simulation
convenience; they are unnecessary to SerDes functionality at the FullDup level.

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Step 6: Here is the VCS console display showing a $width timing violation at time

21,935 ns:

The Step 6 DoParSync pulse is too narrow at time 21,935, causing a $width violation.

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Even zoomed in, the violating pulse (obscured by the measurement cursors) does not
draw attention in the waveforms:

The Step 6 DoParSync violating pulse in a waveform view.

Step 7: The FullDup source verilog simulation should be about the same as shown

in the book, depending on precise coding.

Concerning the synthesis answers in the Lab26_Ans/FullDup_Step7 directory, the

DC script for the quick proof of synthesizability is named FullDup_Simple.sct. Its
only output netlist is named FullDupNetlist_Simple.v. In 2011 software, this
netlist is not fully functional because of timing inconsistencies caused by lack of
constraints. The latest 2011 version of DC synthesizes this SerDes_U2 in a partially
working state.
For one form of a correctly constrained, monolithic FullDup netlist, there is a
FullDup_TimingNoHold.sct script in the answer directory for this Step. You can see
the numerous constraints in the .sct file; these were arrived at by trial and error. This
script produces a different netlist named FullDupNetlist_Hier.v. Using the 2011
version of DC, and the given constraints, the hierarchical netlist simulates mostly
correctly without SDF timing; the output from the B direction being correct, but that
from the A direction being only occasionally correct. Notice that set_fix_hold was not
used for these netlists, but that fairly stringent max delay constraints were used instead,
to avoid hold failures by speeding up all gates. Hold errors vanish for fast-enough gates.
It is possible that these constraints could be improved without hold-fixing, but that was
not attempted.
Hold-fixing, using FullDup_TimingHold.sct, improves the netlist so that the
hierarchical netlist simulates correctly without SDF timing; however, the synthesis with
hold-fixing takes over 24 hours on a 1 GHz machine.
It took over a week of repeated synthesis attempts to arrive at the constraints used
above. In a commercial project, perhaps a week to a month of development time would
be allowed for refinement of the netlist synthesis of such a device. This illustrates the
advantage of purchasing IP when gate constraints may be hard to meet.

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There is a different set of exploratory synthesis results in the

FullDup_Step7/OLD_Netlists directory. These are not mentioned in the Textbook
and are explained in a ReadMe file. There is a correctly simulating netlist there which
was created by aborting a synthesis run (with set_fix_hold) before it had completed.
This exact result is chancy and probably can not be duplicated with new DC. In
particular, the DesDecHold netlist may not simulate correctly in other versions with or
without SDF.

Step 8A: Rather than following the Step 8A Textbook instructions on p. 402, which
recommend copying the Lab25 .sct file, you probably should copy the
FullDupScan.sct file from the Lab26_Ans, Step 8 directory. This is because of minor
changes in DC since the book was published.
In these .sct files, notice the large number of DC warning messages which have been
suppressed; each one was studied individually and deemed unimportant.

Step 8B: To clarify these instructions on p. 402, the netlist comparison should be
between the results of Lab26 Step 7 and Lab26 Step 8. The purpose is to get an idea of
the netlist size difference caused by scan insertion.

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Week 11 Class 2
Today's Agenda:
Lecture on SDF back-annotation
Topics: Back-annotation basics; SDF file use with a verilog design.
Summary: We briefly explain the use of back-annotation and describe some of the
characteristics of an SDF file. We show how SDF fits into the design flow.
We then give the syntax for the use of SDF with a verilog module.
SDF Lab
We synthesize the Intro_Top design and then simulate the netlist with backannotated timing.
Lab Postmortem
Q&A, and how to back-annotate part of a design.
(rest of day may be used for retrospection on recent, previous labs)

Supplementary Notes on SDF delays:

On p. 405, the last sentence in 22.1.1 should read, ". . . the timing of every net and
every component instance in the netlist."
On p. 405, a new last paragraph should be added to 22.1.1: "When a delay is
programmed in the verilog (#delay or in a specify block), but no such path (under the
same conditions) is annotated in the SDF, the verilog delay is simulated unchanged. In
all other cases, the SDF delay replaces the verilog delay; the latter is ignored."
On p. 406, in the first paragraph below Figure 22.1, the last sentence should be
changed to, "Except for colons in timing triplets, the only SDF punctuation is by
parentheses ( '(' and ')' ) and quotes for literals; so, the language looks a bit like lisp
or EDIF at first glance."

Supplementary Note on SDF file functionality. Two new last paragraphs should
be added on p. 407, after the final summary:
"Our presentation here is meant only to show how SDF relates to verilog; we cover only
a minimum of what an SDF file can do. In particular, the SDF language can include
conditional and multivalue delays, PATHPULSE overrides, and timing checks."
"SDF back-annotation may be used for netlist-based tasks such as simulation or static
timing verification; it can not be used for synthesis."

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SDF Lab 27
Topic and Location: Simulation and synthesis of Intro_Top; simulation of SDF
back-annotated netlists.
Do this work in the Lab27 directory.
Preview: We simulate the old Intro_Top design and compare timing of the original
verilog with that of the synthesized, back-annotated netlist. We then edit the SDF file
manually to see how it controls the netlist simulation timing.
Deliverables: Step 1: A correctly simulating Intro_Top design in the orig
directory. Step 2: A correctly simulating synthesized netlist of Intro_Top in the orig
directory. Step 3: A correctly simulating netlist of Intro_Top, with written-out SDF
back-annotated timing, in the ba1 ("back-annotated #1") directory. Step 4: A correctly
simulating netlist of Intro_Top in the ba2 directory, with manually modified SDF backannotated timing.

Supplementary Note concerning all these Steps: In new VCS, to display two
different simulation waveforms at once, begin by simulating one of them as usual. After
arranging the wave window nicely, save the session. Then, use the [x] icon in the upper
left-hand corner of the console window to dismiss the console window; this will leave the
wave window displayed and active. Bring up a second shell window, cd to the same
directory, and run VCS again for the second simulation. Load the saved session to create
a new wave window with the same file-lists and geometry as the first one.
Also: Old VCS used config files (.cfg), as in the Textbook, to save window setups and
wave-window signals; new VCS uses session files (.tcl), which are Tcl scripts.

Supplementary Note concerning Step 1: After copying the Intro_Top files,

change the TestBench.v timescale to 1ns/1ps or 1ns/10ps before simulating; this will
make the source and netlist simulations more precisely comparable.

Supplementary Note concerning Step 4: The following should be added before

the last paragraph on p. 410:
Here are some samples of SDF statements:
// Wire delays are "INTERCONNECT":
(CELL
(CELLTYPE "Intro_Top")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT SRLatch01/U2/ZN U2/I (0.000:0.000:0.000))...
// Instance internal delays are "IOPATH":
(CELL
(CELLTYPE "XOR2D1")
(INSTANCE OutputCombo01/U3)
(DELAY
(ABSOLUTE
(COND A2 == 1'b0 (IOPATH A1 Z (0.073:0.076:0.076) (0.079:0.082:0.082)))

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Week 12 Class 1
Today's Agenda:
Lecture wrapping up coverage of the verilog language
Summary: We describe briefly the differences between verilog-1995 and verilog2001 (or verilog-2005). We review the synthesizable subset of the language
and list the constructs not specifically covered in the course. We explain the
relationship of the verilog PLI to the language. We mention a few wiring
tricks which may be found in legacy code. We also summarize what will be the
scope of the final exam.
Continued Lab Work (Lab 23 or later)

Supplementary Note on the synthesizable subset, p. 413: Keep in mind that

fork-join can not be synthesized (as of 2010) and should be avoided in any final
implementation of simulation code other than a testbench, of course.

Supplementary Note on constructs not exercised in this Course: On p. 415, in

the second bulletted list (topics not part of verilog), the second-bullet paragraph, last
sentence, should be changed to: "This is very similar to Tcl syntax, but it is now
obsolete."
Also, as previously mentioned, defparam and procedural assign-deassign are likely
to be removed from the language, according to the current SystemVerilog IEEE Std 18002012. Don't use them.

Supplementary Note on the verilog PLI. An example of a PLI enhancement

which prints the design hierarchy into a text file is available for licensed users at
Synopsys SolvNet: https://solvnet.synopsys.com/retrieve/030557.html?
charid=techupdate&tuid=389 (as of 2011-01). The PLI version is the VPI of Std 13642005. The PLI function is named vpi() and is located in a file named vpi.c. It is
compiled and linked into the VCS executable, along with a VCS-specific side file.
Supplementary Note concerning verilog nets. Here are a few wiring tricks
which you may encounter in preexisting code. These are not recommended for reasons of
style:
Continuous assignments may be comma-separated:
assign WireX = A && B, WireY = C||(D^E), WireZ = WireY | A && D;
A wire declaration with initialization, and optional delay, may be used instead of
the declaration of the name followed by a continuous assignment:
wire WireX = A && B;
These two tricks are not especially risky but are not recommended because they
complicate syntax and make searches for declarations or continuous assignments less
predictable. They may break shell or Tcl scripts.

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A name used in a port map implies a wire and need not be declared:
ALU U1 (.Result(Res), .Ain(A), .Bin(B), .Clk(GatedClock));
...
bufif1 ClockGater (GatedClock, Clock, Ena);
GatedClock is implied and need not be declared.
Not recommended: (a) widths of implied wires always are 1; and, (b) there may be lost
time and confusion searching for the declarations of the implied names.

Scope of the Final Exam

Conditions. This will be an open-book exam held in the lab or class room: The
Course Note Book, Textbook, or any other hardcopy (including handwritten) materials
will be allowed.
All exam work must be strictly individual. No consultation with anyone, or access to
any electronic device (including a cell phone or other computer) will be permitted. If you
answer 9-1-1 calls on your cell phone in your spare time, get someone to substitute for
you on these calls during the exam.
Subject Matter. This examination is meant to ensure that the student has learned
enough from the course to come up to speed on a verilog-based engineering project with
no ramp-up delay attributable to familiarity with the language.
Topics which may be tested include correct entry of verilog modules in ANSI and
traditional header format, and behavioral or RTL design of simple devices such as
counters, shift registers, decoders, or combinational elements.
Implementation of hierarchical designs, including parameter passing and generate,
may be tested, as may be correct structural connection of simple component instances.
Assignment of delays and understanding of the verilog simulator event queue will be
assumed and may be tested. Use of assertions, timing checks, and assignment of delays
to internal paths in specify blocks may be tested.
A synthesis problem may be presented; and, if so, the student may be required to
provide a solution describing correct use of Design Compiler to improve a result.
The exam may include any other material which has been presented at least on two
occasions during the lectures or labs, or in two or more places in the Textbook.

Continued Lab Work (Lab 23 or later)

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Week 12 Class 2
Today's Agenda:
Lecture on deep-submicron problems and verification
Deep-submicron scaling physics.
Importance of correct logic and clocking.
Functional and timing verification.
System Verilog major features.
Verilog-AMS (Analogue-Mixed Signal)
Continued Lab Work (Lab 23 or later)

24.1.6 SystemVerilog

[completely replaces Textbook section 24.1.6]

SystemVerilog is an Accellera standard which has been adopted by IEEE. The 2012
standard document runs over 1300 pages, but the verilog-related subset is considerably
shorter. We concentrate here on those SystemVerilog features which are related to
verilog and are likely to be synthesizable by recently updated tools.
SystemVerilog consists in part of a superset of verilog-2005 features; all of verilog-2005
is included. This superset additionally contains many C++ design constructs. Also
included is a standalone assertion sublanguage.
A major goal of SystemVerilog is to make the porting of code to and from C++ easier
than it has been with verilog-2005. Another important goal is to make complex systemlevel design, as well as assertion statements, directly expressible.

A Caution
As we have seen, even the synthesizable subset of plain verilog, now almost 20 years
old, has not been implemented fully (and not always correctly) by the major EDA vendors.
SystemVerilog has been an IEEE standard for less than half of that time, and its
synthesizable subset is more complex than that of verilog. It behooves the designer to
try a small test case on any unfamiliar SystemVerilog feature before committing it to use
in commercial coding, whether for simulation or synthesis. Vendors generally will be
quick to fix bugs, but they have to know about them first.

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Some Features of SystemVerilog

User-defined types, with typedefs as in C++, and VHDL-like type-casting controls.

Various pointer, reference, dynamic, and queue types.
Simulation event scheduler extensions.
Pascal-like nested module declarations.
Module final block to run commands after a simulation $finish.
VHDL-like packages for declarations.
C++-like class declarations (with single inheritance, only).
Five integer types: byte, shortint, int, integer,longint. All these except
integer are unsigned types.

A covergroup declaration for functional code coverage.

The new PLI (Programming Language Interface) includes the VPI (Verification
Procedural Interface).

The new variable type, logic, may be assigned procedurally or concurrently.*

A new two-state bit type (value 0 or 1) for more efficient simulation compilation.*
A constant value may be expressed as an unbased, unsized literal.*
A new, timing-check-like gated event control by iff.*
Three procedural always block variants: always_latch, always_ff,
always_comb.*

Per-module alternatives to `timescale:

timeunit and timeprecision

declarations.*

Loop C-like break, continue, and return commands (no block name required).*
A new interface type to make reuse of module I/O declarations easier.*
A self-contained assertion language subset for assertions at module scope or in
procedural code.*
The features marked "*" are likely to be useful for logic synthesis, or for simulation
directly leading to synthesis, and are next discussed individually in more detail.

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New variable type logic

In general, all variables, such as wire or reg, default to logic type if otherwise not
constrained. Procedurally, logic and reg are identical; the word logic is preferred
when "reg" might be misinterpreted as referring to a hardware register. Declared
logic variables are unsigned unless explicitly declared signed. Related to this,
SystemVerilog includes both integer and int types; the former is the usual, signed
verilog 4-state variable, and the latter is an unsigned variable. Procedurally, an explicit
logic declaration may be used thusly:
logic [15:0] Xin, Yin, Zin;
. . .
always@(posedge Clk)
Xreg = {Xin, Yin};
A typical concurrent use of these logic instances might be as follows:
fork
#2 Xin = Ain && Bin;
#3 Yin = Bin ^ Clevel;
join

New bit type

This unsigned type is the same as a reg, except that it only can assume values
composed of 1 and 0. If an x or z is included in a bit expression, it is converted to 0.
For example,
bit[7:0] StartBit = 8'b0111_1010;

Unbased, unsized ' literals

When a ' prepends a one-bit literal with no preceding size value, and if no base unit is
specification, it causes all bits to be set to the literal value given. For example,
logic [7:0]
a = '0; //
b = '1; //
c = 'x; //
d = 'z; //

a, b, c, d;
Same as a =
Same as b =
Same as c =
Same as d =

8'b0000_0000.
8'b1111_1111.
8'bxxxx_xxxx.
8'bzzzz_zzzz.

New gated event control iff

This permits an operation to be performed if and only if a true evaluation of some
specific kind succeeds. Otherwise, the operation is gated off, and it terminates with no
effect. For example, the following always block has no effect unless Ena is equal to
1'b1:
always@(ClockIn iff Ena==1'b1) . . .;
A change in ClockIn or Ena is what triggers evaluation of this always block.

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Variants of the always block

These processes run within a module and differ from the simple always block in that
any LHS variable to which they are assigned is not permitted to be assigned elsewhere in
that module. The simulator will issue a warning if an assignment within the block is
inconsistent with those for which the variant is designed. The always_comb and
always_latch blocks do not require sensitivity lists, because all variables in the
contained statements automatically are listed as sensitive.
The always_comb block models combinational logic. Example:
always_comb
begin
Products = B*B + B*X - 1;
Result
= Products + xProducts;
end
The always_latch block infers a level-sensitive latch. Example:
always_latch
if (S_Z) S <= Z;
An always_ff block infers synchronous logic. Example:
always_ff @ (posedge Clk iff Rst == 1'b0)
CountReg <= CountReg + 1;

New timescale alternatives

These are the timeunit and timeprecision commands, which may be used to
replace `timescale. They may be included in any module, provided they are the first
statements after the module header, allowing the simulation time scale to be changed
module by module, if the tool permits it. Note that these new reserved words do not
begin with a`. If a timeunit value includes a / and a second argument, it becomes
effectively the same as a `timescale for that module. Submodules inherit the
timeunit and timeprecision values of the parent module. Examples:
module MyModule (rest of header);
timeunit 1ns;
// Time is in units of ns.
timeprecision 100 ps; // Time is to a precision of 100 ps.
(rest of module)
endmodule
module MyOtherModule (. . .);
timeunit 1ns/100ps; // Same effect as "`timescale 1ns/100ps;".
. . .
endmodule

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New loop commands

In addition to the verilog disable, SystemVerilog includes three new loop-control
commands: break, continue, and return:
break: As in C, this causes the runtime to break out of a running loop, such as a for or
a while. Example, using our FindPatternBeh.v of Lab10:
. . .
begin : Search
for ( j = 0; j <= 3; j = j ) // Might run forever.
begin : WhileLoop
while(1==1) // This while thus loops forever.
begin
. . .
if (CountOK==3)
begin
. . .
FoundPads = 1'b1;
break; // Replacing original "disable Search;".
end
. . .
continue: As in C, this triggers an immediate skip to the end of a loop statement.
Example:
for (i = 0; i<31; i = i+1)
begin
if (Reg[i] <= 8'h17)
Reg[i] = Reg[i] + 1;
else continue; // Try next i.
end

return: This causes an exit from a SystemVerilog function call or triggers an exit
from a running task.
A SystemVerilog function call may be terminated by a return(value) command
instead of by an assignment to the function's declared name. For example, in our Lab11
FnTask.v example, instead of
function[7:0] doCheckSum ( . . . );
. . .
doCheckSum = temp1[7:0] + temp2[7:0]^temp1[15:8] + temp2[15:8];
end
endfunction

in SystemVerilog we may write,

function[7:0] doCheckSum ( . . . );
. . .
return(temp1[7:0] + temp2[7:0]^temp1[15:8] + temp2[15:8]);
end
endfunction

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New interfact type

As explained fully in Chapter 25 of IEEE Std 1800, an interface is a named
collection of nets or variables and is useful when a port list or other port property is
repetitive among two or more modules. However, this benefit is not necessarily
advantageous when the design process permits easy cut-and-paste repetition of port
declarations.
Interfaces were briefly mentioned in Week 8 Class 1 (Section 15.3.3) of the Textbook.
Interfaces are declared outside of modules. An interface may contain one or more of a
parameter, constant, variable, function, task, modport, initial block, always
block, or continuous assign, although any particular EDA tool may not implement all
these features. Because the most common port declarations are of variables and nets,
one would expect these to be implemented in any supporting EDA tool. An example
follows, taken from the IEEE Std.
Assume this generic design fragment:
module memMod
(input logic req, logic clk, logic start,
logic[1:0] mode, logic[7:0] addr,
output bit gnt, bit rdy,
inout wire[7:0] data
);
logic avail;
...
endmodule
#
module cpuMod
(input logic clk, logic gnt, logic rdy,
output logic req, logic start, logic[7:0] addr,
logic[1:0] mode
inout wire[7:0] data
);
...
endmodule
#
module top;
logic req, gnt, start, rdy;
logic clk = 0;
logic[1:0] mode;
logic[7:0] addr;
wire[7:0] data;
memMod mem(req, clk, start, mode, addr, data, gnt, rdy);
cpuMod cpu(clk, gnt, rdy, data, req, start, addr, mode);
endmodule

Noticing the repetition in the module headers, it is possible to simplify those headers
by means of an interface which contains their common port declarations. This is
typically the simplest and most obvious use of an interface, to bundle a collection of
variables or nets. Other, more involved uses are presented in the IEEE Std 1800 chapter
referenced above.

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Keeping in mind that a default port directionality of inout is assumed, the same
design fragment as above may be rewritten as follows to take advantage of an
interface declaration:
interface simple_bus; // Define the interface.
logic
req, gnt;
logic[7:0] addr, data;
logic[1:0] mode;
logic
start, rdy;
endinterface: simple_bus
#
module memMod
(simple_bus a, // Access the simple_bus interface.
input logic clk
);
logic avail;
//
// When memMod is instantiated in module top, a.req is the
// "logic req, gnt;" signal in the sb_intf instance of the
// 'simple_bus' interface:
always @(posedge clk)
a.gnt <= a.req & avail;
//
endmodule
#
module cpuMod(simple_bus b, input logic clk);
...
endmodule
#
module top;
logic clk = 0;
simple_bus sb_intf();
// Instantiate the interface.
//
memMod mem(sb_intf, clk);
// Connect the interface by position
cpuMod cpu(.b(sb_intf), .clk(clk)); // or by name.
//
endmodule

106

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New assertion language

The SystemVerilog assertion language is based on the Accellera PSL (Property
Specification Language). An example of the simplicity and compactness of the assertion
language is a concurrent assertion as follows:
module MyModule (output . . ., input Clk1, Ena);
. . .
property CheckEna (Pre, Post);
// Declare the property to be asserted.
@(posedge Pre) (Pre==1'b1) |=> ##[1:7] (Post == 1'b1);
endproperty
. . .
Clk1_Ena: assert property ( CheckEna(Clk1, Ena) ) // State the assertion.
else $display("%m [time=%d]: %s\n",
$time, "Ena failed to occur within 7 posedges of Clk1");
. . .
always@(posedge Clk1) // Violation message if no Ena within 7 clocks.
. . .
endmodule

This kind of assertion is declared within a package, module, or interface and may
be called in procedural code. Instead of the "else $display . . ." shown in the code
example, omitting the else action causes a default, tool-specific $error() system task to
run if the assertion should fail. The $error() may be called explicitly and should accept
printf-like formatting, the same as $display(). Other messaging system tasks in
SystemVerilog may be used to define severity levels and include $fatal(), $warning(),
and $info(). The verilog stratified event queue is extended for SystemVerilog to handle
assertions and other enhanced language features.
Assertion messages can be verbose and thus may be used in place of comments in the
code, wherever the comment would specify proper behavior of the module.
SystemVerilog assertions are simulation objects, only; they can not be synthesized and
should be ignored by the synthesizer.

SystemVerilog Conclusion
There are, of course other SystemVerilog features useful for synthesis or synthesisaimed simulation, but the ones discussed above are those most likely to be useful to a
designer and to be implemented by an EDA vendor.

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24.1.7 Verilog-AMS
Introduction
Verilog-A/MS means "Verilog Analogue / Mixed-Signal", in which "mixed" refers to
mixed analogue and digital statements in the same verilog design.

Notes on terminology:
We shall abbreviate Verilog-A/MS as VAMS.
Because analog is a keyword in verilog-A/MS, the alternate
spelling, "analogue", will be used wherever functionality is meant.
Many large ASICs include some analogue functionality. Analogue components
generally require higher voltages and greater noise immunity than digital ones. VAMS
may be used to simulate such an ASIC with accuracy good enough to ensure correct
operation of the digital side of the design.
VAMS contains verilog (IEEE Std. 1364) as a proper subset. In addition, when a
digital or analogue module can not itself resolve inputs of the other kind, VAMS permits
a verilog source file to include declaration and instantiation of special connectmodules
for communication between the analogue and digital domains. Within a verilog module,
VAMS provides analog blocks, similar to always blocks, to implement the analogue
functionality of the module. Basically, VAMS allows a designer to code analogue
functionality in verilog.
SPICE may be included, if necessary, in a VAMS design. A VAMS simulator is
required to permit instantiation of SPICE-deck subckt code blocks in the same manner
as verilog modules. VAMS specifies a core list of SPICE constructs required to be
implemented by a conforming simulator; the precise version of SPICE otherwise is left to
the simulator author.

Relationship to Other Languages

All VAMS analogue functionality, other than SPICE, is procedural, or is by connections
among procedural blocks. However, analog procedural statements superpose effects;
they do not define a sequence in time each time they are read. VAMS is closely related
to verilog (IEEE Std 1364), to verilog-A (an earlier, nondigital Accellera adaptation of
verilog now a subset of VAMS), and to SPICE. The analogue code in an analog block in
VAMS actually, for the most part, uses verilog-A syntax; and, the VAMS analysis modes
within a VAMS analogue domain correspond to those in SPICE.
A VAMS simulator is required to run two independent kernels, one of them computing
and scheduling updates in continuous time for analogue constructs, and the other in
discrete time for digital constructs.
In the Synopsys tools, the NanoSim continuous-time simulator may be used to drive
VCS (discrete-time) and HSPICE (SPICE continuous-time). Mentor and Cadence also
have VAMS implementations.

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Analogue Functionality Overview

One declares verilog wires to be used as nodes, or "signals", which are connection
elements which can convey current or sustain a potential (voltage). Any circuit of nodes
and other elements is simulated according to Kirchoff's laws. In this context, a node
between two or more points is considered a branch of the circuit.
Instead of the "=" and "<=" assignment operators of digital verilog, VAMS uses a
contribution operator "<+" to associate a branch with analogue functionality. In a
procedural (analog) block, successive contributions add to previous ones, representing
the effect of the several components in the circuit. Depending on the context of a
contribution, sometimes a new contribution can remove and replace a previous one. The
general rule is that subsequent potentials or currents superpose on previous ones,
respectively.
There are V(x, y) and I(x, y) operators to represent contributions of voltage or
current, respectively. The operands x, and optionally y, define a branch by naming one
or two nodes between which a potential is imposed or a current flows; when only one node
is named, the other is taken to be a 0-volt, global ground.
Although irrelevant to VLSI design, VAMS can be used to represent mechanical or
hydraulic functionality such as the operation of a relay (switch) or a piston. For fluid
flow, for example, this can be done by mapping the VAMS potential to hydrostatic
pressure and the VAMS current to incompressible hydrodynamic flow.
VAMS can not in general be used for conditions in which the speed of light is
important; it assumes immediate (procedural) effects simultaneously for all components
on a node. Therefore, it can not be used for antenna design, although it can represent
equilibrium states such as resonance among different nodes, as well as impedancematching and other frequency-dependent phenomena.

Analogue and Digital Interaction

Analogue blocks can read outputs of digital blocks, and digital blocks can read outputs
of analogue blocks, but an analogue block can not assign to a discrete-time variable, and a
digital block can not assign to a continuous-time variable.
Using user-declared or predefined natures, different net disciplines may be declared
for incompatible analogue and digital contexts. Nevertheless, VAMS can permit a wire
to run between analogue and digital blocks usefully. This is done by connectmodules
which define thresholds for a digital '1' or '0' in terms of voltage, permitting analogue
calculation of transitions between digital levels. Mixed disciplines thus are resolved by
connection rules. When disciplines of two nets are compatible, there is no further
conversion required.

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Synchronization of the analogue and digital simulator kernels is of some complexity.

The analogue kernel calculates all analog functionality in a module immediately, and
effectively continually, when anything changes. There is no blocking of statements or
delay programming, although analogue effects which take time to occur (voltage changes
on a capacitor, for example) will be simulated over time as they would in a SPICE
transient analysis. The analogue kernel updates by iteration and stops when the state
at that point in simulation time has been calculated to the required degree of precision.
There is no minimum resolution of analogue time, except that imposed by the tool's data
formats. Like the digital kernel, the analogue kernel may calculate future events
predictively, but these are placed in a queue and not immediately made effective.
The digital kernel is the same as the verilog kernel discussed in Week 5 Class 1. It
uses states at the current time, analogue or digital, to evaluate and modify variables
according to the verilog event queue. An analogue update of a digital node is done by
interpolation to the nearest digitally-resolved time.
Values of declared real or integer variables often may be calculated in either
domain.

Example: VAMS DFF

Next is an example of a VAMS analogue model of a DFF, after Kundert and Zinke
(2004; Section 6.8.3, Listing 3):
module DFFa (output Q, input D, Clk);
voltage Q, D;
localparam integer Direction = +1; // +1 for posedge.
integer State;
analog
begin
@( cross(V(Clk) - 0.5, Direction) ) State = (V(D) > 0.5);
V(Q) <+ transition(State? 1: 0);
end
endmodule

The assumption is that we have a VDD of 1.0 V (digital CMOS high). The thresholdcrossing operator cross permits the State variable assignment to occur whenever
V(Clk) rises through 0.5V. The voltage of Q is assigned by the transition operator
regardless of whether the preceding event control has been fulfilled or not. The
transition operator provides a gradual transition rather than an immediate digital one
with infinite slope.

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Notes for Digital VLSI Design with Verilog

111

Benefits of VAMS
The main benefit of VAMS is in relation to SPICE: It is more abstract than SPICE and
simulates far faster; this makes VAMS usable for large analogue circuits.
A secondary benefit is that VAMS is convenient for large-design designers -- which is
to say, digital designers -- because its analogue syntax is that of the familiar verilog, and
its digital semantics is identical to that of verilog.
Otherwise stated, VAMS permits the easy integration of analogue functionality into
large projects requiring top-down design methodologies.

Continued Lab Work (Lab 23 or later)

================================================================

This ends the course.

Good luck in your continuing verilog design work!