IEEE1801 UPF

A brief introduction and overview

John Biggs
ARM Ltd

What is UPF? Power Intent

File(s)
HDL/
!  An Evolving Standard RTL

–  Accellera UPF in 2007 (1.0)

Simulation, Logical Equivalence Checking, …

–  IEEE 1801-2009 UPF (2.0)

–  IEEE 1801-2013 UPF (2.1) Synthesis

!  For Power Intent

–  To define power management
–  To minimize power consumption Power Intent
File(s)
!  Based upon Tcl Verilog
(Netlist)
–  Tcl syntax and semantics
–  Can be mixed with non-UPF Tcl

!  And HDLs
P&R
–  SystemVerilog, Verilog, VHDL

!  For Verification
–  Simulation or Emulation
Power Intent
–  Static/Formal Verification File(s)
Verilog
(Netlist)
!  And for Implementation
–  Synthesis, DFT, P&R, etc.

2
 Components of UPF
!  Power Domain:
–  Groups of elements which share a common set of
power supply requirements

!  Power Supply Network

–  Abstract description of power distribution (ports,
nets, sets & switches)

!  Power State Table

–  The legal combinations of states of each power
domain

!  Isolation Strategies
–  How the interface to a power domain should be
isolated when its primary power supply is removed

!  Retention Strategies
–  What registered state in a power domain should be
retained when its primary power supply is removed

!  Level Shifter Strategies

–  How signals connecting power domains operating at
different voltages should be shifted

!  Repeater Strategies
–  How domain ports should be bufffered

Power Domains All domain names are created

in the current scope (Sub)

Sub
! create_power_domain
set_scope Sub P1 PwrCtl P2

create_power_domain PD_Sub \
-include_scope
M1 M2 M1 M2

create_power_domain PD_Proc1 \
-elements {P1}
create_power_domain PD_Proc1Mem \ Sub/PD_Sub
Sub
-elements {P1/M1 P1/M2} PwrCtl

create_power_domain PD_Proc2 \
-elements {P2} Sub/PD_Proc1 Sub/PD_Proc2
create_power_domain PD_Proc2Mem \ P1 P2
-elements {P2/M1 P2/M2}

M1 M2 M1 M2

Sub/PD_Proc1Mem Sub/PD_Proc2Mem

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 Supply Sets
Supply Nets Supply Set Functions

power
!  A group of related supply nets PD.primary
ground

power
!  Functions represent nets Main ground
nwell
–  which can be defined later pwell
deepnwell
!  Electrically complete model deeppwell
–  power, ground, etc.
create_power_domain PD \
!  Predefined supply sets -supply {primary} \ (predefined)
-supply {backup} (user-defined)
–  for domains

!  User-defined supply sets create_supply_set Main \ (user-defined)

–  for domains (local) -function {power} \
-function {ground} \
–  standalone (global)
-function {nwell}
!  Supply set parameters
–  for strategies set_isolation ISO –domain PD \
-isolation_supply_set PD.backup

Simstates
New for 1801-2013

!  CORRUPT !  NORMAL
–  Combinational outputs corrupted –  Combinational logic functions normally
–  Sequential state/outputs corrupted –  Sequential logic functions normally
–  Both operate with characterized timing

!  CORRUPT_ON_ACTIVITY !  CORRUPT_STATE_ON_ACTIVITY
–  Combinational outputs maintained –  Combinational logic functions normally
as long as inputs are stable –  Sequential state/outputs maintained as
–  Sequential state/outputs corrupted long as inputs are stable

!  CORRUPT_ON_CHANGE !  CORRUPT_STATE_ON_CHANGE
–  Combinational outputs maintained –  Combinational logic functions normally
as long as outputs are stable –  Sequential state/outputs maintained as
–  Sequential state/outputs corrupted long as outputs are stable

add_power_state PD_Proc.primary \
-state RUN { -simstate NORMAL } \
-state DROWSY { -simstate CORRUPT_ON_ACTIVITY } \
-state OFF { -simstate CORRUPT }

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 Power State

! add_power_state <domain> Proc1/PD_Proc P M

add_power_state PD_Mem \
-state RUN {-logic_expr {primary == ON_08}} \
Proc1
P1
-state OFF {-logic_expr {primary == OFF}}

add_power_state PD_Proc \
-state Normal { \ P
-logic_expr {primary == ON_10 && \ M1 M2
memory == ON_08 && \
Proc1/PD_Mem
PD_Mem == RUN} } \
-state Sleep { \
-logic_expr {primary == OFF && \
memory == ON_08 && \
PD_Mem == RUN} } \ PD_PROC primary memory PD_MEM
-state Hibernate { \ Normal ON_10 ON_08 RUN
-logic_expr {primary == OFF && \
memory == OFF && \ Sleep OFF ON_08 RUN
PD_Mem == OFF} }
Hibernate OFF OFF OFF

Power Switches

create_logic_port nPWR1 –direction in Proc1/PD_Proc P M

Proc1
P1
create_power_switch SW -domain PD_Proc
-input_supply_port {sw_in VDDSOC} nPWR1
-output_supply_port {sw_out VDDPROC1}
-control_port {sw_ctl nPWR} P
-on_state {on_state sw_in {!nPWR1}} M1 M2
-off_state {off_state { nPWR1}}
Proc1/PD_Mem

PD_PROC primary memory PD_MEM

Normal ON_10 ON_08 RUN

Sleep OFF ON_08 RUN

Hibernate OFF OFF OFF

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Isolation Strategies

set_isolation ISO_Proc \ Proc1/PD_Proc P M

-domain PD_Proc \
-applies_to outputs \ Proc1
P1
-clamp_value 0 \
nPWR1
-isolation_signal mISO \
-isolation_sense low \
P
-location self
M1 M2
use_interface_cell ISOX1 \ Proc1/PD_Mem
-domain PD_Mem \
-strategy ISOMem \
-lib_cells {TechISOX1}
PD_PROC primary memory PD_MEM

Normal ON_10 ON_08 RUN

Sleep OFF ON_08 RUN

Hibernate OFF OFF OFF

Level Shifting Strategies LS

Proc1/PD_Proc P M
set_level_shifter LSmem \
-domain PD_Mem \
-applies_to outputs \ Proc1
P1
-location self
nPWR1

P
LS

LS

use_interface_cell LSX2 \
M1 M2
-domain PD_Mem \
-strategy LSMem \ Proc1/PD_Mem
-lib_cells {TechLSX2}

PD_PROC primary memory PD_MEM

Normal ON_10 ON_08 RUN

Sleep OFF ON_08 RUN

Hibernate OFF OFF OFF

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Retention Strategies RR

Proc1/PD_Proc P M
set_retention RET1 \
-domain PD_Proc \ RR
SRb

-save_signal {SRb posedge} \ Proc1

P1
-restore_signal {SRb negedge}
nPWR1

P
map_retention_cell RET1 \ M1 M2
-domain PD_Proc \
Proc1/PD_Mem
-lib_cells {TechRRX4}

PD_PROC primary memory PD_MEM

Normal ON_10 ON_08 RUN

Sleep OFF ON_08 RUN

Hibernate OFF OFF OFF

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Successive Refinement of Power Intent

1 IP Creation 2 IP Configuration 3 IP Implementation

RTL RTL RTL

Constraint Constraint
UPF Config’n
+ Soft IP Golden Source UPF
Constraint
+
UPF Configuration +
UPF
Simulation, Logical Equivalence Checking, …

Impl’tion
UPF

IP Provider: IP Licensee/User: Synthesis

!  Creates IP source !  Configures IP for context

Impl’tion UPF
!  Creates low power !  Validates configuration Netlist
implementation
constraints !  Freezes “Golden Source”
!  Implements configuration
P&R
!  Verifies implementation
against “Golden Source”
Impl’tion UPF
Netlist

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A Soft IP provider need only declare four things:

1.  The "atomic" power domains in the design

•  These can be merged but not split during implementation

2.  The state that needs to be retained during shutdown

•  Without prescribing how retention is controlled

3.  The signals that need isolating high/low

•  Without prescribing how isolation is controlled

4.  The legal power states and sequencing between them

•  Without prescribing absolute voltages

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CPU Constraints CPU

FPU
Put everything in PD_CPU
Then call out PD_FPU
1.  Atomic power domains
create_power_domain PD_CPU -elements {.} \
–exclude_elements “$FPU” -atomic
create_power_domain PD_FPU –elements “$FPU” –atomic
!

2.  Retention requirements Retain “all or nothing”

set_retention_elements RETN_LIST -elements {.}
!

3.  Isolation requirements

set_port_attributes -model cortex_cpu -applies_to outputs \
-exclude_ports “$CPU_CLAMP1” -clamp_value 0
set_port_attributes -model cortex_cpu –ports “$CPU_CLAMP1” -clamp_value 1
set_port_attributes -elements “$FPU” -applies_to outputs -clamp_value 0
!
Clamp everything low by default
Then call out the exceptions

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CPU Constraints (cont…) CPU

FPU
Define PD_FPU in terms
of its supply sets
4.  Power State
add_power_state PD_FPU -domain \
-state {RUN -logic_expr {primary == ON \ PD_FPU primary retention
&& default_retention == ON }} \
-state {RET -logic_expr {primary == OFF \ RUN ON ON
&& default_retention == ON }} \
RET OFF ON
-state {OFF -logic_expr {primary == OFF \
&& default_retention == OFF }} OFF OFF OFF

add_power_state PD_CPU -domain \

-state {RUN -logic_expr {primary == ON \
&& default_retention == ON} \ PD_CPU primary retention PD_FPU
-state {RET -logic_expr {primary == OFF \
&& default_retention == ON \ RUN ON ON *
&& PD_FPU != RUN}} \
-state {OFF -logic_expr {primary == OFF \ RET OFF ON !RUN
&& default_retention == OFF \
OFF OFF OFF OFF
&& PD_FPU == OFF}}
Define
! PD_CPU in terms
of its
! supply sets and In RET the FPU state can
the state of PD_FPU be anything but RUN

15

Successive Refinement of Power Intent

1 IP Creation 2 IP Configuration

RTL

+ Soft IP
Constraint
UPF

We now have UPF constraints to go along

with the unconfigured RTL

IP Provider: This is what an IP provider would deliver

!  Creates IP source

!  Creates low power

implementation
constraints

16
Flat vs Hierarchical

! Configure instances in SOC

context nPWR1 nISO1
PMU nPWR2 nISO2

set_scope /SOC
load_upf cpu_cnstr.upf –scope CLSTR/CPU1
load_upf cpu_cnstr.upf –scope CLSTR/CPU2
CLSTR
load_upf clstr_cnstr.upf –scope CLSTR

! Isolation
set_isolation ISO -domain PD_CPU1
-isolation_signal PMU/nISO1
-location self

! Power switches CPU1 CPU2

create_power_switch SW -domain PD_CPU1
-input_supply_port {sw_in VDDSOC}
-output_supply_port {sw_out VDDCPU1}
-control_port {sw_ctl PMU/nPWR1}
-on_state {on_state sw_in {!PMU/nPWR1}}
-off_state {off_state { PMU/nPWR1}}

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Flat vs Hierarchical

! Configure IP out of context SOC

create_logic_port nISO –direction in
nPWR1 nISO1
PMU nPWR2 nISO2
create_logic_port nPWR –direction in
set_isolation ISO -domain PD1
-isolation_signal nISO
create_power_switch SW -domain PD CLSTR
-control_port {sw_ctl nPWR}

! Load configured IP in to
context
set_scope /CLSTR
load_upf cpu_config.upf –scope CPU1
load_upf cpu_config.upf –scope CPU2 CPU1 CPU2
create_logic_port nISO1
create_logic_port nPWR1
connect_logic_net CPU1/ISO –port nPWR1
connect_logic_net CPU1/ISO –port nISO1

! Connect up to PMU
!

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Tip: Align Power Domains and Logic Hierarchy

!  Multi-element power domains can lead TOP

to unexpected “intra-domain” isolation
create_power_domain RED –elements {A B} A B C
iso

!  These can often be avoided with a TOP

different approach
create_power_domain RED –elements {.} A B C D
create_power_domain BLUE –elements {C}

E
!  Better to align power domains with logic TOP
hierarchy if at all possible
create_power_domain RED –elements {RED} RED BLUE
create_power_domain BLUE –elements {BLUE}
A B C D
Failing that use “-diff_supply_only” option
or the source/sink filters

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CPU Configuration CPU

! Compose PD_CPU and PD_FPU in to single FPU

domain
create_composite_domain PD_myCPU –subdomains {PD_CPU PD_FPU}

PD_FPU not
! Create power control ports required
create_logic_port nPWRUP_CPU -direction in
create_logic_port nISOLATE_CPU -direction in

! Create isolation strategies to fulfill isolation

requirements
set_isolation ISO_LO -domain PD_myCPU \
–applies_to outputs -clamp_value 0 \ Clamp all outputs
-isolation_signal nISOLATE_CPU -isolation_sense low \ low by default
-location self
set_isolation ISO_HI -domain PD_myCPU \
-elements “$CPU_CLAMP1” -clamp_value 1 \ Clamp the exceptions high
-isolation_signal nISOLATE_CPU -isolation_sense low \ (more specific overrides
-location self
more generic)

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CPU Configuration CPU

! Update power supply state with supply FPU

expressions
add_power_state PD_myCPU.primary –supply -update\
-state {ON -supply_expr {power == FULL_ON && ground == FULL_ON }}\
-state {OFF -supply_expr {power == OFF || ground == OFF }}

! Update power domain state with logic

expressions!
add_power_state PD_CPU -domain -update \
-state {RUN -logic_expr {!nPWRUP_CPU}} \
-state {RET -illegal} \ CPU state retention
-state {OFF -logic_expr { nPWRUP_CPU}} not required

add_power_state PD_FPU -domain -update \

-state {RUN -logic_expr {!nPWRUP_CPU}} PD_FPU is in on when
-state {OFF -logic_expr { nPWRUP_CPU}}
nPWRUP_CPU is low

add_power_state PD_myCPU –domain -update \

-state {RUN -logic_expr {PD_CPU = RUN && PD_FPU == RUN}
-state {OFF -logic_expr {PD_CPU = OFF && PD_FPU == OFF}
Express PD_myCPU state in
! terms of PD_CPU & PD_FPU

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Successive Refinement of Power Intent

1 IP Creation 2 IP Configuration 3 IP Implementation

RTL RTL
Constraint
UPF
+ Soft IP Golden Source
Constraint
+
UPF Configuration
UPF

We now have a fully

configured technology
IP Provider: IP LicenseeUser: independent “Golden
Reference” ready for
!  Creates IP source !  Configures IP for context
implementation
!  Creates low power !  Validates configuration
implementation
constraints !  Freezes “Golden Source”

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 CPU Implementation CPU

FPU

! Create supply nets and update supply set functions

create_supply_net VDD
create_supply_net VDD_CPU Use VDD_CPU for
create_supply_net VSS
primary power
create_supply_set PD_myCPU.primary –update\
-function {power VDD_CPU} -function {ground VSS}
create_supply_set PD_myCPU.default_isolation –update \ Use VDD for
-function {power VDD} -function {ground VSS} isolation power

! Map the isolation strategies on to specific library cells

use_interface_cell CPU_LO -strategy ISO_LO -domain PD_CPU -lib_cells “$ISO_LO”
use_interface_cell CPU_HI -strategy ISO_HI -domain PD_CPU -lib_cells “$ISO_HI”

! Create a switch to fulfill the power state

create_power_switch SW_CPU -domain PD_myCPU \
-input_supply_port {sw_in VDD} \
-output_supply_port {sw_out VDD_CPU} \
-control_port {sw_ctl nPWRUP_CPU} \ Switch drives VDD_CPU with VDD
-on_state {on_state sw_in {!nPWRUP_CPU}} \
when nPWRUP_CPU is low
-off_state {off_state {nPWRUP_CPU}}
!

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Hand Off as Hard Macro

!  No need to re-verify the low power implementation

–  Just need to verify its low power integration in to the SoC

1.  Power aware simulation model

•  Corruption and retention behaviours during shutdown
•  Assertions to check correct sequencing of power controls

2.  Liberty model with power/ground pin syntax

•  related_power_pin, power_down_function etc.
Liberty:
related_
3.  Macro level UPF (descriptive not directive) power_
PD pin UPF:
•  “Virtual” switches to “expose” internal supply sets Blue set_port_
attributes
•  Power states, related power pins, isolation etc. -model

Hard Macro

!  Alternatively just use the original RTL+UPF to model Hard Macro

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P1801: IEEE-SA Entity Based Work Group

25

The New IEEE1801-2013 Standard

! Motivation
–  Address known issues with 1801-2009
•  Improve the clarity and consistency
–  Syntax clarifications, semantic clarifications
•  Some restrictions, some additions
–  Include limited number of critical enhancements
•  Improved support for macro cell modeling
•  Attribution library pins/cells with low power meta data

! Additional contributions:
–  Cadence: Library Cell Modeling Guide Using CPF
–  Cadence: Hierarchical Power Intent Modeling Guide Using CPF
–  Si2: Common Power Format Specification, Version 2.0

=> Improved methodology convergence with CPF flows

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The New IEEE1801-2013 Standard
!  Revisited each and every command
–  Rewrote the major strategy commands
!  Rewrote many key sections:
–  Definitions, UPF Concepts, Language Basics, Simulation Semantics

!  Added new sections:

–  Power management cell commands, UPF processing,
–  Informative Annex on Low Power Design Methodology

!  “D14” approved by IEEE-SA March 6th 2013

–  A 95% (19/20) approval rate on a 95% (20/21) return.
–  One the largest entity base ballot pools in IEEE-SA history

!  IEEE1801-2013 Published May 30th 2013

–  Available at no charge via the IEEE Get™Program
•  http://standards.ieee.org/findstds/standard/1801-2013.html
•  http://standards.ieee.org/getieee/1801/download/1801-2013.pdf

27

28
 Key:
- Accellera UPF-1.0 (2007)

Accellera UPF-1.0 (2007) - IEEE 1801-2009 (UPF-2.0)

- IEEE 1801-2013 (UPF-2.1)
- Deprecated/Legacy

Navigation:
- set_scope
- set_design_top

Supply Nets: HDL Interface:

- create_supply_port - bind_checker
- create_supply_net - create_hdl2upf_vct
- connect_supply_net - create_upf2hdl_vct
- create_power_switch
Code Management:
Power Domains: - upf_version
- create_power_domain Strategies: - load_upf
- set_domain_supply_net - save_upf

- set_retention
- set_retention_control
Power States: - set_isolation
- add_port_state - set_isolation_control
- create_pst - set_level_shifter
- add_pst_state

Implementation:
- map_retention_cell
- map_isolation_cell
- map_level_shifter_cell
- map_power_switch_cell

29

Key:
- Accellera UPF-1.0 (2007)

IEEE 1801-2009 (UPF-2.0) - IEEE 1801-2009 (UPF-2.0)

- IEEE 1801-2013 (UPF-2.1)
- Deprecated/Legacy

Navigation: Attributes: Control Logic:

- set_scope - set_port_attributes - create_logic_port
- set_design_top - set_design_attributes - create_logic_net
- HDL and Liberty attributes - connect_logic_net

Supply Nets: Supply Sets: HDL Interface:

- create_supply_port - create_supply_set - bind_checker
- create_supply_net - supply set handles - create_hdl2upf_vct
- connect_supply_net - associate_supply_set - create_upf2hdl_vct
- create_power_switch - connect_supply_set
Code Management:
Power Domains: - upf_version
- create_power_domain Strategies: - load_upf
- set_domain_supply_net - save_upf
- create_composite_domain - set_retention_elements - load_upf_protected
- set_retention - load_simstate_behavior
- set_retention_control - find_objects
Power States: - set_isolation
- add_port_state - set_isolation_control
- create_pst - set_level_shifter
- add_pst_state
- add_power_state
- describe_state_transition Implementation:
- map_retention_cell
- map_isolation_cell
Simstates: - map_level_shifter_cell
- add_power_state - map_power_switch_cell
- set_simstate_behavior - use_interface_cell

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 Key:
- Accellera UPF-1.0 (2007)

IEEE 1801-2013 (UPF-2.1) - IEEE 1801-2009 (UPF-2.0)

- IEEE 1801-2013 (UPF-2.1)
- Deprecated/Legacy

Navigation: Attributes: Control Logic:

- set_scope - set_port_attributes - create_logic_port
- set_design_top - set_design_attributes - create_logic_net
- HDL and Liberty attributes - connect_logic_net

Supply Nets: Supply Sets: HDL Interface:

- create_supply_port - create_supply_set - bind_checker
- create_supply_net - supply set handles - create_hdl2upf_vct
- connect_supply_net - associate_supply_set - create_upf2hdl_vct
- create_power_switch - connect_supply_set
- set_equivalent Code Management:
Power Domains: - upf_version
- create_power_domain Strategies: - load_upf
- set_domain_supply_net - set_repeater - save_upf
- create_composite_domain - set_retention_elements - load_upf_protected
- set_retention - load_simstate_behavior
- set_retention_control - find_objects
Power States: - set_isolation - begin_power_model
- add_port_state - set_isolation_control - end_power_model
- create_pst - set_level_shifter - apply_power_model
- add_pst_state
- add_power_state
Implementation: Power Management Cells:
- describe_state_transition
- map_retention_cell - define_always_on_cell
- map_isolation_cell - define_diode_clamp
- map_level_shifter_cell - define_isolation_cell
Simstates:
- map_power_switch_cell - define_level_shifter_cell
- add_power_state
- use_interface_cell - define_power_switch_cell
- set_simstate_behavior
- define_retention_cell

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P1801 Work Group Plans

! 1801-2015 PAR (Project Authorization Request)

–  Just been approved by at June IEEE-SA board meeting

! Motivation
–  Extend scope of “Power Intent” up to System Level
–  Add power modeling and estimation capabilities
•  SAIF integration and extension
–  Consider further UPF/CPF methodology convergence
–  Enhance and extend Low Power Methodology Annex

! Interested in working on UPF? Join the working

group!
–  Send an email to [email protected] for details
–  http://standards.ieee.org/develop/wg/UPF.html

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