Isl95836 PDF

PRELIMINARY
3+2 Voltage Regulator for IMVP-7/VR12™ CPUs

ISL95836 Features
Compliant with IMVP-7/VR12™, the ISL95836 provides a • Serial Data Bus
complete solution for microprocessor and graphic processor • Dual Outputs:
core power supply. It provides two Voltage Regulators (VRs) - Configurable 3-, 2- or 1-phase for the 1st Output using 2
with three integrated gate drivers. The first VR can be integrated Gate Drivers
configured as 3-, 2- or 1-phase VR while the second VR could
- Configurable 2- or 1-phase for the 2nd Output using an
be configured as 2- or 1-phase VR, providing maximum
Integrated Gate Driver
PRELIMINARY
flexibility. The two VRs share the serial control bus to
communicate with the CPU and achieve lower cost and smaller • 0.5% System Accuracy Over-Temperature
board area compared with the two-chip approach. • Supports Multiple Current Sensing Methods
Based on Intersil’s Robust Ripple Regulator (R3) technology™, - Lossless Inductor DCR Current Sensing
the PWM modulator compared to traditional modulators, has - Precision Resistor Current Sensing
CONFIDENTIAL
faster transient settling time, variable switching frequency
during load transients and has improved light load efficiency • Differential Remote Voltage Sensing
with it’s ability to automatically change switching frequency. • Programmable VBOOT Voltage at Start-up
The ISL95836 has several other key features. Both outputs • Resistor Programmable IMAX, Switching Frequency for Both
support DCR current sensing with single NTC thermistor for Outputs
DCR temperature compensation or accurate resistor current
IN REVIEW
• Adaptive Body Diode Conduction Time Reduction
sensing. Both outputs come with remote voltage sense,
programmable VBOOT voltage, IMAX and switching frequency, Applications
adjustable OC protection and separate Power-Good.
• IMVP-7/VR12 Compliant Computers
Load Line Regulation

0.91 VIN = 19V
0.90
0.89
0.88
0.87
VOUT (V)
0.86
0.85
0.84
0.83
VIN = 12V
0.82
VIN = 8V
0.81
0.80
0 6 12 18 24 30 36 42 48 54 60 66
IOUT (A)
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG.
(Notes 1, 2, 3) PART MARKING (°C) (Pb-Free) DWG. #
ISL95836HRTZ 95836 HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5
ISL95836IRTZ 95836 IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95836. For more information on MSL please see techbrief TB363.
THIS IS A PRE-DEVELOPMENT PRELIMINARY DATASHEET. DEVICE FUNCTIONALITY AND SPECIFICATIONS ARE SUBJECT TO CHANGE
March 12, 2011 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
FN7835.0 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Free Datasheet http://www.0PDF.com
ISL95836
Pin Configuration
ISL95836
(40 LD TQFN)
TOP VIEW
UGATE1G
PHASE1G
LGATE1G
PGOODG
BOOT1G
ISUMNG
COMPG
PWM2G
RTNG
FBG
40 39 38 37 36 35 34 33 32 31
ISUMPG 1 30 BOOT2
ISEN1G 2 29 UGATE2
ISEN2G 3 28 PHASE2
NTCG 4 27 LGATE2
SCLK 5 GND PAD 26 VCCP
ALERT# 6 (BOTTOM) 25 VDD
CONFIDENTIAL
SDA 7 24 PWM3
VR_HOT# 8 23 LGATE1
VR_ON 9 22 PHASE1
NTC 10 21 UGATE1
11 12 13 14 15 16 17 18 19 20
IN REVIEW
ISEN2
ISEN1
ISUMP
ISUMN
RTN
FB
COMP
ISEN3/FB2
BOOT1
PGOOD
Pin Descriptions
ISL95836
PIN NUMBER SYMBOL DESCRIPTION
BOTTOM GND Signal common of the IC. Unless otherwise stated, signals are referenced to the GND pin. In
PAD addition, it is the return path for all the low-side MOSFET gate drivers. It should also be used as the
thermal pad for heat removal.
2 ISEN1G Individual current sensing for VR2 Phase 1.
3 ISEN2G Individual current sensing for VR2 Phase 2. When ISEN2 is pulled to 5V VDD, the controller will
disable VR2 Phases 2.
4 NTCG The second thermistor input to VR_HOT# circuit. Use it to monitor VR2 temperature.
5, 6, 7 SCLK, Communication bus between the CPU and the VRs.

ALERT#,
SDA
8 VR_HOT# Open drain thermal overload output indicator. Can be considered part of communication bus with
CPU.
9 VR_ON Controller enable input. A high level logic signal on this pin enables the controller.
10 NTC One of the thermistor inputs to VR_HOT# circuit. Use it to monitor VR1 temperature.
11 INSE3/FB2 When the VR1 is configured in 3-phase mode, this pin is ISEN3. ISEN3 is the individual current
sensing for VR1 phase 3. When VR1 is configured in 2-phase mode, this pin is FB2. There is a switch
between the FB2 pin and the FB pin. The switch is on when VR1 is in 2-phase mode and is off in 1-
phase mode. The components connecting to FB2 are used to adjust the compensation in 1-phase
mode to achieve optimum performance for VR1.
12 ISEN2 Individual current sensing for VR1 Phase 2. When ISEN2 and PWM3 are both pulled to 5V VDD, the
controller will disable VR1 Phases 3 and 2.
13 ISEN1 Individual current sensing for VR1 Phase 1.
2 FN7835.0
March 12, 2011

ISL95836
Pin Descriptions (Continued)
ISL95836
14, 15 ISUMP and VR1 droop current sense input.

ISUMN
16 RTN VR1 remote voltage sensing return.
17 FB This pin is the inverting input of the error amplifier for VR1.
18 COMP This pin is the output of the error amplifier for VR1. Also, aresistor from this pin to GND programs
Imax for VR1, and Vboot for both VR1 and VR2.
19 PGOOD Power-Good open-drain output indicating when VR1 is able to supply regulated voltage. Pull up
externally with a 680 resistor to VCCP or 1.9k to 3.3V.
20 BOOT1 Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT1 pin, each time the PHASE1
pin drops below VCCP minus the voltage dropped across the internal boot diode.
CONFIDENTIAL
21 UGATE1 Output of VR1 Phase-1 high-side MOSFET gate driver. Connect the UGATE1 pin to the gate of the
Phase-1 high-side MOSFET.
22 PHASE1 Current return path for the VR1 Phase-1 high-side MOSFET gate driver. Connect the PHASE1 pin to
the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output
inductor of VR1 Phase 1.
IN REVIEW
23 LGATE1 Output of VR1 Phase-1 low-side MOSFET gate driver. Connect the LGATE1 pin to the gate of VR1
Phase-1 low-side MOSFET.
24 PWM3 PWM output for VR1 Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable VR1 Phase
3.
25 VDD 5V bias power.
26 VCCP Input voltage bias for the internal gate drivers. Connect +5V to the VCCP pin. Decouple with at least
1µF of an MLCC capacitor.
27 LGATE2 Output of VR1 Phase-2 low-side MOSFET gate driver. Connect the LGATE2 pin to the gate of VR1
28 PHASE2 Current return path for VR1 Phase-2 high-side MOSFET gate driver. Connect the PHASE2 pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor
of VR1 Phase 2.
29 UGATE2 Output of VR1 Phase-2 high-side MOSFET gate driver. Connect the UGATE2 pin to the gate of VR1
30 BOOT2 Connect an MLCC capacitor across the BOOT2 and the PHASE2 pins. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT2 pin, each time the PHASE2
pin drops below VCCP minus the voltage dropped across the internal boot diode.
31 BOOT1G Connect an MLCC capacitor across the BOOTG and the PHASE1G pins. The boot capacitor is charged
through an internal boot diode connected from the VCCP pin to the BOOT1G pin, each time the
PHASEG pin drops below VCCP minus the voltage dropped across the internal boot diode.
32 UGATE1G Output of VR2 Phase-1 high-side MOSFET gate driver. Connect the UGATE1G pin to the gate of VR2
33 PHASE1G Current return path for VR2 Phase-1 high-side MOSFET gate driver. Connect the PHASEG pin to the
node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor
of VR2 Phase 1.
34 LGATE1G Output of VR2 Phase-1 low-side MOSFET gate driver. Connect the LGATE1G pin to the gate of VR2
35 PWM2G PWM output for VR2 Phase 2.
36 PGOODG Power-Good open-drain output indicating when VR2 is able to supply regulated voltage. Pull up
externally with a 680 resistor to VCCP or 1.9k to 3.3V.
37 COMPG This pin is the output of the error amplifier for VR2. Also, aresistor from this pin to GND programs
Imax for VR2 and Tmax for both VR1 and VR2.
3 FN7835.0
March 12, 2011

ISL95836
Pin Descriptions (Continued)
ISL95836
38 FBG This pin is the inverting input of the error amplifier for VR2.
39 RTNG VR2 remote voltage sensing return.
40, 1 ISUMNG VR2 droop current sense input. When ISUMNG is pulled to 5V VDD, all the communication to VR2 is
and disabled.
ISUMPG
CONFIDENTIAL
IN REVIEW
4 FN7835.0
March 12, 2011

ISL95836
Block Diagram
COMPG PWM2G

+
RTNG +
E/A BOOT1G
FBG _
VR2
DRIVER UGATE1G
IDROOPG MODULATOR
PHASE1G
ISUMPG +
CURRENT
_ SENSE
ISUMNG
DRIVER LGATE1G
ISEN1G PGOODG
CURRENT
OC FAULT
CONFIDENTIAL
BALANCING
ISEN2G
IBAL FAULT
OV FAULT
NTCG
TEMP T_MONITOR
NTC
IN REVIEW
MONITOR
VDD
VR_HOT#
VCCP
IMAX
VBOOT PROG
TMAX
SET (A/D)
IDROOPG
VR_ON A/D IDROOP
DAC2
SDA
DIGITAL D/A DAC1
PWM3
INTERFACE
ALERT# MODE2
MODE MODE1 BOOT2
SCLK
VREADY
DRIVER UGATE2
PHASE2
COMP
+
DRIVER LGATE2

+ VR1
RTN +
MODULATOR
E/A
FB FB2 _
BOOT1
CIRCUIT
IDROOP
DRIVER UGATE1
ISUMP +
CURRENT
PHASE1
_ SENSE
ISUMN
ISEN3/FB2 DRIVER LGATE1
ISEN2 CURRENT
BALANCING
OC FAULT
PGOOD
ISEN1
IBAL FAULT
OV FAULT
GND
5 FN7835.0
March 12, 2011

ISL95836
Simplified Application Circuit
V+5 V+5
Vin
VCC L5
VDD VCCP UGATE
FCCM
Rntcg PHASE
NTCG ISL6208 BOOT
oC PWM2G PWM LGATE
GND GT Vcore
PGOODG PGOODG
BOOT1G
UGATE1G L4
PHASE1G
COMPG LGATE1G
Rprog2
Rsum5
ISUMPG
Rng
FBG Rsum4
Cng oC
Rdroopg
CONFIDENTIAL
Rig Vsumng
ISUMNG
Cvsumng
Cisen5 Cisen4 Risen5
ISEN2G
VCCSENSEG
VSSSENSEG RTNG Risen4
IN REVIEW
ISEN1G
V+5
Vin
VCC L3
SDA SDA UGATE
FCCM
ALERT# ALERT# PHASE
ISL6208
SCLK SCLK PWM3 BOOT
PWM LGATE
ISL95836 GND
BOOT2
UGATE2 L2
CPU Vcore
Rntc PHASE2
oC NTC
LGATE2
VR_HOT# VR_HOT#
BOOT1
PGOOD PGOOD
VR_ON VR_ON UGATE1 L1
PHASE1
LGATE1
Rsum3
COMP ISUMP
Rsum2
Rprog1 Rn
Cn oC
Rsum1
FB
Rdroop Ri Vsumn
ISUMN
Cvsumn
Cisen1 Cisen2 Cisen3 Risen3
ISEN3/FB2
Risen2
VCCSENSE
ISEN2
VSSSENSE RTN
Risen1
ISEN1
GND
FIGURE 1. TYPICAL ISL95836 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING
6 FN7835.0
March 12, 2011

ISL95836
Table of Contents
Load Line Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Multiphase R3™ Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CONFIDENTIAL
Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage Regulation and Load Line Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Differential Voltage Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IN REVIEW
CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Dynamic Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VR_HOT#/ALERT# Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FB2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Adaptive Body Diode Conduction Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Supported Data And Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Key Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Programming Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slew Rate Compensation Circuit For VID Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 FN7835.0
March 12, 2011

ISL95836
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Thermal Resistance (Typical) JA (°C/W) JC (°C/W)
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V 40 Ld TQFN Package (Notes 4, 5) . . . . . . . 29 1
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Boot-to-Phase Voltage Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
(BOOT-PHASE) -0.3V to +7V(DC) . . . . . . . . . . . . . . -0.3V to +9V(<10ns) Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ) Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
. . . . . . . . . . . . . . . . . . . . PHASE - 5V (<20ns Pulse Width, 10µJ) to BOOT http://www.intersil.com/pbfree/Pb-FreeReflow.asp
LGATE Voltage
. . . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V) Recommended Operating Conditions
Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
ESD Rating Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV Ambient Temperature
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . . . . 1k IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Junction Temperature
HRTZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
CONFIDENTIAL
IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
IN REVIEW
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications "Operating Conditions: VDD = 5V, TA = -40°C to +100°C (ISL95836IRTZ), TA = -10°C to +100°C
(ISL95836HRTZ), fSW = 300kHz, unless otherwise noted." Boldface limits apply over the operating temperature ranges, -10°C to +100°C or
-40°C to +100°C.
MIN MAX
PARAMETER SYMBOL TEST CONDITIONS (Note 6) TYP (Note 6) UNITS
INPUT POWER SUPPLY
+5V Supply Current IVDD VR_ON = 1V 5 mA
VR_ON = 0V 1 µA
Battery Supply Current IVIN VR_ON = 0V 1 µA
VIN Input Resistance RVIN VR_ON = 1V 550 k
POWER-ON-RESET THRESHOLDS
VDD Power-On-Reset Threshold VDDPORr VDD rising 4.35 4.5 V
VDDPORf VDD falling 4.00 4.15 V
VIN Power-On-Reset Threshold VINPORr VIN rising 4.00 4.35 V
VINPORf VIN falling 2.8 3.3 V
SYSTEM AND REFERENCES
System Accuracy HRTZ No load; closed loop, active mode range, VID
%Error (VOUT) = 0.75V to 1.52V, -0.5 +0.5 %
VID = 0.5V to 0.745V -8 +8 mV
VID = 0.25V to 0.495V -15 +15 mV
IRTZ No load; closed loop, active mode range, VID
%Error (VOUT) = 0.75V to 1.52V -0.8 +0.8 %
VID = 0.5V to 0.745V -10 +10 mV
VID = 0.25V to 0.495V -18 +18 mV
Internal VBOOT HRTZ 1.0945 1.100 1.1055 V
IRTZ 1.0912 1.100 1.1088 V
Maximum Output Voltage VOUT(max) VID = [11111111] 1.52 V
8 FN7835.0
March 12, 2011

ISL95836
-40°C to +100°C. (Continued)
MIN MAX
Minimum Output Voltage VOUT(min) VID = [00000001] 0.25 V
CHANNEL FREQUENCY
Adjustment Range 300 450 kHz
AMPLIFIERS
Current-Sense Amplifier Input Offset IFB = 0A -0.15 +0.15 mV
Error Amp DC Gain Av0 90 dB
Error Amp Gain-Bandwidth Product GBW CL = 20pF 18 MHz
ISEN
Imbalance Voltage Maximum of ISENs - Minimum of ISENs 1 mV
Input Bias Current 20 nA
CONFIDENTIAL
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage VOL IPGOOD = 4mA 0.15 0.4 V
PGOOD Leakage Current IOH PGOOD = 3.3V 1 µA
PGOOD Delay tpgd 1.2 ms
IN REVIEW
ALERT# Low Voltage 7 12 
VR_HOT# Low Voltage 7 12 
ALERT# Leakage Current 1 µA
VR_HOT# Leakage Current 1 µA
GATE DRIVER
UGATE Pull-Up Resistance RUGPU 200mA Source Current 1.0 1.5 
UGATE Source Current IUGSRC UGATE - PHASE = 2.5V 2.0 A
UGATE Sink Resistance RUGPD 250mA Sink Current 1.0 1.5 
UGATE Sink Current IUGSNK UGATE - PHASE = 2.5V 2.0 A
LGATE Pull-Up Resistance RLGPU 250mA Source Current 1.0 1.5 
LGATE Source Current ILGSRC LGATE - VSSP = 2.5V 2.0 A
LGATE Sink Resistance RLGPD 250mA Sink Current 0.5 0.9 
LGATE Sink Current ILGSNK LGATE - VSSP = 2.5V 4.0 A
UGATE to LGATE Deadtime tUGFLGR UGATE falling to LGATE rising, no load 23 ns
LGATE to UGATE Deadtime tLGFUGR LGATE falling to UGATE rising, no load 28 ns
BOOTSTRAP DIODE
Forward Voltage VF PVCC = 5V, IF = 2mA 0.58 V
Reverse Leakage IR VR = 25V 0.2 µA
PROTECTION
Overvoltage Threshold OVH VSEN rising above setpoint for >1µs 120 155 200 mV
Current Imbalance Threshold One ISEN above another ISEN for >1.2ms 9 mV
VR1 Overcurrent Threshold 3-Phase - PS0 and 1-Phase - all states 25.5 30.6 35.5 µA
3-Phase - PS1, 2-Phase - PS0 16.75 20.6 24.25 µA
3-Phase - PS2, 2-Phase - PS1 and PS2 8.5 10.6 12.75 µA
VR2 Overcurrent Threshold All states 28.5 30.6 33.5 µA
LOGIC THRESHOLDS
VR_ON Input Low VIL 0.3 V
VR_ON Input High VIH HRTZ 0.7 V
VIH IRTZ 0.75 V
9 FN7835.0
March 12, 2011

ISL95836
-40°C to +100°C. (Continued)
MIN MAX
PWM
PWM Output Low V0L Sinking 5mA 1.0 V
PWM Output High V0H Sourcing 5mA 3.5 4.2 V
PWM Tri-State Leakage PWM = 2.5V 2 µA
THERMAL MONITOR
NTC Source Current NTC = 1.3V 59 60 61 µA
VR_HOT# Trip Voltage (VR1 and VR2) Falling 0.86 0.873 0.89 V
VR_HOT# Reset Voltage (VR1 Rising 0.905 0.929 0.935 V
and VR2)
Therm_Alert Trip Voltage (VR1 Falling 0.9 0.913 0.93 V
CONFIDENTIAL
and VR2)
Therm_Alert Reset Voltage (VR1 Rising 0.945 0.961 0.975 V
and VR2)
CURRENT MONITOR
IccMax_Alert Trip Voltage (VR1 Rising 2.63 2.66 2.69 V
IN REVIEW
and VR2)
IccMax_Alert reset Voltage (VR1 Falling 2.585 2.62 2.655 V
and VR2)
INPUTS
VR_ON Leakage Current IVR_ON VR_ON = 0V -1 0 µA
VR_ON = 1V 18 35 µA
SCLK, SDA Leakage VR_ON = 0V, SCLK & SDA = 0V & 1V -1 1 µA
VR_ON = 1V, SCLK & SDA = 1V -5 1 µA
VR_ON = 1V, SCLK & SDA = 0V -85 -60 -30 µA
SLEW RATE (For VID Change)
Fast Slew Rate 10 mV/µs
Slow Slew Rate 2.5 mV/µs
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
10 FN7835.0
March 12, 2011

ISL95836
Gate Driver Timing Diagram
PWM
tLGFUGR tFU
tRU
UGATE 1V
LGATE 1V
tRL
tFL tUGFLGR
Theory of Operation
CONFIDENTIAL
VW
Multiphase R3™ Modulator Vcrm Hysteretic
W indow
VW MASTER CLOCK CIRCUIT COMP
MASTER
MASTER COMP CLOCK Clock1
Phase
IN REVIEW
CLOCK Clock2 Master
Vcrm Sequencer
Clock3
Clock
gmVo Crm
Clock1
SLAVE CIRCUIT 1
L1 PW M1
Clock1 S PWM1 Phase1 Vo
VW Q
R
IL1 Co Clock2
Vcrs1
gm
PW M2
Crs1
SLAVE CIRCUIT 2 Clock3

L2
Clock2 S PWM2 Phase2
VW Q
R PW M3
IL2
VW
Vcrs2
gm
Crs2
SLAVE CIRCUIT 3 Vcrs2 Vcrs3 Vcrs1

L3
Clock3 S PWM3 Phase3
VW Q
R
IL3 FIGURE 3. R3™ MODULATOR OPERATION PRINCIPLES IN
STEADY STATE
Vcrs3
gm
Crs3
FIGURE 2. R3™ MODULATOR CIRCUIT
11 FN7835.0
March 12, 2011

ISL95836
Crs. The slave circuit turns on its PWM pulse upon receiving the
VW
clock signal, and the current source charges Crs. When Crs
voltage VCrs hits VW, the slave circuit turns off the PWM pulse,
and the current source discharges Crs.
COMP
Vcrm Since the controller works with Vcrs, which are large-amplitude
and noise-free synthesized signals, it achieves lower phase jitter
than conventional hysteretic mode and fixed PWM mode
Master
Clock controllers. Unlike conventional hysteretic mode converters, the
Clock1 ISL95836 uses an error amplifier that allows the controller to
PWM1
maintain a 0.5% output voltage accuracy.
Clock2 Figure 4 shows the operation principles during load insertion

response. The COMP voltage rises during load insertion,
PWM2
generating the master clock signal more quickly, so the PWM
Clock3 pulses turn on earlier, increasing the effective switching
PWM3 frequency, which allows for higher control loop bandwidth than
conventional fixed frequency PWM controllers. The VW voltage
CONFIDENTIAL
VW rises as the COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It takes
the master clock circuit longer to generate the next master clock
signal so the PWM pulse is held off until needed. The VW voltage
Vcrs1 falls as the COMP voltage falls, reducing the current PWM pulse
IN REVIEW
Vcrs3
Vcrs2 width. This kind of behavior gives the controller excellent
response speed.
FIGURE 4. R3™ MODULATOR OPERATION PRINCIPLES IN LOAD
INSERTION RESPONSE The fact that all the phases share the same VW window voltage
also ensures excellent dynamic current balance among phases.
The ISL95836 is a multiphase regulator implementing Intel™
IMVP-7/VR12™ protocol. It has two voltage regulators, VR1 and
Diode Emulation and Period Stretching
VR2, on one chip. VR1 can be programmed for 1-, 2- or 3-phase
operation, and VR2 could be programmed for 2- or 1-phase
operation. The following description is based on VR1, but also
applies to VR2 because they are based on the same architecture. Phase
The ISL95836 uses Intersil patented R3™ (Robust Ripple

Regulator™) modulator. The R3™ modulator combines the best UGATE
features of fixed frequency PWM and hysteretic PWM while
eliminating many of their shortcomings. Figure 2 conceptually
LG ATE
shows the multiphase R3™ modulator circuit, and Figure 3 shows
the operation principles.
Inside the IC, the modulator uses the master clock circuit to IL
generate the clocks for the slave circuits. The modulator
discharges the ripple capacitor Crm with a current source equal
FIGURE 5. DIODE EMULATION
to gmVo, where gm is a gain factor. Crm voltage Vcrm is a
sawtooth waveform traversing between the VW and COMP ISL95836 can operate in diode emulation (DE) mode to improve
voltages. It resets to VW when it hits COMP, and generates a light load efficiency. In DE mode, the low-side MOSFET conducts
one-shot master clock signal. A phase sequencer distributes the when the current is flowing from source to drain and doesn’t allow
master clock signal to the slave circuits. If VR1 is in 3-phase reverse current, emulating a diode. As Figure 5 shows, when
mode, the master clock signal will be distributed to the three LGATE is on, the low-side MOSFET carries current, creating
phases, and the Clock1~3 signals will be 120° out-of-phase. If negative voltage on the phase node due to the voltage drop across
VR1 is in 2-phase mode, the master clock signal will be the ON-resistance. The controller monitors the current through
distributed to Phases 1 and 2, and the Clock1 and Clock2 signals monitoring the phase node voltage. It turns off LGATE when the
will be 180° out-of-phase. If VR1 is in 1-phase mode, the master phase node voltage reaches zero to prevent the inductor current
clock signal will be distributed to Phases 1 only and be the from reversing the direction and creating unnecessary power loss.
Clock1 signal.
If the load current is light enough, as Figure 5 shows, the inductor
Each slave circuit has its own ripple capacitor Crs, whose voltage
current will reach and stay at zero before the next phase node
mimics the inductor ripple current. A gm amplifier converts the
pulse and the regulator is in discontinuous conduction mode
inductor voltage into a current source to charge and discharge
(DCM). If the load current is heavy enough, the inductor current
12 FN7835.0
March 12, 2011

ISL95836
will never reach 0A, and the regulator is in CCM although the Voltage Regulation and Load Line
controller is in DE mode. Implementation
Figure 6 shows the operation principle in diode emulation mode at After the start sequence, the controller regulates the output
light load. The load gets incrementally lighter in the three cases voltage to the value set by the VID information per Table 1. The
from top to bottom. The PWM on-time is determined by the VW controller will control the no-load output voltage to an accuracy of
window size, therefore is the same, making the inductor current ±0.5% over the range of 0.75V to 1.52V. A differential amplifier
triangle the same in the three cases. The controller clamps the allows voltage sensing for precise voltage regulation at the
ripple capacitor voltage Vcrs in DE mode to make it mimic the microprocessor die.
inductor current. It takes the COMP voltage longer to hit Vcrs, TABLE 1. VID TABLE
naturally stretching the switching period. The inductor current
VID
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The 7 6 5 4 3 2 1 0 Hex VO (V)
reduced switching frequency helps increase light load efficiency. 0 0 0 0 0 0 0 0 0 0 0.00000
CCM/DCM BOUNDARY 0 0 0 0 0 0 0 1 0 1 0.25000
VW
Vcrs 0 0 0 0 0 0 1 0 0 2 0.25500
CONFIDENTIAL
0 0 0 0 0 0 1 1 0 3 0.26000
0 0 0 0 0 1 0 0 0 4 0.26500
iL
0 0 0 0 0 1 0 1 0 5 0.27000
LIGHT DCM
VW
0 0 0 0 0 1 1 0 0 6 0.27500
IN REVIEW
Vcrs
0 0 0 0 0 1 1 1 0 7 0.28000
0 0 0 0 1 0 0 0 0 8 0.28500
iL 0 0 0 0 1 0 0 1 0 9 0.29000
DEEP DCM
VW
0 0 0 0 1 0 1 0 0 A 0.29500
Vcrs
0 0 0 0 1 0 1 1 0 B 0.30000
0 0 0 0 1 1 0 0 0 C 0.30500
iL 0 0 0 0 1 1 0 1 0 D 0.31000
0 0 0 0 1 1 1 0 0 E 0.31500
FIGURE 6. PERIOD STRETCHING 0 0 0 0 1 1 1 1 0 F 0.32000
0 0 0 1 0 0 0 0 1 0 0.32500
Start-up Timing
0 0 0 1 0 0 0 1 1 1 0.33000
With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the logic high 0 0 0 1 0 0 1 0 1 2 0.33500
threshold. Figure 7 shows the typical start-up timing of VR1 and 0 0 0 1 0 0 1 1 1 3 0.34000
VR2. The controller uses digital soft-start to ramp-up DAC to the
voltage programmed by the SetVID command. PGOOD is asserted 0 0 0 1 0 1 0 0 1 4 0.34500
high and ALERT# is asserted low at the end of the ramp up. Similar 0 0 0 1 0 1 0 1 1 5 0.35000
results occur if VR_ON is tied to VDD, with the soft-start sequence
starting 800µs after VDD crosses the POR threshold. 0 0 0 1 0 1 1 0 1 6 0.35500
0 0 0 1 0 1 1 1 1 7 0.36000
VDD 0 0 0 1 1 0 0 0 1 8 0.36500
VR_ON SLEW RATE 0 0 0 1 1 0 0 1 1 9 0.37000

2.5mV/µs VID
VID 0 0 0 1 1 0 1 0 1 A 0.37500
COMMAND
2.7ms VOLTAGE 0 0 0 1 1 0 1 1 1 B 0.38000
DAC
0 0 0 1 1 1 0 0 1 C 0.38500
PGOOD 0 0 0 1 1 1 0 1 1 D 0.39000
…...
ALERT# 0 0 0 1 1 1 1 0 1 E 0.39500
FIGURE 7. VR1 SOFT-START WAVEFORMS 0 0 0 1 1 1 1 1 1 F 0.40000
13 FN7835.0
March 12, 2011

ISL95836
TABLE 1. VID TABLE (Continued) TABLE 1. VID TABLE (Continued)
VID VID
7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)
0 0 1 0 0 0 0 0 2 0 0.40500 0 1 0 0 0 1 1 1 4 7 0.60000
0 0 1 0 0 0 0 1 2 1 0.41000 0 1 0 0 1 0 0 0 4 8 0.60500
0 0 1 0 0 0 1 0 2 2 0.41500 0 1 0 0 1 0 0 1 4 9 0.61000
0 0 1 0 0 0 1 1 2 3 0.42000 0 1 0 0 1 0 1 0 4 A 0.61500
0 0 1 0 0 1 0 0 2 4 0.42500 0 1 0 0 1 0 1 1 4 B 0.62000
0 0 1 0 0 1 0 1 2 5 0.43000 0 1 0 0 1 1 0 0 4 C 0.62500
0 0 1 0 0 1 1 0 2 6 0.43500 0 1 0 0 1 1 0 1 4 D 0.63000
0 0 1 0 0 1 1 1 2 7 0.44000 0 1 0 0 1 1 1 0 4 E 0.63500
0 0 1 0 1 0 0 0 2 8 0.44500 0 1 0 0 1 1 1 1 4 F 0.64000
0 0 1 0 1 0 0 1 2 9 0.45000 0 1 0 1 0 0 0 0 5 0 0.64500
CONFIDENTIAL
0 0 1 0 1 0 1 0 2 A 0.45500 0 1 0 1 0 0 0 1 5 1 0.65000
0 0 1 0 1 0 1 1 2 B 0.46000 0 1 0 1 0 0 1 0 5 2 0.65500
0 0 1 0 1 1 0 0 2 C 0.46500 0 1 0 1 0 0 1 1 5 3 0.66000
IN REVIEW
0 0 1 0 1 1 0 1 2 D 0.47000 0 1 0 1 0 1 0 0 5 4 0.66500
0 0 1 0 1 1 1 0 2 E 0.47500 0 1 0 1 0 1 0 1 5 5 0.67000
0 0 1 0 1 1 1 1 2 F 0.48000 0 1 0 1 0 1 1 0 5 6 0.67500
0 0 1 1 0 0 0 0 3 0 0.48500 0 1 0 1 0 1 1 1 5 7 0.68000
0 0 1 1 0 0 0 1 3 1 0.49000 0 1 0 1 1 0 0 0 5 8 0.68500
0 0 1 1 0 0 1 0 3 2 0.49500 0 1 0 1 1 0 0 1 5 9 0.69000
0 0 1 1 0 0 1 1 3 3 0.50000 0 1 0 1 1 0 1 0 5 A 0.69500
0 0 1 1 0 1 0 0 3 4 0.50500 0 1 0 1 1 0 1 1 5 B 0.70000
0 0 1 1 0 1 0 1 3 5 0.51000 0 1 0 1 1 1 0 0 5 C 0.70500
0 0 1 1 0 1 1 0 3 6 0.51500 0 1 0 1 1 1 0 1 5 D 0.71000
0 0 1 1 0 1 1 1 3 7 0.52000 0 1 0 1 1 1 1 0 5 E 0.71500
0 0 1 1 1 0 0 0 3 8 0.52500 0 1 0 1 1 1 1 1 5 F 0.72000
0 0 1 1 1 0 0 1 3 9 0.53000 0 1 1 0 0 0 0 0 6 0 0.72500
0 0 1 1 1 0 1 0 3 A 0.53500 0 1 1 0 0 0 0 1 6 1 0.73000
0 0 1 1 1 0 1 1 3 B 0.54000 0 1 1 0 0 0 1 0 6 2 0.73500
0 0 1 1 1 1 0 0 3 C 0.54500 0 1 1 0 0 0 1 1 6 3 0.74000
0 0 1 1 1 1 0 1 3 D 0.55000 0 1 1 0 0 1 0 0 6 4 0.74500
0 0 1 1 1 1 1 0 3 E 0.55500 0 1 1 0 0 1 0 1 6 5 0.75000
0 0 1 1 1 1 1 1 3 F 0.56000 0 1 1 0 0 1 1 0 6 6 0.75500
0 1 0 0 0 0 0 0 4 0 0.56500 0 1 1 0 0 1 1 1 6 7 0.76000
0 1 0 0 0 0 0 1 4 1 0.57000 0 1 1 0 1 0 0 0 6 8 0.76500
0 1 0 0 0 0 1 0 4 2 0.57500 0 1 1 0 1 0 0 1 6 9 0.77000
0 1 0 0 0 0 1 1 4 3 0.58000 0 1 1 0 1 0 1 0 6 A 0.77500
0 1 0 0 0 1 0 0 4 4 0.58500 0 1 1 0 1 0 1 1 6 B 0.78000
0 1 0 0 0 1 0 1 4 5 0.59000 0 1 1 0 1 1 0 0 6 C 0.78500
0 1 0 0 0 1 1 0 4 6 0.59500 0 1 1 0 1 1 0 1 6 D 0.79000
14 FN7835.0
March 12, 2011
F r e e D a t a s h e e t
ISL95836
VID VID
7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)
0 1 1 0 1 1 1 0 6 E 0.79500 1 0 0 1 0 1 0 1 9 5 0.99000
0 1 1 0 1 1 1 1 6 F 0.80000 1 0 0 1 0 1 1 0 9 6 0.99500
0 1 1 1 0 0 0 0 7 0 0.80500 1 0 0 1 0 1 1 1 9 7 1.00000
0 1 1 1 0 0 0 1 7 1 0.81000 1 0 0 1 1 0 0 0 9 8 1.00500
0 1 1 1 0 0 1 0 7 2 0.81500 1 0 0 1 1 0 0 1 9 9 1.01000
0 1 1 1 0 0 1 1 7 3 0.82000 1 0 0 1 1 0 1 0 9 A 1.01500
0 1 1 1 0 1 0 0 7 4 0.82500 1 0 0 1 1 0 1 1 9 B 1.02000
0 1 1 1 0 1 0 1 7 5 0.83000 1 0 0 1 1 1 0 0 9 C 1.02500
0 1 1 1 0 1 1 0 7 6 0.83500 1 0 0 1 1 1 0 1 9 D 1.03000
0 1 1 1 0 1 1 1 7 7 0.84000 1 0 0 1 1 1 1 0 9 E 1.03500
CONFIDENTIAL
0 1 1 1 1 0 0 0 7 8 0.84500 1 0 0 1 1 1 1 1 9 F 1.04000
0 1 1 1 1 0 0 1 7 9 0.85000 1 0 1 0 0 0 0 0 A 0 1.04500
0 1 1 1 1 0 1 0 7 A 0.85500 1 0 1 0 0 0 0 1 A 1 1.05000
IN REVIEW
0 1 1 1 1 0 1 1 7 B 0.86000 1 0 1 0 0 0 1 0 A 2 1.05500
0 1 1 1 1 1 0 0 7 C 0.86500 1 0 1 0 0 0 1 1 A 3 1.06000
0 1 1 1 1 1 0 1 7 D 0.87000 1 0 1 0 0 1 0 0 A 4 1.06500
0 1 1 1 1 1 1 0 7 E 0.87500 1 0 1 0 0 1 0 1 A 5 1.07000
0 1 1 1 1 1 1 1 7 F 0.88000 1 0 1 0 0 1 1 0 A 6 1.07500
1 0 0 0 0 0 0 0 8 0 0.88500 1 0 1 0 0 1 1 1 A 7 1.08000
1 0 0 0 0 0 0 1 8 1 0.89000 1 0 1 0 1 0 0 0 A 8 1.08500
1 0 0 0 0 0 1 0 8 2 0.89500 1 0 1 0 1 0 0 1 A 9 1.09000
1 0 0 0 0 0 1 1 8 3 0.90000 1 0 1 0 1 0 1 0 A A 1.09500
1 0 0 0 0 1 0 0 8 4 0.90500 1 0 1 0 1 0 1 1 A B 1.10000
1 0 0 0 0 1 0 1 8 5 0.91000 1 0 1 0 1 1 0 0 A C 1.10500
1 0 0 0 0 1 1 0 8 6 0.91500 1 0 1 0 1 1 0 1 A D 1.11000
1 0 0 0 0 1 1 1 8 7 0.92000 1 0 1 0 1 1 1 0 A E 1.11500
1 0 0 0 1 0 0 0 8 8 0.92500 1 0 1 0 1 1 1 1 A F 1.12000
1 0 0 0 1 0 0 1 8 9 0.93000 1 0 1 1 0 0 0 0 B 0 1.12500
1 0 0 0 1 0 1 0 8 A 0.93500 1 0 1 1 0 0 0 1 B 1 1.13000
1 0 0 0 1 0 1 1 8 B 0.94000 1 0 1 1 0 0 1 0 B 2 1.13500
1 0 0 0 1 1 0 0 8 C 0.94500 1 0 1 1 0 0 1 1 B 3 1.14000
1 0 0 0 1 1 0 1 8 D 0.95000 1 0 1 1 0 1 0 0 B 4 1.14500
1 0 0 0 1 1 1 0 8 E 0.95500 1 0 1 1 0 1 0 1 B 5 1.15000
1 0 0 0 1 1 1 1 8 F 0.96000 1 0 1 1 0 1 1 0 B 6 1.15500
1 0 0 1 0 0 0 0 9 0 0.96500 1 0 1 1 0 1 1 1 B 7 1.16000
1 0 0 1 0 0 0 1 9 1 0.97000 1 0 1 1 1 0 0 0 B 8 1.16500
1 0 0 1 0 0 1 0 9 2 0.97500 1 0 1 1 1 0 0 1 B 9 1.17000
1 0 0 1 0 0 1 1 9 3 0.98000 1 0 1 1 1 0 1 0 B A 1.17500
1 0 0 1 0 1 0 0 9 4 0.98500 1 0 1 1 1 0 1 1 B B 1.18000
15 FN7835.0
March 12, 2011
ISL95836
VID VID
7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)
1 0 1 1 1 1 0 0 B C 1.18500 1 1 1 0 0 0 1 1 E 3 1.38000
1 0 1 1 1 1 0 1 B D 1.19000 1 1 1 0 0 1 0 0 E 4 1.38500
1 0 1 1 1 1 1 0 B E 1.19500 1 1 1 0 0 1 0 1 E 5 1.39000
1 0 1 1 1 1 1 1 B F 1.20000 1 1 1 0 0 1 1 0 E 6 1.39500
1 1 0 0 0 0 0 0 C 0 1.20500 1 1 1 0 0 1 1 1 E 7 1.40000
1 1 0 0 0 0 0 1 C 1 1.21000 1 1 1 0 1 0 0 0 E 8 1.40500
1 1 0 0 0 0 1 0 C 2 1.21500 1 1 1 0 1 0 0 1 E 9 1.41000
1 1 0 0 0 0 1 1 C 3 1.22000 1 1 1 0 1 0 1 0 E A 1.41500
1 1 0 0 0 1 0 0 C 4 1.22500 1 1 1 0 1 0 1 1 E B 1.42000
1 1 0 0 0 1 0 1 C 5 1.23000 1 1 1 0 1 1 0 0 E C 1.42500
CONFIDENTIAL
1 1 0 0 0 1 1 0 C 6 1.23500 1 1 1 0 1 1 0 1 E D 1.43000
1 1 0 0 0 1 1 1 C 7 1.24000 1 1 1 0 1 1 1 0 E E 1.43500
1 1 0 0 1 0 0 0 C 8 1.24500 1 1 1 0 1 1 1 1 E F 1.44000
IN REVIEW
1 1 0 0 1 0 0 1 C 9 1.25000 1 1 1 1 0 0 0 0 F 0 1.44500
1 1 0 0 1 0 1 0 C A 1.25500 1 1 1 1 0 0 0 1 F 1 1.45000
1 1 0 0 1 0 1 1 C B 1.26000 1 1 1 1 0 0 1 0 F 2 1.45500
1 1 0 0 1 1 0 0 C C 1.26500 1 1 1 1 0 0 1 1 F 3 1.46000
1 1 0 0 1 1 0 1 C D 1.27000 1 1 1 1 0 1 0 0 F 4 1.46500
1 1 0 0 1 1 1 0 C E 1.27500 1 1 1 1 0 1 0 1 F 5 1.47000
1 1 0 0 1 1 1 1 C F 1.28000 1 1 1 1 0 1 1 0 F 6 1.47500
1 1 0 1 0 0 0 0 D 0 1.28500 1 1 1 1 0 1 1 1 F 7 1.48000
1 1 0 1 0 0 0 1 D 1 1.29000 1 1 1 1 1 0 0 0 F 8 1.48500
1 1 0 1 0 0 1 0 D 2 1.29500 1 1 1 1 1 0 0 1 F 9 1.49000
1 1 0 1 0 0 1 1 D 3 1.30000 1 1 1 1 1 0 1 0 F A 1.49500
1 1 0 1 0 1 0 0 D 4 1.30500 1 1 1 1 1 0 1 1 F B 1.50000
1 1 0 1 0 1 0 1 D 5 1.31000 1 1 1 1 1 1 0 0 F C 1.50500
1 1 0 1 0 1 1 0 D 6 1.31500 1 1 1 1 1 1 0 1 F D 1.51000
1 1 0 1 0 1 1 1 D 7 1.32000 1 1 1 1 1 1 1 0 F E 1.51500
1 1 0 1 1 0 0 0 D 8 1.32500 1 1 1 1 1 1 1 1 F F 1.52000
1 1 0 1 1 0 0 1 D 9 1.33000
1 1 0 1 1 0 1 0 D A 1.33500
1 1 0 1 1 0 1 1 D B 1.34000
1 1 0 1 1 1 0 0 D C 1.34500
1 1 0 1 1 1 0 1 D D 1.35000
1 1 0 1 1 1 1 0 D E 1.35500
1 1 0 1 1 1 1 1 D F 1.36000
1 1 1 0 0 0 0 0 E 0 1.36500
1 1 1 0 0 0 0 1 E 1 1.37000
1 1 1 0 0 0 1 0 E 2 1.37500
16 FN7835.0
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ISL95836
VCC SENSE + V = V DAC + VSS SENSE (EQ. 3)

droop
Rdroop
VCCSENSE
Vdroop
FB
VCC SENSE – VSS SENSE = V DAC – R droop  I droop (EQ. 4)
VR LOCAL VO
Idroop
“CATCH”
RESISTOR
Equation 4 is the exact equation required for load line
implementation.
E/A VIDs
COMP
 VDAC
DAC VID The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
RTN
VSSSENSE
Figure 8 shows, it is recommended to add a “catch” resistor to feed
INTERNAL TO IC X1 VSS
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
“CATCH” RESISTOR RTN pin. These resistors, typically 10~100, will provide voltage
feedback if the system is powered up without a processor installed.
FIGURE 8. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION Phase Current Balancing
L3 Rdcr3
CONFIDENTIAL
Rpcb3
As the load current increases from zero, the output voltage will Phase3
droop from the VID table value by an amount proportional to the Risen
ISEN3 IL3
load current to achieve the load line. The controller can sense the
Cisen
inductor current through the intrinsic DC Resistance (DCR) of the L2 Rdcr2
Rpcb2
INTERNAL Vo
inductors (as shown in Figure 1) or through resistors in series TO IC Phase2
with the inductors (as shown in Figure 2). In both methods, Risen
IN REVIEW
ISEN2 IL2
capacitor Cn voltage represents the inductor total currents. A Cisen
droop amplifier converts Cn voltage into an internal current L1 Rdcr1
Rpcb1
source with the gain set by resistor Ri. The current source is used Phase1
Risen
for load line implementation, current monitor and overcurrent ISEN1 IL1
protection. Cisen
Figure 8 shows the load line implementation. The controller

drives a current source Idroop out of the FB pin, described by FIGURE 9. CURRENT BALANCING CIRCUIT
Equation 1.
The controller monitors individual phase average current by
V Cn (EQ. 1)
I droop = --------- monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 9
Ri
shows the recommended current balancing circuit. Each phase
When using inductor DCR current sensing, a single NTC element node voltage is averaged by a low-pass filter consisting of Risen
is used to compensate the positive temperature coefficient of the and Cisen, and presented to the corresponding ISEN pin. Risen
copper winding thus sustaining the load line accuracy with should be routed to inductor phase-node pad in order to
reduced cost. eliminate the effect of phase node parasitic PCB DCR. Equations
5 thru 7 give the ISEN pin voltages:
Idroop flows through resistor Rdroop and creates a voltage drop,
as shown in Equation 2. V ISEN1 =  R dcr1 + R pcb1   I L1 (EQ. 5)
V droop = R droop  I droop (EQ. 2)

V ISEN2 =  R dcr2 + R pcb2   I L2 (EQ. 6)
Vdroop is the droop voltage required to implement load line.

Changing Rdroop or scaling Idroop can both change the load line V ISEN3 =  R dcr3 + R pcb3   I L3 (EQ. 7)
slope. Since Idroop also sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement, where Rdcr1, Rdcr2 and Rdcr3 are inductor DCR; Rpcb1, Rpcb2
then select an appropriate Rdroop value to obtain the desired and Rpcb3 are parasitic PCB DCR between the inductor output
load line slope. side pad and the output voltage rail; and IL1, IL2 and IL3 are
inductor average currents.
Differential Voltage Sensing
Figure 8 also shows the differential voltage sensing scheme. The controller will adjust the phase pulse-width relative to the
VCCSENSE and VSSSENSE are the remote voltage sensing signals other phases to make VISEN1 = VISEN2 = VISEN3, thus to achieve
from the processor die. A unity gain differential amplifier senses IL1 = IL2 = IL3, when there are Rdcr1 = Rdcr2 = Rdcr3 and
the VSSSENSE voltage and adds it to the DAC output. The error Rpcb1 = Rpcb2 = Rpcb3.
amplifier regulates the inverting and the non-inverting input
voltages to be equal, as shown in Equation 3: Using the same components for L1, L2 and L3 will provide a good
match of Rdcr1, Rdcr2 and Rdcr3. Board layout will determine
Rewriting Equation 3 and substitution of Equation 2 gives:
17 FN7835.0
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ISL95836
Rpcb1, Rpcb2 and Rpcb3. It is recommended to have symmetrical V ISEN2 = V 1n + V 2p + V 3n (EQ. 9)
layout for the power delivery path between each inductor and the
V ISEN3 = V 1n + V 2n + V 3p (EQ. 10)
output voltage rail, such that Rpcb1 = Rpcb2 = Rpcb3.
The controller will make VISEN1 = VISEN2 = VISEN3, as shown in
L3 Rdcr3 Rpcb3
V3p Equations 11 and 12:
Phase3
Risen V 1p + V 2n + V 3n = V 1n + V 2p + V 3n (EQ. 11)
ISEN3 IL3 V3n
Cisen Risen V 1n + V 2p + V 3n = V 1n + V 2n + V 3p (EQ. 12)
INTERNAL Risen
TO IC L2 Rdcr2 Rpcb2 Vo Rewriting Equation 11 gives Equation 13:
V2p
Phase2 V 1p – V 1n = V 2p – V 2n (EQ. 13)
Risen
ISEN2 IL2 V2n
Cisen Risen and rewriting Equation 12 gives Equation 14:
Risen V 2p – V 2n = V 3p – V 3n (EQ. 14)
L1 Rdcr1 Rpcb1
V1p
Phase1 Combining Equations 13 and 14 gives:
Risen V 1p – V 1n = V 2p – V 2n = V 3p – V 3n
ISEN1 IL1 V1n (EQ. 15)
Cisen Risen
CONFIDENTIAL
Risen Therefore:
R dcr1  I L1 = R dcr2  I L2 = R dcr3  I L3 (EQ. 16)

FIGURE 10. DIFFERENTIAL-SENSING CURRENT BALANCING
CIRCUIT
Current balancing (IL1 = IL2 = IL3) will be achieved when there is
Rdcr1 = Rdcr2 = Rdcr3. Rpcb1, Rpcb2 and Rpcb3 will not have any
IN REVIEW
Sometimes, it is difficult to implement symmetrical layout. For effect.
the circuit shown in Figure 9, asymmetric layout causes different
Since the slave ripple capacitor voltages mimic the inductor currents,
Rpcb1, Rpcb2 and Rpcb3 thus current imbalance. Figure 10
R3™ modulator can naturally achieve excellent current balancing
shows a recommended differential-sensing current balancing during steady state and dynamic operations. Figure 11 shows current
circuit. The current sensing traces should be routed to the balancing performance of the evaluation board with load transient of
inductor pads so they only pick up the inductor DCR voltage. Each 12A/51A at different rep rates. The inductor currents follow the load
ISEN pin sees the average voltage of three sources: its own phase current dynamic change with the output capacitors supplying the
inductor phase-node pad, and the other two phases inductor difference. The inductor currents can track the load current well at low
output side pads. Equations 8 thru 10 give the ISEN pin voltages: rep rate, but cannot keep up when the rep rate gets into the
V ISEN1 = V 1p + V 2n + V 3n (EQ. 8) hundred-kHz range, where it’s out of the control loop bandwidth. The
controller achieves excellent current balancing in all cases.
18 FN7835.0
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ISL95836
CCM Switching Frequency
REP RATE = 10kHz
The resistor form COMPG and GND sets four different switching
frequencies: 300kHz, 350kHz, 400kHz and 450kHz. Please refer
Table 8 for details.
Modes of Operation
TABLE 2. VR1 MODES OF OPERATION
OCP Threshold
PWM3 ISEN2 CONFIG. PS MODE (µA)
To To 3-phase 0 3-phase CCM 60
External Power CPU VR
1 2-phase CCM 40
REP RATE = 25kHz Driver Stage Config.
2 1-phase DE 20
3
Tied to 5V 2-phase 0 2-phase CCM 60
CPU VR
1 1-phase CCM 30
CONFIDENTIAL
Config.
2 1-phase DE
3
Tied to 1-phase 0 1-phase CCM 60
5V CPU VR
1
Config.
IN REVIEW
REP RATE = 50kHz 2 1-phase DE
3
VR1 can be configured for 3, 2 or 1-phase operation. Table 2

shows VR1 configurations and operational modes, programmed
by the PWM3 pin and the ISEN2 pin status, and the PS
command. For 2-phase configuration, tie the PWM3 pin to 5V. In
this configuration, phases 1 and 2 are active. For 1-phase
configuration, tie the PWM3 pin and the ISEN2 pin to 5V. In this
configuration, only phase-1 is active.
REP RATE = 100kHz In 3-phase configuration, VR1 operates in 3-phase CCM in PS0. It
enters 2-phase CCM in PS1 by dropping phase 3 and reducing
the overcurrent and the way-overcurrent protection levels to 2/3
of the initial values. It enters 1-phase DE mode in PS2 or PS3 by
dropping phases 3 and 2, and reduces the overcurrent and the
way-overcurrent protection levels to 1/3 of the initial values.
In 2-phase configuration, VR1 operates in 2-phase CCM in PS0. It
enters 1-phase CCM in PS1 and enters 1-phase DE mode in PS2
or PS3 by dropping phase 2, and reducing the overcurrent and
the way-overcurrent protection levels to 1/2 of the initial values.
In 1-phase configuration, VR1 operates in 1-phase CCM in PS0
REP RATE = 200kHz and PS1, and enters 1-phase DE mode in PS2 and PS3.
TABLE 3. VR2 MODES OF OPERATION
OCP Threshold
ISEN2G PS MODE (µA)
To Power Stage 0 2-phase CCM 60
1 1-phase CCM 30
2 1-phase DE
3
FIGURE 11. CURRENT BALANCING DURING DYNAMIC
OPERATION. CH1: IL1, CH2: ILOAD, CH3: IL2, CH4:
IL3
19 FN7835.0
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ISL95836
TABLE 3. VR2 MODES OF OPERATION command. At t3, Vo reaches the new target voltage and the
OCP Threshold controller asserts the ALERT# signal.
ISEN2G PS MODE (µA) The R3™ modulator intrinsically has voltage feed-forward. The
Tied to 5V 0 1-phase CCM 60 output voltage is insensitive to a fast slew rate input voltage
1 change.
2 1-phase DE VR_HOT#/ALERT# Behavior

3
VR Temperature 3% Hysteris
Temp Zone
Table 3 shows VR2 operational modes, programmed by the Bit 7 =1 7 1111 1111
ISEN2G pin status and PS command. For 2-phase configuration,
Bit 6 =1 1 10 0111 1111
connect the ISEN2G pin to power stage. In this configuration,
phases 1 and 2 are active. For 1-phase configuration, tie tthe 0011 1111
Bit 5 =1
ISEN2G pin to 5V. In this configuration, only phase-1 is active. 12 0001 1111
VR2 can be disabled completely by tying ISUMNG to 5V, and all Temp Zone
communication to VR2 will be rejected. Register 2 8
0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111
Dynamic Operation Status 1 3
CONFIDENTIAL
Register = “001” = “011” = “001”
VR1 and VR2 behave the same during dynamic operation. The GerReg 5 13 GerReg 15
SVID Status1 Status1
controller responds to VID changes by slewing to the new voltage
at a slew rate indicated in the SetVID command. There are three ALERT# 4 6 14 16
SetVID slew rates, namely SetVID_fast, SetVID_slow and
SetVID_decay.
IN REVIEW
VR_HOT#
9 11
SetVID_fast command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a FIGURE 13. VR_HOT#/ALERT# BEHAVIOR
minimum 10mV/µs slew rate.
The controller drives 60µA current source out of the NTC pin and
SetVID_slow command prompts the controller to enter CCM and the NTCG pin alternatively at 1kHz frequency with 50% duty
to actively drive the output voltage to the new VID value at a cycle. The current source flows through the respective NTC
minimum 2.5mV/µs slew rate. resistor networks on the pins and creates voltages that are
monitored by the controller through an A/D converter (ADC) to
SetVID_decay command prompts the controller to enter DE
generate the Tzone value. Table 4 shows the programming table
mode. The output voltage will decay down to the new VID value at
for Tzone. The user needs to scale the NTC and the NTCG network
a slew rate determined by the load. If the voltage decay rate is
resistance such that it generates the NTC (and NTCG) pin voltage
too fast, the controller will limit the voltage slew rate at
that corresponds to the left-most column. Do not use any
SetVID_slow slew rate.
capacitor to filter the voltage.
ALERT# will be asserted low at the end of SetVID_fast and
TABLE 4. TZONE TABLE
SetVID_slow VID transitions.
VNTC (V) TMAX (%) TZONE
S e tV ID _ d e c a y S e tV ID _ fa s t/s lo w 0.84 >100 FFh
0.88 100 FFh
Vo 0.92 97 7Fh
0.96 94 3Fh
V ID 1.00 91 1Fh
t3
1.04 88 0Fh
t1 T _ a le r t
t2 1.08 85 07h
ALERT#
1.12 82 03h
1.16 79 01h
FIGURE 12. SETVID DECAY PRE-EMPTIVE BEHAVIOR
1.2 76 01h
Figure 12 shows SetVID Decay Pre-Emptive behavior. The
controller receives a SetVID_decay command at t1. The VR >1.2 <76 00h
enters DE mode and the output voltage Vo decays down slowly. Figure 13 shows the how the NTC and the NTCG network should be
At t2, before Vo reaches the intended VID target of the designed to get correct VR_HOT#/ALERT# behavior when the
SetVID_decay command, the controller receives a SetVID_fast (or system temperature rises and falls, manifested as the NTC and the
SetVID_slow) command to go to a voltage higher than the actual NTCG pin voltage falls and rises. The series of events are:
Vo. The controller will turn around immediately and slew Vo to the
new target voltage at the slew rate specified by the SetVID
20 FN7835.0
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ISL95836
1. The temperature rises so the NTC pin (or the NTCG pin) The FB2 function ensures excellent transient response in both
voltage drops. Tzone value changes accordingly. 2-phase mode and 1-phase mode. If one decides not to use the
2. The temperature crosses the threshold where Tzone register FB2 function, simply populate C3.1 only.
Bit 6 changes from 0 to 1.
Adaptive Body Diode Conduction Time
3. The controller changes Status_1 register bit 1 from 0 to 1.
Reduction
4. The controller asserts ALERT#.
In DCM, the controller turns off the low-side MOSFET when the
5. The CPU reads Status_1 register value to know that the alert
inductor current approaches zero. During on-time of the low-side
assertion is due to Tzone register bit 6 flipping.
MOSFET, phase voltage is negative and the amount is the
6. The controller clears ALEERT#. MOSFET rDS(ON) voltage drop, which is proportional to the
7. The temperature continues rising. inductor current. A phase comparator inside the controller
8. The temperature crosses the threshold where Tzone register monitors the phase voltage during on-time of the low-side
Bit 7 changes from 0 to 1. MOSFET and compares it with a threshold to determine the
zero-crossing point of the inductor current. If the inductor current
9. The controllers asserts VR_HOT# signal. The CPU throttles has not reached zero when the low-side MOSFET turns off, it’ll
back and the system temperature starts dropping eventually. flow through the low-side MOSFET body diode, causing the phase
10. The temperature crosses the threshold where Tzone register node to have a larger voltage drop until it decays to zero. If the
bit 6 changes from 1 to 0. This threshold is 1 ADC step lower inductor current has crossed zero and reversed the direction
CONFIDENTIAL
than the one when VR_HOT# gets asserted, to provide 3% when the low-side MOSFET turns off, it’ll flow through the
hysteresis. high-side MOSFET body diode, causing the phase node to have a
11. The controllers de-asserts VR_HOT# signal. spike until it decays to zero. The controller continues monitoring
the phase voltage after turning off the low-side MOSFET and
12. The temperature crosses the threshold where Tzone register
adjusts the phase comparator threshold voltage accordingly in
bit 5 changes from 1 to 0. This threshold is 1 ADC step lower
IN REVIEW
iterative steps such that the low-side MOSFET body diode
than the one when ALERT# gets asserted during the
conducts for approximately 40ns to minimize the body diode-
temperature rise to provide 3% hysteresis.
related loss.
13. The controller changes Status_1 register bit 1 from 1 to 0.
14. The controller asserts ALERT#. Protections
15. The CPU reads Status_1 register value to know that the alert VR1 and VR2 both provide overcurrent, current-balance and
assertion is due to Tzone register bit 5 flipping. overvoltage fault protections. The controller also provides over-
16. The controller clears ALERT#. temperature protection. The following discussion is based on VR1
and also applies to VR2.
FB2 Function The controller determines overcurrent protection (OCP) by
The FB2 function is only available for VR1 in 2-phase comparing the average value of the droop current Idroop with an
configuration. internal current source threshold as Table 2 shows. It declares OCP
CONTROLLER IN C1 R2
CONTROLLER IN
C1 R2 when Idroop is above the threshold for 120µs.
2-PHASE MODE 1-PHASE MODE
C3.1 C3.1 For overcurrent conditions above 1.5x the OCP level, the PWM
C2 R3 C3.2 C2 R3 C3.2
outputs will immediately shut off and PGOOD will go low to
FB2 FB2
maximize protection. This protection is also referred to as way-
R1 R1 overcurrent protection or fast-overcurrent protection, for short-
VSEN VSEN circuit protection.
FB E/A FB E/A
COMP COMP
VREF VREF The controller monitors the ISEN pin voltages to determine
FIGURE 14. FB2 FUNCTION current-balance protection. If the ISEN pin voltage difference is
greater than 9mV for 1ms, the controller will declare a fault and
Figure 14 shows the FB2 function. A switch (called FB2 switch) latch off.
turns on to short the FB and the FB2 pins when the controller is in The controller takes the same actions for all of the above fault
2-phase mode. Capacitors C3.1 and C3.2 are in parallel, serving protections: de-assertion of both PGOODs and turn-off of all the
as part of the compensator. When the controller enters 1-phase high-side and low-side power MOSFETs. Any residual inductor
mode, the FB2 switch turns off, removing C3.2 and leaving only current will decay through the MOSFET body diodes.
C3.1 in the compensator. The compensator gain will increase
with the removal of C3.2. By properly sizing C3.1 and C3.2, the The controller will declare an overvoltage fault and de-assert PGOOD
compensator cab be optimal for both 2-phase mode and 1-phase if the output voltage exceeds the VID set value by +200mV. The
mode. controller will immediately declare an OV fault, de-assert PGOOD,
and turn on the low-side power MOSFETs. The low-side power
When the FB2 switch is off, C3.2 is disconnected from the FB pin. MOSFETs remain on until the output voltage is pulled down below
However, the controller still actively drives the FB2 pin voltage to the VID set value when all power MOSFETs are turned off. If the
follow the FB pin voltage such that C3.2 voltage always follows output voltage rises above the VID set value +200mV again, the
C3.1 voltage. When the controller turns on the FB2 switch, C3.2 protection process is repeated. This behavior provides the
will be reconnected to the compensator smoothly.
21 FN7835.0
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ISL95836
maximum amount of protection against shorted high-side power TABLE 6. SUPPORTED DATA AND CONFIGURATION
MOSFETs while preventing output ringing below ground. REGISTERS (Continued)
Default
The overvoltage fault threshold is 1.7V when output voltage
Index Register Name Description Value
ramps up from 0V. And the overvoltage fault threshold is restored
to VID set value + 200mV after the output voltage settles. 12h Temperature Data register showing 00h
Zone temperature zones that have
All the above fault conditions can be reset by bringing VR_ON low been entered.
or by bringing VDD below the POR threshold. When VR_ON and
VDD return to their high operating levels, a soft-start will occur 1Ch Status_2_ This register contains a copy of 00h
LastRead the Status_2 data that was last
Table 5 summarizes the fault protections. read with the GetReg (Status_2)
command.
TABLE 5. FAULT PROTECTION SUMMARY
21h ICC max Data register containing the ICC Refer to
FAULT DURATION max the platform supports, set Table 7
BEFORE PROTECTION FAULT at start-up by resistors Rprog1
FAULT TYPE PROTECTION ACTION RESET and Rprog2. The platform
Overcurrent 120µs PWM tri-state, VR_ON design engineer programs this
PGOOD latched low toggle or value during the design process.
Phase Current 1ms Binary format in amps, i.e.
CONFIDENTIAL
VDD toggle
Unbalance 100A = 64h
Way-Overcurrent Immediately
22h Temp max Data register containing the Refer to
(1.5xOC)
temperature max the platform Table 8
Overvoltage PGOOD latched low. support, set at startup by
+200mV Actively pulls the resistor Rprog2. The platform
IN REVIEW
output voltage to design engineer programs this
below VID value, value during the design process.
then tri-state. Binary format in degree C, i.e.
100C = 64h
Supported Data And Configuration Registers
24h SR-fast Slew Rate Normal. The fastest 0Ah
The controller supports the following data and configuration slew rate the platform VR can
registers. sustain. Binary format in
mV/µs. i.e. 0Ah = 10mV/µs.
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS 25h SR-slow Is 4x slower than normal. Binary 02h
format in mV/µs. i.e.
Default
02h = 2.5mV/µs
Index Register Name Description Value
26h Vboot If programmed by the platform, 00h
00h Vendor ID Uniquely identifies the VR 12h
the VR supports Vboot voltage
vendor. Assigned by Intel.
during start-up ramp. The VR
01h Product ID Uniquely identifies the VR 1Fh will ramp to VBOOT and hold at
product. Intersil assigns this VBOOT until it receives a new
number. SetVID command to move to a
different voltage.
02h Product Uniquely identifies the revision
Revision of the VR control IC. Intersil 30h Vout max This register is programmed by FBh
assigns this data. the master and sets the
maximum VID the VR will
05h Protocol ID Identifies what revision of SVID 01h support. If a higher VID code is
protocol the controller supports. received, the VR will respond
06h Capability Identifies the SVID VR 81h with “not supported”
capabilities and which of the acknowledge.
optional telemetry registers are 31h VID Setting Data register containing 00h
supported. currently programmed VID
10h Status_1 Data register read after ALERT# 00h voltage. VID data format.
signal. Indicating if a VR rail has 32h Power State Register containing the current 00h
settled, has reached VRHOT programmed power state.
condition or has reached ICC
max.
11h Status_2 Data register showing status_2 00h

communication.
22 FN7835.0
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ISL95836
TABLE 6. SUPPORTED DATA AND CONFIGURATION frequency-domain relationship between inductor total current
REGISTERS (Continued) Io(s) and Cn voltage VCn(s):
Default  
 R ntcnet DCR
Index Register Name Description Value V Cn  s  =  -----------------------------------------  ------------  I o  s   A cs  s 
R sum N  (EQ. 17)

33h Voltage Offset Sets offset in VID steps added to 00h  R ntcnet + ------------- N
- 
the VID setting for voltage
margining. Bit 7 is a sign bit,  R ntcs + R ntc   R p
0 = positive margin, R ntcnet = --------------------------------------------------- (EQ. 18)
R ntcs + R ntc + R p
1 = negative margin.
s
Remaining 7 bits are # VID 1 + ------
L
steps for the margin. A cs  s  = ---------------------- (EQ. 19)
00h = no margin, s
1 + ------------
01h = +1 VID step  sns
02h = +2 VID steps...
DCR
 L = ------------ (EQ. 20)
34h Multi VR Data register that configures VR1: 00h L
Config multiple VRs behavior on the VR2: 01h
same SVID bus. 1
 sns = ------------------------------------------------------ (EQ. 21)
R sum
CONFIDENTIAL
R ntcnet  --------------
Key Component Selection N
-----------------------------------------  C n
R sum
R ntcnet + --------------
Inductor DCR Current-Sensing Network N
Phase1 Phase2 Phase3
where N is the number of phases.
Transfer function Acs(s) always has unity gain at DC. The inductor
IN REVIEW
Rsum
DCR value increases as the winding temperature increases,
Rsum
giving higher reading of the inductor DC current. The NTC Rntc
ISUM+
Rsum values decrease as its temperature decreases. Proper selections
of Rsum, Rntcs, Rp and Rntc parameters ensure that VCn
represent the inductor total DC current over the temperature
L L L Rntcs
range of interest.
Rp Cn Vcn
There are many sets of parameters that can properly temperature-
Rntc
DCR DCR DCR compensate the DCR change. Since the NTC network and the Rsum
Ro Ri ISUM- resistors form a voltage divider, Vcn is always a fraction of the
Ro inductor DCR voltage. It is recommended to have a higher ratio of
Vcn to the inductor DCR voltage, so the droop circuit has higher
Ro
signal level to work with.
A typical set of parameters that provide good temperature
Io compensation are: Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k
FIGURE 15. DCR CURRENT-SENSING NETWORK
and Rntc = 10k (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
Figure 15 shows the inductor DCR current-sensing network for a load DC current and record the output voltage reading
3-phase solution. An inductor current flows through the DCR and immediately; then record the output voltage reading again when
creates a voltage drop. Each inductor has two resistors in Rsum the board has reached the thermal steady state. A good NTC
and Ro connected to the pads to accurately sense the inductor network can limit the output voltage drift to within 2mV. It is
current by sensing the DCR voltage drop. The Rsum and Ro recommended to follow the Intersil evaluation board layout and
resistors are connected in a summing network as shown, and feed current-sensing network parameters to minimize engineering
the total current information to the NTC network (consisting of time.
Rntcs, Rntc and Rp) and capacitor Cn. Rntc is a negative VCn(s) also needs to represent real-time Io(s) for the controller to
temperature coefficient (NTC) thermistor, used to achieve good transient response. Transfer function Acs(s) has a
temperature-compensate the inductor DCR change. pole wsns and a zero wL. One needs to match wL and wsns so
The inductor output side pads are electrically shorted in the Acs(s) is unity gain at all frequencies. By forcing wL equal to wsns
schematic, but have some parasitic impedance in actual board and solving for the solution, Equation 22 gives Cn value.
layout, which is why one cannot simply short them together for the L
C n = ------------------------------------------------------------ (EQ. 22)
R sum
current-sensing summing network. It is recommended to use R ntcnet  --------------
1~10Ro to create quality signals. Since Ro value is much N
-----------------------------------------  DCR
smaller than the rest of the current sensing circuit, the following R sum
R ntcnet + --------------
analysis will ignore it for simplicity. N
The summed inductor current information is presented to the

capacitor Cn. Equations 17 thru 21 describe the
23 FN7835.0
March 12, 2011

ISL95836
For example, given N = 3, Rsum = 3.65k, Rp = 11k,
Rntcs = 2.61k, Rntc = 10k, DCR = 0.9m and L = 0.36µH,
Equation 22 gives Cn = 0.397µF.
io
iL
Assuming the compensator design is correct, Figure 16 shows the
expected load transient response waveforms if Cn is correctly
selected. When the load current Icore has a square change, the
output voltage Vcore also has a square response.
Vo
If Cn value is too large or too small, VCn(s) will not accurately
represent real-time Io(s) and will worsen the transient response. RING
Figure 17 shows the load transient response when Cn is too BACK
small. Vcore will sag excessively upon load insertion and may
create a system failure. Figure 18 shows the transient response FIGURE 19. OUTPUT VOLTAGE RING BACK PROBLEM
when Cn is too large. Vcore is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs ISUM+
during this time, which may potentially hurt the CPU reliability.
io
CONFIDENTIAL
Rntcs
Cn.1
Rp Cn.2 Vcn
Rn
Rntc
Vo
Ri ISUM-
IN REVIEW
OPTIONAL
FIGURE 16. DESIRED LOAD TRANSIENT RESPONSE

Cip
WAVEFORMS Rip
OPTIONAL
io
FIGURE 20. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 19 shows the output voltage ring back problem during

load transient response. The load current io has a fast step
Vo change, but the inductor current iL cannot accurately follow.
Instead, iL responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
FIGURE 17. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO capacitors makes the output voltage Vo dip quickly upon load
SMALL current change. However, the controller regulates Vo according to
the droop current idroop, which is a real-time representation of iL;
therefore it pulls Vo back to the level dictated by iL, causing the
ring back problem. This phenomenon is not observed when the
output capacitor have very low ESR and ESL, such as all ceramic
io
capacitors.
Figure 20 shows two optional circuits for reduction of the ring
back.
Vo Cn is the capacitor used to match the inductor time constant. It
usually takes the parallel of two (or more) capacitors to get the
desired value. Figure 20 shows that two capacitors Cn.1 and Cn.2
FIGURE 18. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO are in parallel. Resistor Rn is an optional component to reduce
LARGE the Vo ring back. At steady state, Cn.1 + Cn.2 provides the desired
Cn capacitance. At the beginning of io change, the effective
capacitance is less because Rn increases the impedance of the
Cn.1 branch. As Figure 17 explains, Vo tends to dip when Cn is too
small, and this effect will reduce the Vo ring back. This effect is
more pronounced when Cn.1 is much larger than Cn.2. It is also
more pronounced when Rn is bigger. However, the presence of
Rn increases the ripple of the Vn signal if Cn.2 is too small. It is
recommended to keep Cn.2 greater than 2200pF. Rn value
24 FN7835.0
March 12, 2011

ISL95836
usually is a few ohms. Cn.1, Cn.2 and Rn values should be Overcurrent Protection
determined through tuning the load transient response
Refer to Equation 1 on page 17 and Figures 15, 19 and 21;
waveforms on an actual board.
resistor Ri sets the droop current Idroop. Tables 2 and 3 show the
Rip and Cip form an R-C branch in parallel with Ri, providing a internal OCP threshold. It is recommended to design Idroop
lower impedance path than Ri at the beginning of io change. Rip without using the Rcomp resistor.
and Cip do not have any effect at steady state. Through proper
For example, the OCP threshold is 60µA for 3-phase solution. We
selection of Rip and Cip values, idroop can resemble io rather than
will design Idroop to be 40.9µA at full load, so the OCP trip level is
iL, and Vo will not ring back. The recommended value for Rip is
1.5x of the full load current.
100. Cip should be determined through tuning the load
transient response waveforms on an actual board. The For inductor DCR sensing, Equation 26 gives the DC relationship
recommended range for Cip is 100pF~2000pF. However, it of Vcn(s) and Io(s).
should be noted that the Rip -Cip branch may distort the idroop  
waveform. Instead of being triangular as the real inductor  R ntcnet DCR
V Cn =  -----------------------------------------  ------------  I o
current, idroop may have sharp spikes, which may adversely  R sum N  (EQ. 26)
affect idroop average value detection and therefore may affect  R ntcnet + ------------- N
- 
OCP accuracy. User discretion is advised.
Substitution of Equation 26 into Equation 1 gives Equation 27:
Resistor Current-Sensing Network
CONFIDENTIAL
1 R ntcnet DCR
Phase1 Phase2 Phase3 I droop = -----  -----------------------------------------  ------------  I o (EQ. 27)
Ri R sum N
R ntcnet + --------------
N
L L L
Therefore:
R ntcnet  DCR  I o
IN REVIEW
R i = -------------------------------------------------------------------------------- (EQ. 28)
DCR DCR DCR R sum
Rsum N   R ntcnet + --------------  I droop
 N 
Rsum
Substitution of Equation 18 and application of the OCP condition
Rsum ISUM+
in Equation 28 gives Equation 29:
 R ntcs + R ntc   R p
Rsen Rsen Rsen Vcn Cn ---------------------------------------------------  DCR  I omax
Ro Ri ISUM- R ntcs + R ntc + R p
R i = ------------------------------------------------------------------------------------------------------------------------- (EQ. 29)
Ro  ntcs + R ntc   R p R sum
 R
N   --------------------------------------------------- + --------------  I droopmax
 R ntcs + R ntc + R p N 
Ro
where Iomax is the full load current, Idroopmax is the

corresponding droop current. For example, given N = 3,
Io Rsum = 3.65k, Rp = 11k, Rntcs = 2.61k, Rntc = 10k,
FIGURE 21. RESISTOR CURRENT-SENSING NETWORK DCR = 0.9m, Iomax = 94A and Idroopmax = 48µA, Equation 29
gives Ri = 487.
Figure 21 shows the resistor current-sensing network for a
2-phase solution. Each inductor has a series current-sensing For resistor sensing, Equation 30 gives the DC relationship of
resistor Rsen. Rsum and Ro are connected to the Rsen pads to Vcn(s) and Io(s).
accurately capture the inductor current information. The Rsum R sen
V Cn = ------------  I o (EQ. 30)
and Ro resistors are connected to capacitor Cn. Rsum and Cn N
form a a filter for noise attenuation. Equations 23 thru 25 give
VCn(s) expression: Substitution of Equation 30 into Equation 1 gives Equation 31:
R sen 1 R sen
(EQ. 23) I droop = -----  ------------  I o (EQ. 31)
V Cn  s  = ------------  I o  s   A Rsen  s  Ri N
N
1 Therefore:
A Rsen  s  = --------------------------- (EQ. 24)
s
1 + ---------------- R sen  I o
 Rsen R i = -------------------------- (EQ. 32)
N  I droop
1
 Rsen = --------------------------- (EQ. 25)
R sum Substitution of Equation 32 and application of the OCP condition
--------------  C n
N in Equation 28 gives Equation 33:
R sen  I omax
Transfer function ARsen(s) always has unity gain at DC. R i = ------------------------------------- (EQ. 33)
Current-sensing resistor Rsen value will not have significant N  I droopmax
variation over-temperature, so there is no need for the NTC
network. where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given N = 3,
The recommended values are Rsum = 1k and Cn = 5600pF.
25 FN7835.0
March 12, 2011

ISL95836
Rsen = 1m, Iomax = 94A and Idroopmax = 48µA, Equation 33 T2(s), that describe the entire system. Figure 23 conceptually
gives Ri = 652. shows T1(s) measurement set-up and Figure 24 conceptually
shows T2(s) measurement set-up. The VR senses the inductor
Load Line Slope current, multiplies it by a gain of the load line slope, then adds it
Refer to Figure 8. on top of the sensed output voltage and feeds it to the
compensator. T(1) is measured after the summing node, and T2(s)
For inductor DCR sensing, substitution of Equation 27 into is measured in the voltage loop before the summing node. The
Equation 2 gives the load line slope expression: spreadsheet gives both T1(s) and T2(s) plots. However, only T2(s)
V droop R droop R ntcnet DCR can be actually measured on an ISL95836 regulator.
LL = ------------------ = ------------------  -----------------------------------------  ------------ (EQ. 34)
Io Ri R sum N
R ntcnet + -------------- T1(s) is the total loop gain of the voltage loop and the droop loop.
N
It always has a higher crossover frequency than T2(s) and has
For resistor sensing, substitution of Equation 31 into Equation 2 more meaning of system stability.
gives the load line slope expression:
V droop R sen  R droop T2(s) is the voltage loop gain with closed droop loop. It has more
LL = ------------------ = ------------------------------------- (EQ. 35) meaning of output voltage response.
Io N  Ri
Design the compensator to get stable T1(s) and T2(s) with
Substitution of Equation 28 and rewriting Equation 34, or
sufficient phase margin, and output impedance equal or smaller
substitution of Equation 32 and rewriting Equation 35 give the
CONFIDENTIAL
than the load line slope.
same result in Equation 36:
Io
R droop = ----------------  LL (EQ. 36) L Vo
I droop
Q1
One can use the full load condition to calculate Rdroop. For
Vin GATE Q2 Cout io
example, given Iomax = 94A, Idroopmax = 48µA and LL = 1.9m,
IN REVIEW
DRIVER
Equation 36 gives Rdroop = 3.72k.
It is recommended to start with the Rdroop value calculated by
Equation 36, and fine tune it on the actual board to get accurate LOAD LINE SLOPE
load line slope. One should record the output voltage readings at ٛ
20
no load and at full load for load line slope calculation. Reading MOD. EA
the output voltage at lighter load instead of full load will increase COMP
VID
the measurement error. ISOLATION
TRANSFORMER
CHANNEL B
Compensator LOOP GAIN =
CHANNEL A
Figure 16 shows the desired load transient response waveforms. CHANNEL A CHANNEL B
Figure 22 shows the equivalent circuit of a voltage regulator (VR) NETWORK
ANALYZER EXCITATION OUTPUT
with the droop function. A VR is equivalent to a voltage source
(= VID) and output impedance Zout(s). If Zout(s) is equal to the FIGURE 23. LOOP GAIN T1(s) MEASUREMENT SET-UP
load line slope LL, i.e. constant output impedance, in the entire
frequency range, Vo will have square response when Io has a
L VO
square change.
Q1
Zout(s) = LL i
o
VIN GATE Q2 COUT I
O
DRIVER
VID VR V
LOAD o
LOAD LINE SLOPE
20 
MOD. EA
FIGURE 22. VOLTAGE REGULATOR EQUIVALENT CIRCUIT COMP
VID
ISOLATION
TRANSFORMER
CHANNEL B
Intersil provides a Microsoft Excel-based spreadsheet to help LOOP GAIN=
CHANNEL A
design the compensator and the current sensing network, so the CHANNEL A CHANNEL B
VR achieves constant output impedance as a stable system. NETWORK
Please go to www.intersil.com/design/ to request spreadsheet. ANALYZER EXCITATION OUTPUT
Figure 26 shows a screenshot of the spreadsheet.
FIGURE 24. LOOP GAIN T2(s) MEASUREMENT SET-UP
A VR with active droop function is a dual-loop system consisting of
a voltage loop and a droop loop which is a current loop. However,
neither loop alone is sufficient to describe the entire system. The
spreadsheet shows two loop gain transfer functions, T1(s) and
26 FN7835.0
March 12, 2011

ISL95836
Programming Resistors TABLE 8. RCOMPG PROGRAMMING TABLE
RCOMPG (k)
TABLE 7. RCOMP PROGRAMMING TABLE SWITCHING
Min. Typ. Max. FREQUENCY (kHz) VR2 ICCMAX (A)
RCOMP
(kohm) 57.14 400 70
Min. Typ. Max. VBOOT (V) VR1 ICCMAX (A) 64.76 350 70
0 3.2 0 99 72.38 350 57
5.714 0 94 80 350 45
9.224 0 80 89.52 350 33
13.33 0 70 100.952 350 24
17.143 0 60 112.381 350 18
20.952 0 53 123.81 300 18
24.762 0 48 137.14 300 24
28.571 0 43 152.38 300 33
32.381 0 38 167.62 300 45
CONFIDENTIAL
36.19 0 38 184.76 300 57
41.9 0 33 275 open 300 70
49.52 0 24 There are two programming resistors: RCOMP and RCOMPG. Table
57.14 0 18 7 shows how to select RCOMP based on VBOOT and VR1 ICCMAX
IN REVIEW
64.76 1.1 18
register settings. VR1 can power to 0V VBOOT or an internally-set
VBOOT based on RCOMP value. When the controller works with an
72.38 1.1 24 actual CPU, select RCOMP such that VR1 powers up to VBOOT =
80 1.1 33 0V as required by the SVID command. In the absence of a CPU,
89.52 1.1 38
such as testing of the VR alone, select RCOMP such that VR1
powers up to the internally-set VBOOT, which by default is 1.1V.
100.952 1.1 43 Determine the maximum current VR1 can support and set the
112.381 1.1 48 VR1 ICCMAX register value accordingly by selecting the
appropriate RCOMP value. The CPU will read the VR1 ICCMAX
123.81 1.1 53
register value and ensure that the CPU CORE current doesn’t
137.14 1.1 60 exceed the value specified by VR1 ICCMAX.
152.38 1.1 70
Table 8 shows how to select RCOMP based on VR1 and VR2 CCM
167.62 1.1 18 switching frequency and VR2 ICCMAX register settings. There are
184.76 1.1 24 four switching frequecies to choose from: 300kHz, 350kHz,
400kHz, and 450kHz. There are also six VR2 ICCMAX values to
275 open 1.1 33
choose.
TABLE 8. RCOMPG PROGRAMMING TABLE
Current Balancing
RCOMPG (k)
SWITCHING Refer to Figures 1 thru 2. The controller achieves current
Min. Typ. Max. FREQUENCY (kHz) VR2 ICCMAX (A)
balancing through matching the ISEN pin voltages. Risen and
0 3.2 450 70 Cisen form filters to remove the switching ripple of the phase
5.714 450 57 node voltages. It is recommended to use rather long RisenCisen
time constant such that the ISEN voltages have minimal ripple
9.224 450 45 and represent the DC current flowing through the inductors.
13.33 450 33 Recommended values are Rs = 10k and Cs = 0.22µF.
17.143 450 24
20.952 450 18
24.762 400 18
28.571 400 24
32.381 400 33
36.19 400 33
41.9 400 45
49.52 400 57
27 FN7835.0
March 12, 2011

ISL95836
Slew Rate Compensation Circuit For VID During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate. For example, the DAC may change a tick
Transition (5mV) per 0.5µs, controlling output voltage Vcore slew rate at
10mV/µs.
Rdroop Figure 25 shows the waveforms of VID transition. During VID
Vcore
transition, the output capacitor is being charged and discharged,
Rvid Cvid
causing Cout x dVcore/dt current on the inductor. The controller
OPTIONAL
senses the inductor current increase during the up transition, as
FB Ivid the Idroop_vid waveform shows, and will droop the output voltage
Vcore accordingly, making Vcore slew rate slow. Similar behavior
Idroop_vid
occurs during the down transition. To get the correct Vcore slew
E/A VIDs rate during VID transition, one can add the Rvid-Cvid branch,
COMP  VDACDAC VID whose current Ivid cancels Idroop_vid.
RTN It’s recommended to choose the R, C values from the reference
VSSSENSE
X1
design as a starting point. then tweak the actual values on the
VSS
INTERNAL TO board to get the best performance.
IC
CONFIDENTIAL
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The Rvid
VID - Cvid network is between the virtual ground and the real ground,
and hence has no effect on transient response.
Vfb
IN REVIEW
Ivid
Vcore
Idroop_vid
FIGURE 25. SLEW RATE COMPENSATION CIRCUIT FOR VID

TRANSITION
28 FN7835.0
March 12, 2011

ISL95836
Layout Guidelines
ISL95836
PIN NUMBER SYMBOL LAYOUT GUIDELINES
BOTTOM PAD GND Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect
to ground planes in PCB internal layers.
2 ISEN1G Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMNG, then through another capacitor (Cvsumng) to GND.
Place Cisen capacitors as close as possible to the controller and keep the following loops small:
3 ISEN2G 1. ISEN1G pin to ISEN2G pin
2. Any ISENG pin to GND
4 NTCG The NTC thermistor needs to be placed close to the thermal source that is monitored to determine AXG Vcore thermal
throttling. Recommend placing it at the hottest spot of the AXG Vcore VR.
5, 6, 7 SCLK, Follow Intel recommendation.

ALERT#, SDA
8 VR_HOT# No special consideration.
CONFIDENTIAL
9 VR_ON No special consideration.
10 NTC The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU Vcore thermal
throttling. Recommend placing it at the hottest spot of the CPU Vcore VR.
10 PGOOD
IN REVIEW
9 NC No special consideration.
10 VR_HOT# No special consideration.
11 ISEN3 Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place
Cisen capacitors as close as possible to the controller and keep the following loops small:
12 ISEN2 1. Any ISEN pin to another ISEN pin
2. Any ISEN pin to GND
13 ISEN1
The red traces in the following drawing show the loops that need to minimized.
Phase1 L3
Risen Ro
ISEN3
Cisen Vo
Phase2 L2
Risen Ro
ISEN2
Cisen
Phase3 L1
Risen Ro
ISEN1
GND Vsumn
Cisen Cvsumn
29 FN7835.0
March 12, 2011

ISL95836
Layout Guidelines (Continued)
ISL95836
14 ISUMP Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
15 ISUMN Place the NTC thermistor next to VR1 phase-1 inductor (L1) so it senses the inductor temperature correctly.
Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces
in parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. Route R63 and R71 to VR1
phase-1 side pad of inductor L1. Route R88 to the output side pad of inductor L1. Route R65 and R72 to VR1 phase-2
side pad of inductor L2. Route R90 to the output side pad of inductor L2. If possible, route the traces on a different layer
from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is allowed on the pad,
consider routing the traces into the pads from the inside of the inductor. The following drawings show the two preferred
ways of routing current sensing traces.
Inductor Inductor
CONFIDENTIAL Vias
IN REVIEW
Current-Sensing Current-Sensing
Traces Traces
16 RTN Place the RTN filter in close proximity of the controller for good decoupling.
17 FB Place the compensator components in general proximity of the controller.
18 COMP
19 PGOOD No special consideration.
20 BOOT1 Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
21 UGATE1 Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1 trace to VR1 phase-1 high-side MOSFET (Q2 and Q8) source
22 PHASE1 pins instead of general copper.
23 LGATE1 Place the RTNG filter in close proximity of the controller for good decoupling.
24 PWM3 No special consideration.
25 VDD A capacitor decouples it to GND. Place it in close proximity of the controller.
26 VCCP A capacitor decouples it to GND. Place it in close proximity of the controller.
27 LGATE2 If available, run VSSP2 trace in parallel with LGATE2 trace. Use decent width (>30mil). Avoid any sensitive analog signal
trace from crossing over or getting close.
28 PHASE2 Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE2 trace to VR1 phase-2 high-side MOSFET (Q4 and Q10)
29 UGATE2 source pins instead of general copper.
30 BOOT2 Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
31 BOOT1G Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
32 UGATE1G Run these two traces in parallel fashion with decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE1G trace to VR2 phase-1 high-side MOSFET source pins
33 PHASE1G instead of general copper
34 LGATE1G Use decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
35 PWM2G No special consideration.
36 PGOODG No special consideration.
30 FN7835.0
March 12, 2011

ISL95836
Layout Guidelines (Continued)
ISL95836
37 COMPG Place the compensator components in general proximity of the controller.
38 FBG
39 RTNG Place the RTNG filter in close proximity of the controller for good decoupling.
40 ISUMNG Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
1 ISUMPG Place the NTC thermistor next to VR2 phase-1 inductor (L1) so it senses the inductor temperature correctly.
See ISUMN and ISUMP pins for layout guidelines of current-sensing trace routing.
CONFIDENTIAL
IN REVIEW
31 FN7835.0
March 12, 2011

ISL95836
Package Outline Drawing
L40.5x5
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/07
4X 3.60
5.00 A
B 36X 0.40
6 6
PIN 1 PIN #1 INDEX AREA
INDEX AREA
5.00
3.50
(4X) 0.15
CONFIDENTIALTOP VIEW
40X 0.4
±0 .1 b
0.20
0.10 M C A B
IN REVIEW
BOTTOM VIEW
PACKAGE OUTLINE
0.40
0.750 SEE DETAIL “X”
// 0.10 C
C
BASE PLANE
0.050 SEATING PLANE
0.08 C
SIDE VIEW
3.50
5.00
(36X 0..40)
0.2 REF
5
C
0.00 MIN
0.05 MAX
(40X 0.20)
(40X 0.60)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN

NOTES:
1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.27mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
32 FN7835.0
March 12, 2011

ISL95836
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
March 12, 2011 FN7835.0 Preliminary.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL95836
CONFIDENTIAL
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
IN REVIEW
For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
33 FN7835.0
March 12, 2011

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PRELIMINARY

3+2 Voltage Regulator for IMVP-7/VR12™ CPUs

Load Line Regulation

ISL95836HRTZ 95836 HRTZ -10 to +100 40 Ld 5x5 TQFN L40.5x5

ISL95836IRTZ 95836 IRTZ -40 to +100 40 Ld 5x5 TQFN L40.5x5

2 ISEN1G Individual current sensing for VR2 Phase 1.

5, 6, 7 SCLK, Communication bus between the CPU and the VRs.

13 ISEN1 Individual current sensing for VR1 Phase 1.

Free Datasheet http://www.0PDF.com

14, 15 ISUMP and VR1 droop current sense input.

16 RTN VR1 remote voltage sensing return.

25 VDD 5V bias power.

35 PWM2G PWM output for VR2 Phase 2.

Free Datasheet http://www.0PDF.com

39 RTNG VR2 remote voltage sensing return.

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ISEN3/FB2 DRIVER LGATE1

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FIGURE 1. TYPICAL ISL95836 APPLICATION CIRCUIT USING INDUCTOR DCR SENSING

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SLAVE CIRCUIT 2 Clock3

SLAVE CIRCUIT 3 Vcrs2 Vcrs3 Vcrs1

FIGURE 2. R3™ MODULATOR CIRCUIT

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Clock2 Figure 4 shows the operation principles during load insertion

The ISL95836 uses Intersil patented R3™ (Robust Ripple

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VR_ON SLEW RATE 0 0 0 1 1 0 0 1 1 9 0.37000

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7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)

7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)

7 6 5 4 3 2 1 0 Hex VO (V) 7 6 5 4 3 2 1 0 Hex VO (V)

VCC SENSE + V = V DAC + VSS SENSE (EQ. 3)

Figure 8 shows the load line implementation. The controller

V droop = R droop  I droop (EQ. 2)

Vdroop is the droop voltage required to implement load line.

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R dcr1  I L1 = R dcr2  I L2 = R dcr3  I L3 (EQ. 16)

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VR1 can be configured for 3, 2 or 1-phase operation. Table 2

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2 1-phase DE VR_HOT#/ALERT# Behavior

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11h Status_2 Data register showing status_2 00h

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The summed inductor current information is presented to the

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FIGURE 16. DESIRED LOAD TRANSIENT RESPONSE

Figure 19 shows the output voltage ring back problem during

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where Iomax is the full load current, Idroopmax is the

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