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ADC - 1p5 - Bits - Per - Stage: From Import Def

This Python code defines a function called ADC_1p5_bits_per_Stage that simulates an analog-to-digital converter (ADC) with 1.5 bits per stage. The function takes in inputs like the analog input voltage, resolution, supply voltages, and error matrix and returns the analog and digital outputs after putting the input through multiple 1.5 bit stages based on the resolution. It also includes test code that calls the function with sample inputs to test it.

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Surya Padma
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36 views1 page

ADC - 1p5 - Bits - Per - Stage: From Import Def

This Python code defines a function called ADC_1p5_bits_per_Stage that simulates an analog-to-digital converter (ADC) with 1.5 bits per stage. The function takes in inputs like the analog input voltage, resolution, supply voltages, and error matrix and returns the analog and digital outputs after putting the input through multiple 1.5 bit stages based on the resolution. It also includes test code that calls the function with sample inputs to test it.

Uploaded by

Surya Padma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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1 # -*- coding: utf-8 -*-

2 """
3 Created on Sun Feb 11 00:05:55 2018
4
5 @author: lenovo
6 """
7 from MX1P5_STAGE import MX1p5_stage
8 def ADC_1p5_bits_per_Stage(AN_IN, RESOLUTION, VDD, VSS, Margin, Error_Matrix):
9 V_HI = Margin*VDD
10 V_LO = Margin*VSS
11 V_FS = V_HI - V_LO
12 ANA_OUT = []
13 DIG_OUT = []
14 ana_out, dig_out = MX1p5_stage(AN_IN, Error_Matrix[0], VDD, VSS, Margin)
15 ANA_OUT.append(ana_out)
16 DIG_OUT.append(dig_out)
17 for stage in range(1, RESOLUTION):
18 ana_out, dig_out = MX1p5_stage(ana_out, Error_Matrix[stage], VDD, VSS, Margin)
19 ANA_OUT.append(ana_out)
20 DIG_OUT.append(dig_out)
21
22 return ANA_OUT, DIG_OUT
23
24 # ANA_OUT, DIG_OUT = ADC_1p5_bits_per_Stage(AN_IN, RESOLUTION, VDD, VSS, Margin,
Error_Matrix)
25 #TESTBENCH
26
27 #VDD = 1.0
28 #VSS = -1.0
29 #Margin = 1.0
30 #V_HI = VDD*Margin
31 #V_LO = VSS*Margin
32 #Resolution = 4
33 #Vin_ana = 0.2
34 #Error_Matrix = [[0.00, 0.000, 0.000, 0.000], #MX1p5_1
35 # [0.00, 0.000, 0.000, 0.000], #MX1p5_2
36 # [0.00, 0.000, 0.000, 0.000], #MX1p5_3
37 # [0.00, 0.000, 0.000, 0.000], #MX1p5_4
38 # [0.00, 0.000, 0.000, 0.000], #MX1p5_5
39 # [0.00, 0.000, 0.000, 0.000], #MX1p5_6
40 # [0.00, 0.000, 0.000, 0.000], #MX1p5_7
41 # [0.00, 0.000, 0.000, 0.000], #MX1p5_8
42 # [0.00, 0.000, 0.000, 0.000], #MX1p5_9
43 # [0.00, 0.000, 0.000, 0.000], #MX1p5_10
44 # [0.00, 0.000, 0.000, 0.000], #MX1p5_11
45 # [0.00, 0.000, 0.000, 0.000], #MX1p5_12
46 # [0.00, 0.000, 0.000, 0.000], #MX1p5_13
47 # [0.01, 0.000, 0.000, 0.000], #MX1p5_14
48 # [0.01, 0.000, 0.000, 0.000] #MX1p5_15
49 # ]
50 #Ana_Out, Dig_Out = ADC_1p5_bits_per_Stage(Vin_ana, Resolution, VDD, VSS,
Margin, Error_Matrix)
51 #
52 #del Error_Matrix
53 #del VDD
54 #del VSS
55 #del Margin
56 #del V_HI
57 #del V_LO
58 #del Resolution
59 #del Vin_ana

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