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Cadence Tutorial PDF

This document provides an outline for using Cadence tools to simulate Verilog code. It discusses: 1. Setting up the working environment, including editing configuration files and creating directories for code. 2. Writing Verilog code, compiling it to check for errors, and elaborating the design to construct the design hierarchy. 3. Creating a test bench, loading the snapshot into the simulator, and running the simulation.

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0% found this document useful (0 votes)
290 views9 pages

Cadence Tutorial PDF

This document provides an outline for using Cadence tools to simulate Verilog code. It discusses: 1. Setting up the working environment, including editing configuration files and creating directories for code. 2. Writing Verilog code, compiling it to check for errors, and elaborating the design to construct the design hierarchy. 3. Creating a test bench, loading the snapshot into the simulator, and running the simulation.

Uploaded by

erdvk
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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10/14/2008

Outline
• Introduction
Cadence Verilog Simulation • Setting up your Working Environment
Guide and Tutorial • Compilation
• Elaboration
ECE 4680: Computer Organization • Simulation
• Examples
• LAB Exercises

1
10/14/2008

Introduction Setting up your Working Environment

• This guide describes, via a tutorial, how use  • Login to your Linux machine.
– Use your WSU access ID and password.
Cadence Tools to work with Verilog
Cadence Tools to work with Verilog. • Double click on the “ab1234's Home” folder on your desktop.
– (“ab1234” should be your AccessID).
• Cadence tools can be accessed from Eng 2360   • Click “View” and check “Show Hidden Files”. 
LAB. • Scroll down to find the .cshrc file. 
– The file is currently Read Only. 
• This guide is presented in three sections: – Right click on the file and choose “Properties”. 
1. How to set up your environment to view the documents  – Go to the “Permissions” tag and check “Owner >Write”.
and run the simulator tools
and run the simulator tools. – Click “Close”
Click “Close”. 
2. Executing the Verilog simulator. – Now the file can be edited.
• Right click on the file and choose “Open with Text Editor”. 
3. How to visualize the simulation results. – This will open the .cshrc file in the text editor. 

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10/14/2008

Setting up your Working Environment (cont…) Setting up your Working Environment (cont…)


• If you can find the following line  • Create new directory, name it cadence, under you 
“source /usr/local/etc/ALLSET” home directory.
home directory.
comment out  it by puting # sign in front of it. – mkdir cadence  
– like this: # source /usr/local/etc/ALLSET 
• Add these two lines to the file:  • Create vhdl directory under cadence directory. 
– source /opt/cds/class/cds_setup – mkdir vhdl
– source /opt/cds/class/setup_files/vhdl/.vhdl_setup • Execute the following commands:
• Save and close the editor. – cd vhdl
• Open a new terminal (by right click on the desktop and choose “Open  – cp $NCVHDL/cds.lib $CDSVHDL 
Terminal”) and type the commands:
– cp $NCVHDL/hdl.var $CDSVHDL
– cd $HOME
– source .cshrc
• Now your environment is ready.

3
10/14/2008

Writing Verilog Code  Compiling Verilog Code 
• You should start by setting up directories for your new  • On a terminal, type the following commands
code.
– cd $CDSVHDL  – cd $HOME/cadence/vhdl 
– mkdir alu
– cd alu – nclaunch &  
– mkdir src
• Open a text editor.  • The nclaunch command opens the NCLaunch
– ( Applicatins Æ accessories Æ text editor)

• Go to (http://www.ece.eng.wayne.edu/~nabil/ece4680/labs/lab2_alu.v)
main window. 
• Copy the code from the page and paste it in the text editor 
Copy the code from the page and paste it in the text editor
window.
• Change the module name in the code as required.
• Save the file in the src directory with the name 
– <your last name>_alu.v

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10/14/2008

Compiling Verilog Code (cont …) Compiling Verilog Code (cont …)
Menu Bar • Select your Verilog source file from File Browser
Toolbar Icons
area.
area
– If you can not see it, brows for it.
File Browser
Design Area 
• Choose Verilog compiler from Tools main menu.
– The Compile form appears.
– Press OK. (without changing any thing).
• The
The results of the compilation appear in the 
results of the compilation appear in the
Console Window.
Consol Window – If you have errors, read them from the consol window 
and fix them in the source file using a text editor.
NCLaunch Main Window

5
10/14/2008

Compiling Verilog Code (cont …) Elaborating the Design 
• The elaboration process constructs a design hierarchy 
based on the instantiation and configuration information in 
the design, establishes signal connectivity, and computes 
h d i bli h i l i i d
initial values for all objects in the design.
Compiled design  – Make the compiled unit ready to use in the simulation
unit • Click the plus sign to the left of the worklib library (vhdl) in 
the Library Browser to expand it.
• Select the top‐level design unit.  
• Choose Elaborator
Choose Elaborator from the Tools menu.
from the Tools menu.
• Press OK. (without changing any thing).
• This design hierarchy is stored in a simulation snapshot. 
• The snapshot is the representation of your design that the 
simulator uses to run the simulation. 

6
10/14/2008

Creating the test bench design  Simulation with NcSim
• Open a text editor.  • Load the Snapshot into the Simulator.
• Go to 
Go to – In the Design Area, in the snapshot folder, select 
(http://www.ece.eng.wayne.edu/~nabil/ece4680/labs/lab2_alu_tb.v)
the test bench component.
• Copy the code from the page and paste it in 
the text editor window. – Choose Simulator from Tools Menu.
• Change the module name in the code as  – Press OK
required.
• Save the file in the src directory with the name 
– <your last name>_alu_tb.v
• Compile and elaborate the new code.

7
10/14/2008

Simulation with NcSim (cont …) Simulation with NcSim (cont …)
• To view signals in SignalScan Waveform 
Viewer:
Vi
Your design Waveform viewer
– Select your design from the Design Browser.
– Choose Signals from the Select menu.
Signals
Design Browser – Click on the button      in the upper right corner.

8
10/14/2008

Simulation with NcSim (cont …) Simulation with NcSim (cont …)
• Click on the button on the new window to start 
simulation. 
simulation

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