8155/ 8156 multipurpose programmable devices

 8155 is designed to be compatible with 8085 microprocessor.

 8155 includes 256 bytes of RAM memory, three IO ports and a timer. The 8156 is
identical with 8155 except that the 8156 requires active high Chip Enable.
 8155 has two sections. One is read write memory and another one includes three
programmable I/O ports (PA, PB, PC) along with a timer. All the ports can be
configured as simple input or output ports.
 The IO ports PA and PB are 8-bit and can be programmed in handshake mode. In
handshake mode, each port uses three handshake signals. Some of port PC (6-bit)
pins are used for handshake signals.
 The timer has 14-bit counter. It has four operating modes.
 There are total five control signals in 8155. CE: Chip Enable is a master chip select
signal connected to the decoded higher order bus. The ALE, IO/M, RD & WR signals
from 8085 microprocessor can be directly connected to the device. The control logic
of 8155 is specifically designed to eliminate the need for demultiplexing of AD0-AD7.
 The ports and the timer of 8155 are IO mapped in the system. Hence an 3-bit
address is used to select the internal devices. The remaining address lines are
decoded to produce chip select signal.

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Table: internal address of 8155

Internal device Internal address

A2 A1 A0
Control register/ 0 0 0
status register
Port-A 0 0 1
Port- B 0 1 0
Port- C 0 1 1
LSB timer 1 0 0
MSB timer 1 0 1

CONTROL REGISTER
Control register also called command register.
It is a 8-bit which defines different functions.
It defines the function of different ports such as input, output or handshaking mode.
It also defines timer command for timer to start and stop.

Control Word Format:

D7 D6 D5 D4 D3 D2 D1 D0
PC - ALT1 (00) and
Timer command IEB IEA PB PA
ALT2 (11)
Input or output for PA and PB respectively:
1-output; 0-input

Interrupt Enable for PA and PB(D4 and D5):

1- enable; 0- disable

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Timer command:
00 -No effect
01 -Stop counting if timer is running. No operation if counter is not running.
10 -Stop after terminal counter is reached.
11 -Start timer if timer is not running. If timer is running reload the TC and then continue.

8155 timer

The 8155 timer consists of two 8-bit registers.

1. 8-bit LSB and 8-bit MSB.
2. In these 16 bits, 14 bits are used for counter and two bit for mode selection.
3. The counter is a 14 bit down counter. It can operate in 4 different modes of operation.

Timer MSB:
M2 M1 T13 T12 T11 T10 T9 T8
Timer LSB:
T7 T6 T5 T4 T3 T2 T1 T0

We can select mode using two bits M2 and M1.

M2 M1
00(Mode 0)- Single Square Wave
01(Mode 1)- Square Wave
10(Mode 2)- Single Pulse on TC(terminal count)
11(Mode 3)- Pulse every TC

Mode 0: In this mode, timer gives only one cycle of square wave, the output remains high
for 1/2 count and remain s low for 1/2 count. If count is odd it remains high for (n+1)/2 and
low for (n-1)/2. Where n is count value. Wave width depends on two factor: one is Input clock
pulse frequency, and the other is count loaded in counter.
Mode 1: This mode is similar to single square wave in operation but the when counter
becomes zero, the count value is automatically reloaded. Thus it provides continuous square
wave.

Mode 2: This mode gives a single clock pulse as a output of the end of the count. The
output is high normally, but it becomes low for 1 clock pulse and again it will become high
and remain high.

Mode 3: This mode is similar to mode 2 but when the counter becomes zero the count value
is automatically reloaded. Thus it provides continuous pulses.

8155 has a status register which can be read by processor by using the control register
address. They both have same port address and they can be differentiated by only RD &
WR signals. The processor can only write to control register and it can only read the status
register.

8155 Handshake Input port

When a port is programmed as a handshake input port then handshake signals are used to
transfer the data from input device to the port. When the port receives a data, it interrupts the

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processor for executing a subroutine for reading the data from the port and storing in
appropriate place. Alternately, the processor can check the status register of 8155 to know
any data is available on the port, if a data is available on the port then the processor
executes a subroutine to read the data and store it in appropriate place.

ALE PC2 STBA

IO/M BFA Input
PC1
8085 RD device
RST 7.5 INTRA PC
0
AD0-AD7

Port-A as handshake input port

8155 Handshake Input port

When a port is programmed as a handshake output port then handshake signals are used to
transfer the data from port to the output device. The processor first loads a data to the port.
When the data is accepted by the output device the port will send an interrupt signal to the
processor. Now the processor can load the next data to the port. Alternatively the processor
can check the status register before loading the next data.

Port-A as handshake output port

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8355
 The INTEL 8755 is an EPROM and IO chip.
 It can be used in 8085A and 8088 microprocessor.
 The ROM portion has 2kbyte memory with word size of 8-bit.
 It has maximum access time of 400 ns so that the device can be used without wait
states in 8085A CPU.
 The 8355-2 has 300ns access time for compatibility with the 8085A-2 and full speed
5 MHz 8088 microprocessor.

It is a 40 pin IC available in DIP. It has multiplexed address and data lines. It has an
internal address latch to demultiplex the address and data lines using the signal ALE.
The IO portion consists of two general purpose IO ports each with 8 port lines.
8755
 The INTEL 8755 is an EPROM and IO chip.
 It can be used in 8085A and 8088 microprocessor.
 It has 2kbyte memory with word size of 8-bit.
 It has maximum access time of 450 ns so that the device can be used without wait
states in 8085A CPU.

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 internal block diagram of 8755
The ports are programmed as input or output port by loading an 8-bit word in the Data
Direction Register of the connected port. Each line of the port can be individually used as
input or output lines. A zero loaded in the DDR makes the corresponding line of the port as
input line of the port.
The ports and data direction registers are selected by two bit internal address A0, A1. when
A1 A0 = 00 port A, 01 port B, 10 DDRA, 11 DDRB
When the device is reset by applying a high signal at RESET pin, the DDRs are cleared and
the ports are initialized in the input mode.

8255 PPI (PROGRAMMABLE PERIPHERAL INTERFACE):

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Features of 8255 PPI:

1. It is a programmable parallel I/O Device.

2. It contains 24 programmable I/O pins.
3. The 24 pins are classified as three 8-bit bi-directional I/O ports.
4. Three 8-bit bi-directional I/O ports are PORT A, PORT B and PORT C.
5. TTL compatible.
6. Direct bit set reset capability is available for port C.
7. It operates in two modes
i. BSR MODE.
ii. I/O MODE.
8. I/O Mode is classified in three different modes
i. MODEO: Simple I/O Mode.
ii. MODE1: Handshake or Strobbed I/O Mode.
iii. MODE2: Bi-directional I/O Mode.

INTERNAL ARCHITECTURE OR BLOCK DIAGRAM OF 8255:

Data Bus Buffer:

This three-state bi-directional 8-bit buffer (D0 to D7) is used to interface the
8255 to the system data bus. Data is transmitted or received by the buffer
upon execution of input or output instructions by the microprocessor. The
direction of data bus is decided by read and writes control signals. Control
words and status information are also transferred through the data bus buffer.
The architecture of 8255 is given as below

Read/Write and Control Logic:

The function of this block is to manage all of the internal and external
transfers of both Data and Control or Status words. It accepts inputs from the
CPU Address and Control busses and in turn, issues commands to both of
the Control Groups.

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(Chip Select):

A “low” on this input pin enables the communication between the 8255 and
the microprocessor.

(Read):

A “low” on this input pin enables 8255 to send the data or status information to
the microprocessor on the data bus. In essence, it allows the microprocessor
to “read from” the 8255. The pin diagram of 8255 is as shown below.

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9
 (Write):

A “low” on this input pin enables the microprocessor to write data or control
words into the 8255.

(A0 and A1):

Port Select 0 and Port Select 1. The selection of one of the three ports of the
control word register. They are normally connected to the least significant bits
of the address bus (A0 and A1).

A1 A0 Operation
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Word Register

RESET

A “high” on this reset the 8255 operation. All ports (A, B, C) are set to the
input mode. “Bus hold” devices internal to the 82C55A will hold the I/O port
inputs to a logic “1” state with a maximum hold current of 400mA

Group A and Group B Controls:

The control word contains information such as “mode”, “bit set”, “bit reset”,
etc., that initializes the functional configuration of the 82C55A. Each of the
Control blocks (Group A and Group B) accepts “commands” from the
Read/Write Control logic, receives “control words” from the internal data bus
and issues the proper commands to its associated ports.
 Control Group A - Port A and Port C upper (PC7 - PC4)
 Control Group B - Port B and Port C lower (PC3 -PC0)
The control word register can be both written and read as shown in the “Basic
Operation” table. Figure 4 shows the control word format for both Read and
Write operations. When the control word is read, bit D7 will always be logic

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“1”, as this implies control word mode information.

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Operating Modes

Mode 0 (Basic Input/output mode):

This functional configuration provides simple input and output operations for
each of the three ports. No handshaking is required, data is simply written to
or read from a specific port.
Mode 0 Basic Functional Definitions:
1. Two 8-bit ports and two 4-bit ports
2. Any Port can be input or output
3. Outputs are latched
4. Input are not latched
5. 16 different Input/output configurations possible

Mode 0 Configurations

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13
Mode 1 - (Strobbed Input/output mode or Handshake Input/output mode):

This functional configuration provides a means for transferring I/O data to or

from a specified port in conjunction with strobes or “hand shaking” signals. In
mode 1, port A and port B use the lines on port C to generate or accept these
“hand shaking” signals.

Mode 1 Basic Function Definitions:

1. Two Groups (Group A and Group B).

2. Each group contains one 8-bit port and one 4-bit control/data port
3. The 8-bit data port can be either input or output.
4. Both inputs and outputs are latched.
5. The 4-bit port is used for control and status of the 8-bit port.

Input Control Signal Definition

(Strobe Input):
A “low” on this input loads data into the input latch.

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IBF (Input Buffer Full F/F):
A “high” on this output indicates that the data has been loaded into the input
latch: in essence, and acknowledgment. IBF is set by STB input being low
and is reset by the rising edge of the read input.

INTR (Interrupt Request)

A “high” on this output can be used to interrupt the CPU when and input
device is requesting service. INTR is set by the condition: STB is a “one”, IBF
is a “one” and INTE is a “one”. It is reset by the falling edge of RD. This
procedure allows an input device to request service from the CPU by simply
strobing its data into the port.
INTE A
It is controlled by bit set/reset of PC4.

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 INTE B
It is controlled by bit set/reset of PC2.

Output Control Signal Definition:

OBF (Output Buffer Full F/F):

The OBF output will go “low” to indicate that the CPU has written data out to
be specified port. This does not mean valid data is sent out of the part at this
time since OBF can go true before data is available. Data is guaranteed valid
at the rising edge of OBF. The OBF F/F will be set by the rising edge of the
WR input and reset by ACK input being low.
(Acknowledge Input).
A “low” on this input informs the 82C55A that the data from Port A or Port B is
ready to be accepted. In essence, a response from the peripheral device
indicating that it is ready to accept data.
INTR (Interrupt Request):
A “high” on this output can be used to interrupt the CPU when an output
device has accepted data transmitted by the CPU. INTR is set when ACK is a
“one”, OBF is a “one” and INTE is a “one”. It is reset by the falling edge of
WR.
INTE A
It is controlled by Bit Set/Reset of PC6.

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INTE B
It is controlled by Bit Set/Reset of PC2.
NOTE:
To strobe data into the peripheral device, the user must operate the strobe
line in a hand shaking mode. The user needs to send OBF to the peripheral
device generates an ACK from the peripheral device and then latch data into
the peripheral device on the rising edge of OBF.

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Mode 2 (Strobbed Bi-Directional I/O Mode):

The functional configuration provides a means for communicating with a

peripheral device or structure on a single 8-bit bus for both transmitting and
receiving data (bi-directional bus I/O). “Hand shaking” signals are provided to
maintain proper bus flow discipline similar to Mode 1. Interrupt generation and
enable/disable functions are also available.
Mode 2 Basic Functional Definitions:
1. Used in Group A only
2. One 8-bit, bi-directional bus Port (Port A) and a 5-bit control Port (Port
C)
3. Both inputs and outputs are latched
4. The 5-bit control port (Port C) is used for control and status for the 8-
bit, bi-directional bus port (Port A)

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 INTR (Interrupt Request):
A high on this output can be used to interrupt the CPU for both input or output
operations.

Output Operations

OBF (Output Buffer Full):

The OBF output will go “low” to indicate that the CPU has written data out to
port A.
(Acknowledge Input).
A “low” on this input enables the three-state output buffer of port A to send
out the data. Otherwise, the output buffer will be in the high impedance state.
INTE 1 (The INTE flip-flop associated with OBF):
It is controlled by bit set/reset of PC4.

Input Operations
STB (Strobe Input):
A “low” on this input loads data into the input latch.
IBF (Input Buffer Full F/F):
A “high” on this output indicates that data has been loaded into the input
latch.
INTE 2 (The INTE flip-flop associated with IBF):
It is controlled by bit set/reset of PC4.

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20
STATUS WORD OF 8255:

Applications of the 82C55A

The 82C55A is a very powerful tool for interfacing peripheral equipment to the
microcomputer system. It represents the optimum use of available pins and is
flexible enough to interface almost any I/O device without the need for
additional external logic.
Each peripheral device in a microcomputer system usually has a “service
routine” associated with it. The routine manages the software interface
between the device and the CPU. The functional definition of the 82C55A is
programmed by the I/O service routine and becomes an extension of the
system software. By examining the I/O devices interface characteristics for
both data transfer and timing, and matching this information to the examples
and tables in the detailed operational description, a control word can easily be
developed to initialize the 82C55A to exactly “fit” the application.

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 8253/8254 PIT (PROGRAMMABLE INTERVAL TIMER)

Features of 8253 /8254 PIT:

1. Three independent 16-bit counter/ timer.

2. Six programmable counter modes.
3. Counting facility in both binary and BCD number systems.
4. Compatible with 8085 and 8086 microprocessor.
5. Single + 5 V Power Supply.
6. 24 pin DIP (Dual in Line Package).
7. For 8253 operating frequency range -- DC to 2 MHz
8. For 8254 operating frequency range -- DC to 8 MHz
9. For 8254(2) operating frequency range -- DC to 10 MHz

BLOCK DIAGRAM OF 8254:

DATA BUS BUFFER: This tri-state, bi-directional, 8-bit buffer is used to

interface the 8254 to the system bus, see the figure : Block Diagram Showing
Data Bus Buffer and Read/Write Logic Functions.

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READ/WRITE LOGIC : The Read/Write Logic accepts inputs from the system bus and
generates control signals for the other functional blocks of the 8254. A ``low'' on the RD
input tells the 8254 that the CPU is reading one of the counters. A ``low'' on the WR input
tells the 8254 that the CPU is writing either a Control Word or an initial count. Both RD and
WR are qualified by CS; RD and WR are ignored unless the 8254 has been selected by
holding CS low. A1 and A0 select one of the three counters or the Control Word Register to
be read from/written into.
A1 A0 selection
0 0 counter 0
0 1 counter 1
1 0 counter 2
1 1 control register

Control word register

This register is accessed when lineA0 and A1 are at logic 1. It is used to write a command
word which specifies the counter to be used, its mode, and either a read or a write operation.

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

modes M2 M1 M0
Mode 0 0 0 0
SC1 SC0
Mode1 0 0 1 Select counter 0 0 0
Mode2 X 1 0 Select counter 1 0 1
Mode3 X 1 1
Select counter 2 1 0
Mode4 1 0 0 Read back 1 1
Mode5 1 0 1 command

RW 1 RW 0
Counter latch command 0 0
Rd/ wr least significant byte only 0 1
Rd/ wr most significant byte only 1 0
Rd/ wr least significant byte then 1 1
most significant byte

Binary counter 16 bit 0

Binary coded decimal counter 1

Mode:
The 8254 has 6 different modes, the gate of a counter is used either to enable or disable
counting.
In mode 0, after the count is written and if the gate is high, the count is decremented every
clock cycle. When the count reaches zero, the output goes high and remains high until a
new count or mode word is loaded.
In mode 1, the out is initially high. When the gate is triggered, the out goes low and at the
end of the count, the out goes high again.

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Mode 2 is used to generate a pulse equal to the clock period at a given interval. When the
counter is loaded, the out stays high until the count reaches 1 and then the out goes low for
one clock cycle period. The count is reloaded automatically, and the pulse is generated
continuously.
In mode 3, when count is loaded, the out is high. The count is decremented by 2 in every
clock cycle and when it reaches 0, the out goes low and the count is reloaded again. So a
continuous square wave is generated with period equal to the period of the count.
Mode 4 is software triggered strobe. Here, out is initially high; it goes low for one clock
period at the end of the count. The count must be reloaded for subsequent output.
Mode 5 is similar to mode 4 except that it is triggered by the rising pulse at the gate. Initially
the out is low and when the gate pulse is triggered from low to high, the count begins. At the
end of the count OUT goes low for one clock period.
Read back commend allows the user to read the count and status of the counter. This
command is not available in 8253.
READ BACK COMMAND FORMAT

D7 D6 D5 D4 D3 D2 D1 D0
1 1 COUNT STATUS CNT 2 CNT1 CNT0 0

STATUS BYTE

D7 D6 D5 D4 D3 D2 D1 D0
NULL
OUTPUT RW1 RW0 M2 M1 M0 BCD
COUNT

USART- INTEL 8251A

The 8251A is a programmable serial communication interface chip designed for
synchronous and asynchronous serial data communication. It is packed in a 28 pin DIP. The
8251A is the enhanced version of its predecessor, 8251. When information is to be sent by
8085 over long distances, it is economical to send it on a single line. The 8251A converts the
parallel data received from microprocessor on the D 7-0 data pins into serial data and
transmit it on TxD output pin of 8251. Similarly it converts the serial data received on RxD
input into parallel data, and the processor reads it using the data pins D7-0.

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READ/ WRITE CONTROL LOGIC
The read/ write control logic interfaces the 8251 with CPU, determines the functions of the
8251 according to the control word written into its control register and monitors the data flow.
This section has three registers and they are control register, status register and data buffer.
The read, write and chip select signals are used to read/ write operations with these
registers. When signal is high, the control register is selected for writing control word or
reading status word. When signal is low the data buffer is selected for read/write
operation. A high on reset input forces 8251 into idle mode. The clock input is necessary fro
communication with CPU and the clock does not control either serial transmission or the
reception rate.

TRANSMITTER SECTION
The transmitter section accepts parallel data from CPU and converts them into serial data.
This section is double buffered i.e. it has a buffer register to hold an 8-bit parallel data and
another register called output register to convert the previous data into a stream of serial
bits.

25
The processor loads a data into the buffer register. When output register is empty, the data
is transferred from buffer to output register. Now the processor can again load another data
in buffer register. If the buffer register is empty, then TxRDY is asserted high and if output
register is empty the TxEMPTY is asserted high. These signals can also be used as interrupt
or status for data transmission.

The clock signal controls the rate at which the bits are transmitted by the USART. The
clock frequency can be 1, 16 or 64 times the baud rate.

RECEIVER SECTION
The receiver section accepts serial data and converts them into parallel data. The receiver
section is double buffered.
Normally RxD line is high, when the RxD line goes low, the control logic assumes it as a
START bit, waits for half a bit time and samples the line again. If the line is still low, then the
input register accepts the following bits, forms character and loads it into the buffer register.
The CPU reads the parallel data from buffer register. When the input register loads a parallel
data to buffer register, the RxRDY line goes high. The signal can be used as an interrupt or

status to indicate the readiness of the receiver section to CPU. The clock signal
controls the rate at which bits are received by the USART. In the asynchronous mode, the
clock frequency can be set to 1, 16, 64 times the baud rate.
During asynchronous mode, the signal SYNDET/BRKDET will indicate the intentional break
in data transmission. If the RxD line remains low for more than 2 character time then this
signal is asserted high to indicate the break in the transmission.
During synchronous mode, the signal SYNDET/BRKDET will indicate reception of
synchronous character. If the 8251 finds a synchronous character in the incoming string of
data bits then it asserts SYNDET signal as high.

MODEM CONTROL
The modem control unit allows to interface a MODEM to 8251 and to establish data
communication through MODEM over telephone lines. This unit takes care of handshake
signals for MODEM interface.
The 8251 is programmed by sending mode word and command word. First reset the 8251
and then send a mode word to control register address. Next, the command word is sent to
the same address. The CPU can check the readiness of the 8251 for data transfer by
reading the status register. The format of status and control register are shown.

26
Interfacing of 8251 with 8085
A simple schematic for interfacing the 8251 with 8085 is shown. The 8251 can either be
memory mapped or IO mapped in the system. In the schematic the 8251 is IO mapped in the
system. The chip select signal for IO mapped devices are generated by using a 3-to-8
decoder. The address lines A4, A5, A6 are decoded to generate eight chip select signals and
in this, the signal IOCS 2 is used to select 8251. The address line A7 and the control signal

IO/ M are used as enable for decoder.

27
The address line A0 of 8085 is connected to of 8251 to provide the internal addresses.
The IO addresses allotted to the internal devices of 8251 are listed above. The data line are
connected to the processor to achieve parallel data transfer. The RESET and clock signals
are supplied by the processor. Here the processor clock is directly connected to 8251. This
clock controls the parallel data transfer between the processor and the 8251.
The output clock signal of 8085, is divided by suitable clock dividers and then used as clock
for serial transmission and reception. In 8251 the transmission and reception baun rates can
be same or different.
The TTL logic levels of the serial data lines and control signals necessary for serial
transmission and reception are converted to RS232 logic levels using MAX232 and then

28
terminated on a standard 9 pin D type connector. The device which requires serial
communication with processor can be connected to this 9 pin D type connector using 9 core
cable.
The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate
interrupt driven data transfer scheme.

RS 232
A communication standard for connecting computers to printers, modems, etc.The most
common communication standard. Defined in the 1950’s.It uses voltages between +15 and –
15 V Restricted to speeds less than 20 K baud. Restricted to distances of less than 50 feet
(15 m).The original standard uses 25 wires to connect the two devices. However, in reality
only three of these wires are needed.

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