ANALOG & DIGITAL ELECTRONICS

Laboratory Manual

Department of Electrical and Electronics Engineering

Gokaraju Rangaraju
Institute Of Engineering and Technology
(Autonomous)
(Approved by A.I.C.T.E and Affiliated to JNTU) Bachupally, Kukatpally,
HYDERABAD 500090.
 Gokaraju Rangaraju Institute of Engineering and
Technology
(Autonomous Institution under JNTU Hyderabad)

Analog and Digital Electronics Lab Record

Name:

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Course: B.Tech.____ Yr____Semester

Branch: EEE
 CERTIFICATE

This is to certify that it is a bonafide record of practical

work done by Mr. /Ms._____________ ____ _____ _____ ,

Reg. No.___________________ in the ANALOG AND

DIGITAL ELECTRONICS LABORATORY in__ semester of ___

year during 20__ - 20___.

Internal Examiner External Examiner

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 CONTENTS
S. No Topic Page No.

1 Introduction to Analog discovery Kit 1

2 Steps to Waveform Software 3

3 Proportional Amplifier 6

4 Inverting Amplifier 10

5 Integrating Amplifier 15

6 Differentiating Amplifier 19

7 Summing Amplifier 23

8 Differential/Difference Amplifier 26

9 Square Wave Generator 29

10 Triangular Wave Generator 33

11 Sine Wave Generator 38

12 Digital To Analog Converter 41

13 Astable Multivibrator using a 555 Timer 44

14 Monostable Multivibrator using a 555 Timer 47

15 Logical AND-OR Gates 51

16 Half Adder and Full Adder 54

17 Half Substractor 59

18 Full Substractor 63

19 Multiplexer 67

20 2x4 Decoder 72

21 D-Flip Flop 75

22 T-Flip Flop 78

23 Annexure 82
 INTRODUCTION TO ANALOG DISCOVERY KIT

Overview
The Digilent Analog Discovery , developed in conjunction with Analog Devices Inc., is a multi-
function instrument that can measure, record and generate analog and digital signals.

Figure: Analog Discovery used in a circuit design experiment

The small, portable and low-cost Analog Discovery (above Figure) was created so that
engineering students could work with analog and digital circuits anytime, anywhere - right from
their PC. The Analog Discovery‟s analog and digital inputs and outputs connect to a circuit using
simple wire probes. Inputs and outputs are controlled using the free PC- based Waveforms
software that can configure the Discovery to work as any one of several traditional instruments.
Instruments include:

 Two channel oscilloscope (1MΩ, ±25V, differential, 14 bit, 100Msample/sec, 5MHz

bandwidth);
 Two channel arbitrary function generator (22Ω, ±5V, 14 bit, 100Msample/sec, 5MHz
bandwidth);
 Stereo audio amplifier to drive external headphones or speakers with replicated AWG
signals;
 16-channel digital logic analyzer (3.3V CMOS, 100Msample/sec)*;
 16-channel pattern generator (3.3V CMOS, 100Msample/sec)*;
 16-channel virtual digital I/O including buttons, switches and LEDs –good for logic trainer
applications*;
 Two input/output digital trigger signals for linking multiple instruments (3.3V CMOS);
 Two power supplies (+5V at 50mA, -5V at 50mA).
 Single channel voltmeter (AC, DC, ±25V);
 Network analyzer – Bode, Nyquist, Nichols transfer diagrams of a circuit. Range: 1Hz to
10MHz;
 Spectrum Analyzer - power spectrum and spectral measurements (noise floor, SFDR, SNR,
THD, etc.);
 Digital Bus Analyzers (SPI, I2C, UART, Parallel);

1
The Analog Discovery was designed for students in typical university-based circuits and
electronics classes. Its features and specifications, including operating from USB power, a small
and portable form factor, and the ability to be used by students in a variety of environments at
low cost, are based directly on inputs from many professors at many universities. Meeting all the
requirements proved challenging, and resulted in some new and innovative circuits. This
document is a reference for the Analog Discovery‟s electrical functions and operations. This
reference also provides a description of the hardware‟s features and limitations. It is not intended
to provide enough information to enable complete duplication of the Analog Discovery, or to
allow users to design custom configurations for programmable parts in the design.

The pin-out terminals of Analog Discovery Kit(AD Kit) is shown below

2
 STEPS TO RUN WAVEFORM SOFTWARE

Step1: Open the “Waveform” software from the start menu of the windows desktop

Figure: Showing the selection of Waveform software from the start menu

Step2: Each block representation of Waveform software

“in” -To check waveforms at the output terminals of the hardware connections done on Bread
board “in” is selected

“out”- To give different input signals to the circuit done on the Bread board “out” is selected

“voltage”-This option is selected to apply +Vcc and –Vcc to the circuit connections done on Bread
board

3
 Figure: showing the Window of Waveform software

Step 3: The window shown below is obtained when “in” is selected from the “Waveform” software.
Two waveforms can be seen at one time (one is “orange” and the other is “Blue”). The right side
window shows the settings of different waveforms who‟s Y and X axis can be set. After selecting
the required options, click the “Run” button on Top left side of the Window to see the obtained
output of the circuit connected on the Bread board.

Figure: Shows the “in” window of “Waveform” software

4
Step4: “Out” tab of Waveform software is used for selecting the types of waveforms like-
sinusoidal, square, triangular, trapezoidal, random signal of different frequencies from this
window. The signal selected from this window is given as input signal to the circuit connected on
the Bread board. After making the required settings click on the “Run AWG1” option from the
window.

Figure: The “Out” window of Waveform in which different waveforms can be given as input

Step5: “Voltage” is selected for giving the input voltage of either +Vcc (Constant +5V) or –Vcc
(Constant -5V) or both. When the “Power is ON/OFF” is selected the respective voltages are
applied to the circuit connected.

Figure: The “Voltage” window of Waveform helps to run the ADE kit

5
 EXPERIMENT-1

PROPORTIONAL AMPLIFIER
AIM: To demonstrate Proportional Amplifier Circuit using Op-Amp.

APPARATUS: 741/OP27 IC or its equivalent(1)

1KΩ Resistors

Analog Discovery Kit (AD Kit)

Breadboard

CIRCUIT DIAGRAM:

Figure: Proportional Ampilifier

PROCEDURE:

1. Connect the components as per the circuit diagram on the Bread board
2. The color terminals represent the connections made with respect to the Analog Discovery kit
at the respective terminals on the Bread board

6
 3. Adjust the input voltage starting with 500mv and find the output voltage.

4. Repeat the above steps for different voltages by taking two different values of load
resistance RL=1KΩ and RL =5KΩ and complete the table

5. Draw the graph between input and output voltages for the values obtained from the two tables.

Tabular Column for RL = 1KΩ:

S. No Vin V out Vout/Vin

Tabular Column for RL = 5KΩ:

S. No Vin Vout Vout/Vin

MODEL GRAPH:

7
GRAPH SHEET:

RESULT:

8
Exercise:

1. Execute the following “Voltage Follower” circuit and draw the waveforms for different
signals

9
 EXPERIMENT-2
INVERTING AMPLIFIER
AIM: To demonstrate Inverting Amplifier Circuit using Op-Amp.

APPARATUS: 741/OP27 IC or its equivalent

10 KΩ, 1KΩ Resistors

Analog Discovery Kit (AD Kit)

Breadboard

CIRCUIT DIAGRAM:

Figure: Inverting Amplifier

THEORY:

As the open loop DC gain of an Operational Amplifiers is extremely high we can therefore
afford to lose some of this high gain by connecting a suitable resistor across the amplifier from the
output terminal back to the inverting input terminal to both reduce and control the overall gain of the
amplifier. This then produces and effect known commonly as Negative Feedback, and thus produces
a very stable Operational Amplifier based system.

Negative Feedback is the process of “feeding back” a fraction of the output signal back to the
input, but to make the feedback negative, we must feed it back to the negative or “inverting input”
terminal of the op-amp using an external Feedback Resistor called Rƒ. This feedback connection
between the output and the inverting input terminal forces the differential input voltage towards zero.

This effect produces a closed loop circuit to the amplifier resulting in the gain of the amplifier
now being called its Closed-loop Gain. Then a closed-loop inverting amplifier uses negative feedback
to accurately control the overall gain of the amplifier, but at a cost in the reduction of the amplifiers
gain. This negative feedback results in the inverting input terminal having a different signal on it than
the actual input voltage as it will be the sum of the input voltage plus the negative feedback voltage

10
giving it the label or term of a Summing Point. We must therefore separate the real input signal from
the inverting input by using an Input Resistor, Rin.

In this Inverting Amplifier circuit the operational amplifier is connected with feedback to produce a
closed loop operation. When dealing with operational amplifiers there are two very important rules to
remember about inverting amplifiers, these are: “No current flows into the input terminal”and
that “V1 always equals V2”. However, in real world op-amp circuits both of these rules are slightly
broken.

This is because the junction of the input and feedback signal ( X ) is at the same potential as the
positive ( + ) input which is at zero volts or ground then, the junction is a “Virtual Earth”. Because of
this virtual earth node the input resistance of the amplifier is equal to the value of the input
resistor, Rin and the closed loop gain of the inverting amplifier can be set by the ratio of the two
external resistors.

We said above that there are two very important rules to remember about Inverting Amplifiers or any
operational amplifier for that matter and these are.
1. No Current Flows into the Input Terminals
2. The Differential Input Voltage is Zero as V1 = V2 = 0 (Virtual Earth)

PROCEDURE:

1. Connect the components as per the circuit diagram on the Bread board
2. The color terminals represent the connections made with respect to the Analog Discovery kit at
the respective terminals on the Bread board
3. Adjust the input voltage starting with 500mv and find the output voltage.
4. Repeat the above steps for different voltages by taking different input signals
5. Draw the graph between input and output voltages for the values obtained from the table.

Tabular Column:

S. No Vin V out Vout/Vin

11
Theoretical Calculations::

MODEL GRAPH:

12
GRAPH SHEET:

RESULT:

13
Exercise:
1. Execute the following “Non inverting Amplifier” circuit with different values of Rf
resistance

14
 EXPERIMENT-3
INTEGRATING AMPLIFIER
AIM: To demonstrate Integrator Amplifier Circuit using Op-Amp

APPARATUS: 741/OP27 IC or its equivalent(1)

10 KΩ, 1KΩ Resistor

100nF Capacitor

Analog Discovery Kit (AD Kit)

Breadboard

CIRCUIT DIAGRAM:

Figure: shows the Integrator

THEORY:

It is a low pass RC filter circuit. It can work as an integrator when time constant is very
large. This requires very large values of R and C by Miller‟s theorem the effective input
capacitance becomes C!(1-Av)where Av is the gain of the op-amp. The gain Av is infinite for an
ideal op-amp.so, the effective time constant of the op-amp becomes large which results in perfect
integration. The output voltage of an integrator is shown below

15
PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Suitable R f and C1 are chosen such that the output of the circuit is the integral of the input
voltage.
3. Apply square wave or sine wave input voltage (V) or any other type of signal at the input
terminal.
4. Observe the output voltage waveform on the CRO and note down the corresponding values.
5. The time constant RfC1 is changed by changing the values of R f or C1 and the corresponding
output waveforms are noted.

MODEL GRAPH:

Figure: showing the output waveforms for different input waveforms

16
Tabular Column

S. No Vin V out Vout/Vin

Theoretical Calculations:

17
GRAPH SHEET:

RESULT:

18
 EXPERIMENT-4

DIFFERENTIATING AMPLIFIER
AIM: To demonstrate Differentiate Amplifier Circuit using Op-Amp.

APPARATUS: 741/OP27 IC or its equivalent(1)

10 KΩ, 1.5KΩ Resistors

0.1µF Capacitor

Analog Discovery Kit(AD Kit)

Breadboard/PCB

CIRCUIT DIAGRAM:

Figure: shows the Differentiator

THEORY:

It consists of an high pass RC filter .it acts as a differentiator for low values of time constant. Here the
output is the derivative of the input signal by

Thus output is not only the derivative of the input but also out of phase by 180o with respect to the
input.

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PROCEDURE:

1. Connect the circuit as shown in the circuit diagram.

2. Suitable values of R1, R2, C1, C2 are chosen such that the output of the circuit is the integral of
the input voltage.
3. A square wave input voltage (V) is applied at the input terminal.
4. Observe the output voltage waveform on the CRO and note down the corresponding values.
5. The time constant R2C1 is changed by changing the values of R 2 or C1 and the corresponding
output waveforms are noted.

MODEL GRAPHS:

Figure: Model output waveforms for different input signals

20
Tabular Column

S. No Vin V out Vout/Vin

Theoritical Calculations:

21
GRAPH SHEET:

RESULT:

22
 EXPERIMENT-5

SUMMING AMPLIFIER

AIM: To demonstrate Summing Amplifier Circuit using Op-Amp.

APPARATUS: 741/OP27 IC or its equivalent

10 KΩ, 1.5KΩ Resistors
Analog Discovery Kit (AD Kit)

Breadboard

THEORY:
Summing amplifier is a circuit whose output is the sum of several input signals. For
example: An inverting summing amplifier with two input voltages V1 and V2 two input resistors
R1 and R2 and a feedback resistor (consider all are of equal values).

CIRCUIT DIAGRAM :

Figure: Summing Amplifier Circuit

23
PROCEDURE:

1. Connect the relevant circuit for the summing configuration as shown in the
circuit diagram.
2. Measure the output voltage Vo from AD Kit.
3. Observe the waveforms at V1, V2, and Vo.
4. Note the phase of the output voltage Vo with respect to the input voltage.
5. Set different values of two input voltages, and find the output voltage
6. Repeat the steps 3, 4, and 5.
7. The waveforms are to be plotted.
Tabular Column :

S.No Vin V out Vout/Vin

Theoritical Calculations:

24
GRAPH SHEET:

RESULT:

25
 EXPERIMENT-6
DIFFERENTIAL AMPLIFIER

AIM: To demonstrate Summing Amplifier Circuit using Op-Amp.

APPARATUS: 741/OP27 IC or its equivalent(1)

Resistors 2.2KΩ, 10KΩ
Analog Discovery Kit( AD Kit)

Breadboard

CIRCUIT DIAGRAM:

Figure: Differential Amplifier

THEORY:
The differential amplifiers amplify the difference between two voltages making this type of
operational amplifier circuit a Subtractor unlike a summing amplifier which adds or sums together
the input voltages. This type of operational amplifier circuit is commonly known as a Differential
Amplifier configuration.
By connecting each input in turn to 0v ground we can use superposition to solve for the output
voltage Vout. Then the transfer function for a Differential Amplifier circuit is given as:

When resistors, R1 = R2 and R3 = R4 the above transfer function for the differential amplifier can
be simplified to the following expression:

26
If all the resistors are all of the same ohmic value, that is: R1 = R2 = R3 = R4 then the circuit will
become a Unity Gain Differential Amplifier and the voltage gain of the amplifier will be exactly
one or unity. Then the output expression would simply be Vout = V2 - V1. Also note that if input
V1 is higher than input V2 the output voltage sum will be negative, and if V2 is higher than V1, the
output voltage sum will be positive.

The Differential Amplifier circuit is a very useful op-amp circuit and by adding more resistors in
parallel with the input resistors R1 and R3, the resultant circuit can be made to either “Add” or
“Subtract” the voltages applied to their respective inputs. One of the most common ways of doing
this is to connect a “Resistive Bridge” commonly called a Wheatstone Bridge

PROCEDURE:

1. Connect the relevant circuit for the difference configuration as shown in the circuit
diagram.
2. Measure the output voltage Vo from AD Kit.
3. Observe the waveforms at V1, V2, and Vo.
4. Note the phase of the output voltage Vo with respect to the input voltage.
5. Set different values of two input voltages, and find the output voltage
6. Repeat the steps 3, 4, and 5.
7. The waveforms are to be plotted.
Tabular Column :

S.No Vin V out Vout/Vin

Theoritical Calculations:

27
GRAPH SHEET:

RESULT:

28
 EXPERIMENT-7
SQUAREWAVE GENERATOR
AIM: To construct and demonstrate square wave generator using op-amp.

APPARATUS:
LM 741/OP27 or its equivalent
Capacitor – 0.1µF
Resistors – 10KΩ (2), 1KΩ (2)
AD Kit
Bread Board.
THEORY:
The non-sinusoidal waveform generators are also called relaxation oscillators. The op-amp
relaxation oscillator shown in figure is a square wave generator. In general, square waves are relatively
easy to produce.
The comparator uses positive feedback that increases the gain of the amplifier. In a comparator
circuit this offer two advantages. First, the high gain causes the op-amp‟s output to switch very quickly
from one state to another and vice-versa. Second, the use of positive feedback gives the circuit hysteresis.
In the op-amp square-wave generator circuit given in figure, the output voltage v out is shunted to ground
by two Zener diodes Z1 and Z2 connected back-to-back and is limited to either VZ 2 or –VZ 1. A fraction of
the output is fedback to the non-inverting (+) input terminal. Combination of IL and C acting as a low-
pass R-C circuit is used to integrate the output voltage v out and the capacitor voltage vc is applied to the
inverting input terminal in place of external signal. The differential input voltage is given as vin = vc - β
vout

When vin is positive, vout = – Vz1 and when vin is negative vout = + Vz 2. Consider an instant of time
when vin < 0. At this instant vout = + Vz 2 , and the voltage at the non-inverting (+) input terminal is β Vz 2 ,
the capacitor C charges exponentially towards Vz 2, with a time constant R f C. The output voltage remains
constant at Vz 2 until vc equal β Vz 2.

When it happens, comparator output reverses to – Vz 1. Now vc changes exponentially towards -

Vz1 with the same time constant and again the output makes a transition from -Vz1 to + Vz 2. when
vc equals -βVz 1

Let Vz1 = Vz 2

The time period, T, of the output square wave is determined using the charging and discharging
phenomena of the capacitor C. The voltage across the capacitor, vc when it is charging from – β Vz to + Vz
is given by

29
Vc = [1-(1+β)]e-T/2τ

Where τ = RfC

The waveforms of the capacitor voltage vc and output voltage vout (or vz) are shown in figure.

When t = t/2

Vc = +β Vz or + β Vout

Therefore β Vz = Vz [1-(1+β)e-T/2τ]

Or e-T/2τ = 1- β/1+ β

Or T = 2τ loge 1+β/1- β = 2Rf C loge [1+ (2R3/R2)]

The frequency, f = 1/T , of the square-wave is independent of output voltage V out. This circuit is
also known as free-running or astable multivibrator because it has two quasi-stable states. The output
remains in one state for time T1 and then makes an abrupt transition to the second state and remains in that
state for time T2. The cycle repeats itself after time T = (T1 + T2) where T is the time period of the square-
wave.

The op-amp square-wave generator is useful in the frequency range of about 10 Hz -10 kHz. At
higher frequencies, the op-amp‟s slew rate limits the slope of the output square wave. The symmetry of
the output waveform depends on the matching of two Zener diodes Z1 and Z2. The unsymmetrical square-
wave (T1 not equal to t2) can be had by using different constants for charging the capacitor C to +V out and
-Vout

30
 CIRCUIT DIAGRAM:

Figure: Circuit diagram for square wave generator

PROCEDURE:

1. Expression for the frequency of oscillation,

f = 1/ (2RCloge (1+ β/1-β)), where β = (R3/R3+R2).
2. Choose any frequency between 1 kHz and 5 kHz and select the values of R1, R2, R, and C.
3. Connect the circuit as per the circuit diagram and give the supply volt age.
4. Observe the frequency of operation of the circuit and compare with the theoretical values.
5. Change the R and C values to change the frequency and oscillation and verify with the
theoretical values.
6. Trace the output waveform for inverting and non-inverting inputs.
MODEL GRAPHS:

31
GRAPH SHEET:

RESULT:

Exercise:
1. Write a short notes on types of oscillators and their applications
32
 EXPERIMENT-8

TRIANGULAR WAVE GENERATOR

AIM: To construct and demonstrate Triangular wave generator using LM741/OP27.

APPARATUS:
LM741/OP27 or its equivalent
Resistors – 10kΩ (2),22kΩ, 47kΩ
Capacitor – 0.1µF
Analog discovery Kit (AD Kit)
Bread Board
THEORY:

This experiment is about a triangular wave generator using opamp IC. Triangular wave is a periodic, non-
sinusoidal waveform with a triangular shape. People often get confused between triangle and sawtooth
waves. The most important feature of a triangular wave is that it has equal rise and fall times while a
sawtooth wave has un-equal rise and fall times. The applications of triangular wave include sampling
circuits, thyristor firing circuits, frequency generator circuits, tone generator circuits etc. There are many
methods for generating triangular waves but here we focus on method using opamps. This circuit is based
on the fact that a square wave on integration gives a triangular wave.

The circuit uses an opamp based square wave generator for producing the square wave and an opamp
based integrator for integrating the square wave. The circuit diagram is shown in the figure. The square
wave generator section and the integrator section of the circuit is explained in detail.

Square wave generator:

The square wave generator is based on a uA741 opamp (IC1). Resistor R1 and capacitor C1

33
 Figure: Shows the circuit diagram of Triangular wave generator

determines the frequency of the square wave. Resistor R2 and R3 forms a voltage divider setup which
feedbacks a fixed fraction of the output to the non-inverting input of the IC.

Initially, when power is not applied the voltage across the capacitor C 1 is 0V. When the power supply is
switched ON, the C1 starts charging through the resistor R1 and the output of the opamp will be high
(+Vcc). A fraction of this high voltage is fed back to the non- inverting pin by the resistor network R2, R3.
When the voltage across the charging capacitor is increased to a point the the voltage at the inverting pin
is higher than the non-inverting pin, the output of the opamp swings to negative saturation (-Vcc). The
capacitor quickly discharges through R1 and starts charging in the negative direction again through R 1.
Now a fraction of the negative high output (-Vcc) is fed back to the non-inverting pin by the feedback
network R2, R3. When the voltage across the capacitor has become so negative that the voltage at the
inverting pin is less than the voltage at the non-inverting pin, the output of the opamp swings back to the
positive saturation. Now the capacitor discharges trough R1 and starts charging in positive direction. This
cycle is repeated over time and the result is a square wave swinging between +Vcc and -Vcc at the output
of the opamp.

If the values of R2 and R3 are made equal, then the frequency of the square wave can be expressed using
the following equation:

F=1 / (2.1976 R1C1)

Integrator:

Next part of the triangular wave generator is the opamp integrator. Instead of using a simple passive RC
integrator, an active integrator based on opamp is used here. The opamp IC used in this stage is also
uA741 (IC2). Resistor R5 in conjunction with R4 sets the gain of the integrator and resistor R 5 in
conjunction with C2 sets the bandwidth. The square wave signal is applied to the inverting input of the
opamp through the input resistor R4. The opamp integrator part of the circuit is shown in the figure below.

34
Let‟s assume the positive side of the square wave is first applied to the integrator. By virtue capacitor C 2
offers very low resistance to this sudden shoot in the input and C2 behaves something like a short circuit.
The feedback resistor R5 connected in parallel to C2 can be put aside because R5 has almost zero
resistance at the moment. A serious amount of current flows through the input resistor R4 and the
capacitor C2 bypasses all these current. As a result the inverting input terminal (tagged A) of the opamp
behaves like a virtual ground because all the current flowing into it is drained by the capacitor C 2. The
gain of the entire circuit (Xc2/R4) will be very low and the entire voltage gain of the circuit will be close
the zero.

After this initial “kick” the capacitor starts charging and it creates an opposition to the input current
flowing through the input resistor R4. The negative feedback compels the opamp to produce a voltage at
its out so that it maintains the virual ground at the inverting input. Since the capacitor is charging its
impedance Xc keeps increasing and the gain Xc2/R4 also keeps increasing. This results in a ramp at the
output of the opamp that increases in a rate proportional to the RC time constant (T=R 4C2) and this ramp
increases in amplitude until the capacitor is fully charged.

When the input signal (square wave) falls to the negative peak at integrator, the capacitor quickly
discharges through the input resistor R4, and starts charging in the opposite polarity. Now the conditions
are reversed and the output of the opamp will be a ramp that is going to the negative side at a rate
proportional to the R4R2 time constant. This cycle is repeated and the result will be a triangular waveform
at the output of the opamp integrator.

CIRCUIT DIAGRAM:

35
PROCEDURE:

1. Connect the components on the bread board as shown in the Circuit diagram
2. Connect the AD kit and find the output voltage and its frequency of the circuit connected on the
Bread board
3. Calculate the frequency by changing the value of R1.
4. Tabulate the values taken and write the frequency obtained
5. Plot the graph of output voltage considering both square and triangular waves.

Tabular Column:
Square Triangular OFF
S.No R2(kΩ) fth ON Time fp
Amplitude Amplitude Time

MODEL GRAPH:

36
GRAPH SHEET:

RESULT:

37
 EXPERIMENT-9

SINE WAVE GENERATOR

AIM: To construct and demonstrate Sine wave generator using LM741/OP27.

APPARATUS: LM741/OP27 or its equivalent

Resistors – 10KΩ (2), 22KΩ, 47KΩ
Capacitor – 0.1µF
Analog discovery Kit (AD Kit)
Bread Board
CIRCUIT DIAGRAM

Figure: Sine wave generator Circuit

THEORY:

The AM modulation is a kind of modulation technique which is in use since the very early days
of wireless data transmission. In a radio transmission system there is a relation between the ranges of
frequencies which can be transmitted wirelessly with the length of the transmitting antenna. The relation
is inversely proportional to one another, means as the frequency of the signal to be transmitted increases
the length of the antenna can be reduced and as the frequency of the signal to be transmitted decreases the
length of the transmitting antenna should be increased accordingly.

Using an antenna of few meters the frequencies in the range of Mhz can be easily transmitted to a
distance. The basic purpose of the wireless transmitting system in early days was to transmit the audio
signals, but to transmit audio signals which fall in the range of few Khz an antenna of more than a
kilometer height would have been required. Since it was practically impossible to construct such a long
antenna, the high frequency signals are transmitted after they are modulated with the low frequency audio
signals.

38
 The amplitude modulation is the simplest modulation technique among the wide verity of
modulation techniques in use. The amplitude modulation of a high frequency signal is easy to achieve and
the demodulation is also simple compared to other techniques. The high frequency signal which

is modulated to carry the low frequency audio signals are called „carrier frequency‟ and the audio
signals used for modulation is called „modulating signal‟ or „message signal‟ or „base band signal‟.

Variable frequency sine wave generator

The sine wave generation circuit used in this project is the Wien bridge oscillator circuit. This is
the only circuit which can generate the pure sine wave without any distortion. The amplifier component
used in the Wien bridge circuit is an op-amp with dual-power supply. Both the circuits are built around
the versatile op-amp IC, 741. The circuit of the sine wave generator is shown

The frequency of the above circuit can be varied by simply varying the potentiometer R2 and the
amplitude of the wave form can be adjusted by varying the potentiometer R. The frequency of the sine
wave generated by the above circuit depends on the components R1, R2, C1 and C2 and the equation for
the frequency is given

PROCEDURE:

1. Connect the components on the bread board as shown in the Circuit diagram
2. Connect the AD kit and find the output voltage and its frequency of the circuit connected on the
Bread board for different values of Resistance
3. Calculate the frequency by changing the value of R2 .
4. Tabulate the values taken and write the frequency obtained
5. Plot the graph of output voltage of sine wave.

Tabular Column:
S.No R2(kΩ) fp

MODEL GRAPH:

39
GRAPH SHEET:

RESULT:

Exercise:
1. Write the applications of Sine wave generator

40
 EXPERIMENT-10

DIGITAL TO ANALOG CONVERTER

(R-2R LADDER METHOD)

AIM: To construct a 4-bit R-2R ladder type of digital to analog converter for R = 1K.

APPARATUS:
Operational Amplifier – LM741/OP 27 or its equivalent
Resistors – 1kΩ, 2.2kΩ (3), 3.3kΩ (3)
Analog Discovery Kit
Bread Board
CIRCUIT DIAGRAM:

Figure: R-2R Ladder Diagram for D to A converter

THEORY:
R-2R ladder DAC, avoids the use of wide range of resistors. This makes the circuit suitable for
monolithic fabrication. Typical range of values of R will be in 2-10KΩ.

PROCEDURE:
1. Set up the circuit as shown in the circuit diagram.
2. Apply the digital input of two bit and measure the analog output voltage for each of the
possible combinations.
3. Plot the digital input versus the analog output voltage using AD kit.
4. Calculate the maximum linearity error and accuracy. Specify the percentage resolution.

41
MODEL GRAPH:

Theoretical Calculations:

42
GRAPHSHEET:

RESULT:

Exercise:
1. Write types of Digital to Analog converters and their applications.
43
 EXPERIMENT-11

ASTABLE MULTIVIBRATOR USING A 555 TIMER

AIM: To design an Astable Multivibrator using a 555 timer

APPARATUS:
Operational Amplifier – 555/565 Timer
Capacitors – 10µF, 0.01µF
Resistors – 4.7kΩ, 100kΩ (variable), 1kΩ, 330Ω
LED (Optional)
Analog Discovery Kit (AD Kit)
Bread Board.

CIRCUIT DIAGRAM:

Figure: Astable Multivibrator using 555 timer

THEORY:

An astable multivibrator, also known as “free running multivibrator” is nothing but an

oscillator that generates square waves. These waves are required to control the timing circuits.
These multivibrator circuits can be designed using an op-amp.
An astable multivibrator designed using a 555-Timer op-amp is shown. To explain the
principle operation, the internal circuit diagram of 555 Timer is also shown beside.

44
PROCEDURE:

1. Calculate the values of R, R, and C for different duty cycles using the formulae given.
2. Connect the circuit as per the diagram.
3. Calculate the frequency of the astable multivibrator by noting the waveform and compare it with
the theoretical values.
4. Change the value of R and C to change the frequency of oscillation and verify the theoretical
values.
5. Note the output voltages at pin no. 3 and capacitor voltage at pin no.6 and plot it on a graph sheet.

MODEL GRAPH:

Figure: Model graphs of Astable Multivibrator

OBSERVATIONS:

S N0. %Duty Theoretical Practical Capacitor Resistor Resistor

Cycle Frequency Frequency C in µf RA in KΩ RB in KΩ
(KHz) (KHz)
1

Theoretical Calculations:

45
 GRAPH SHEET:

RESULT:

Exercise:
1. Derive the expression of Frequency for the Astable Multivibrator

46
 EXPERIMENT-12

MONOSTABLE MULTIVIBRATOR USING A 555 TIMER

AIM: To use a 555 timer as Monostable Multivibrator

APPARATUS:
IC 555 – 1No.
Resistors – 100kΩ, 47kΩ(2), 470Ω
Capacitors – 10µF, 10nF
Switch (S1)
Analog Discovery Kit
Bread Board

CIRCUIT DIAGRAM:

Figure: Monostable Multivibrator

THEORY:

Monostable multivibrator often called a one shot multivibrator is a pulse generating circuit in which the
duration of this pulse is determined by the RC network connected externally to the 555 timer. In a stable
or standby state, the output of the circuit is approximately zero or a logic-low level.

When external trigger pulse is applied output is forced to go high ( VCC). The time for which output
remains high is determined by the external RC network connected to the timer. At the end of the timing
47
interval, the output automatically reverts back to its logic-low stable state. The output stays low until
trigger pulse is again applied. Then the cycle repeats. The monostable circuit has only one stable state
(output low) hence the name monostable.

Initially when the circuit is in the stable state i.e , when the output is low, transistor Q1(internal of 555
Timer) is ON and the capacitor C is shorted out to ground. Upon the application of a negative trigger
pulse to pin 2, transistor Q1(internal of 555 Timer) is turned OFF, which releases the short circuit across
the external capacitor C and drives the output high. The capacitor C now starts charging up towards VCC
through R. When the voltage across the capacitor equals 2/3 V CC, comparator 1‟s output switches from
low to high, which inturn drives the output to its low state via the output of the flip-flop.

At the same time the output of the flip-flop turns transistor Q1(internal of 555 Timer) ON and hence the
capacitor C rapidly discharges through the transistor. The output of the Monostable remains low until a
trigger pulse is again applied. Then the cycle repeats.

The pulse width of the trigger input must be smaller than the expected pulse width of the output
waveform. Also the trigger pulse must be a negative going input signal with amplitude larger than 1/3
VCC.

The time during which the output remains high is given by

where R is in Ohms and C is in Farads.

Once triggered, the circuit‟s output will remain in the high state until the set time, t elapses. The output
will not change its state even if an input trigger is applied again during this time interval t. The circuit can
be reset during the timing cycle by applying negative pulse to the reset terminal. The output will remain
in the low state until a trigger is again applied.

PROCEDURE:

1. Connect the trigger circuit as shown in the circuit diagram.

2. Apply the square wave input to the trigger circuit and apply the output of this trigger
circuit to the pin no. 2 of the 555 timer.
3. Now observe the output of the monostable multivibrator and compare the values of the
gate width with the theoretical values.
4. The gate width of the monostable multivibrator is given by, GATE WIDTH = 1.1RC.

48
WAVEFORMS:

Figure: Model Waveforms

Tabular Column:

GATE WIDTH OF THE OUPUT

S.No. R (kΩ) C (µF)
THEORITICAL PRACTICAL

Theoretic Calculations:

49
GRAPH SHEET:

RESULT:

50
 EXPERIMENT-13

LOGICAL AND & OR GATES

Aim: To write verilog code for logical AND & OR Gates .

Software tools: Xilinx ISE 9.2i

Verilog Code:

AND GATE:
module and(a,b,c); input a,
b; output c; assign
c=a&b;
endmodule

OR GATE:
module or(a,b,c); input a, b;
output c; assign
c=a^b;
endmodule

51
Test Bench:

module add_tb_v;
// Inputs reg a;
reg b;
// Outputs
wire c;
// Instantiate the Unit Under Test (UUT)
add uut (
.a(a),
.b(b),
.c(c)

);
initial begin
// Initialize Inputs
a = 0; b = 0; // Wait 100 ns for global reset to finish
#100;a=0;b=1;
#100;a=1;b=0;
#100;a=1;b=1;
end
endmodule

Truth Table:

AND Gate: OR Gate:

52
Simulation Result:
AND Gate:

OR Gate:

53
 EXPERIMENT-14

HALFADDER & FULLADDER

Aim: To write verilog code for half adder and Full adder.

Software tools: Xilinx ISE 9.2i

Verilog Code:

module fulladder(a,b,c,sum,carry);
input a, b, c;
output sum, carry;
wire s1, c1, c2;
had h1(a,b,s1,c1);
had h2(s1,c,sum,c2);
assign carry=c1|c2;
endmodule

Verilog Code for half adder:

module had(a,b,s,c);
input a, b;
output s, c;
assign s=a^b;
assign c=a&b;
endmodule

54
Test Bench:

module fulladder_tb_v;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire sum;
wire carry;
// Instantiate the Unit Under Test (UUT)
fulladder uut (
.a(a),
.b(b),
.c(c),
.sum(sum),
.carry(carry)
);
initial begin
// Initialize Inputs
a = 0; b = 0; c = 0;
// Wait 100 ns for global reset to finish
#100;a=0;b=0;c=1;
#100;a=0;b=1;c=0;
#100;a=0;b=1;c=1;
#100;a=1;b=0;c=1;
#100;a=1;b=0;c=1;
#100;a=1;b=1;c=0;
#100;a=1;b=1;c=1;
end
endmodule

55
Simulation Result:

Schematic Diagram:

Block Diagram

56
Circuit diagram of full adder

Circuit Diagram of Half adder

57
Synthesis Report:

Quartus II Version 6.0 Build 178 04/27/2006 SJ Web Edition

Revision Name verilog
Top-level Entity Name fulladder
Family Cyclone II
Device EP2C35F672C6
Timing Models Final
Met timing requirements Yes
Total logic elements 2 / 33,216 ( < 1 % )
Total registers 0
Total pins 5 / 475 ( 1 % )
Total virtual pins 0
Total memory bits 0 / 483,840 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 70 ( 0 % )
Total PLLs 0/4(0%)

58
 EXPERIMENT-15

HALF SUBTRACTOR
Aim: To write a verilog code for half subtractor.

Software tools: Xilinx ISE 9.2i

Verilog code:

module halfsub(a, c, b, d);

input a;
input c;
output b;
output d;
assign d=a^c;
assign b=((!a)&c);
endmodule

59
Test Bench:

module halfsub_tb_v;

reg a;

reg c;

wire b;

wire d;

halfsub uut (

.a(a),

.c(c),

.b(b),

.d(d));

always begin

a = 0;c = 0;

#100;a=0;c=1;

#100;a=1;c=0;

#100;a=1;c=1;

#100; end

endmodule

60
Simulation Result:

Schematic Diagram:

Block diagram

Circuit diagram of half subtractor

61
Circuit diagram of half subtractor

62
 EXPERIMENT-16

FULL SUBTRACTOR
Aim: To write a verilog code for full subtractor.

Software tools: Xilinx ISE 9.2i, Quartus II 6.0

Verilog code:

module fullsubtractor(a, b, c, d, br);

input a;
input b;
input c;
output d;
output br;
assign d=(c+(!c)&(a^b));
assign br=((!a)&b)+c;
endmodule

63
Test Bench:
module fullsub_tb_v;

reg a;

reg c;

reg e;

wire b;

wire d;

fullsub uut (

.a(a),

.c(c),

.e(e),

.b(b),

.d(d) );

always begin

a = 0;c = 0;e = 0;

#100;a=0;c=0;e=1;

#100;a=0;c=1;e=0;

#100;a=0;c=1;e=1;

#100;a=1;c=0;e=0;

#100;a=1;c=0;e=1;

#100;a=1;c=0;e=0;

64
 #100;a=1;c=0;e=1;

#100;a=1;c=1;e=0;

#100;a=1;c=1;e=1;

#100;

end

endmodule

Simulation result:

Schematic Diagram:

Block diagram

65
Circuit diagram of full subtractor

Circuit diagram of full subtractor.

66
 EXPERIMENT-17

MULTIPLEXER

Aim: To write a verilog code for 16x1 multiplexer using 2x1 multiplexer.

Software tools: Xilinx ISE 9.2i

Verilog code:

module mux16by1(e,i,s,y);
input [15:0]i;
input [3:0]s;
input e;
output y;
wire [7:0]i1;
wire [3:0]i2;
wire [1:0]i3;
mux2by1 m1(e,i[0],i[1],s[0],i1[0]);
mux2by1 m2(e,i[2],i[3],s[0],i1[1]);
mux2by1 m3(e,i[4],i[5],s[0],i1[2]);
mux2by1 m4(e,i[6],i[7],s[0],i1[3]);
mux2by1 m5(e,i[8],i[9],s[0],i1[4]);
mux2by1 m6(e,i[10],i[11],s[0],i1[5]);
mux2by1 m7(e,i[12],i[13],s[0],i1[6]);
mux2by1 m8(e,i[14],i[15],s[0],i1[7]);
mux2by1 m9(e,i1[0],i1[1],s[1],i2[0]);
mux2by1 m10(e,i1[2],i1[3],s[1],i2[1]);
mux2by1 m11(e,i1[4],i1[5],s[1],i2[2]);
mux2by1 m12(e,i1[6],i1[7],s[1],i2[3]);
mux2by1 m13(e,i2[0],i2[1],s[2],i3[0]);

67
 mux2by1 m14(e,i2[2],i2[3],s[2],i3[1]);
mux2by1 m15(e,i3[0],i3[1],s[3],y);
endmodule

Verilog code for 2x1mux:

module mux2by1(e,a,b,s,y);
input s, e;
input a, b;
output y;
assign y=(e&~s&a)|(e&s&b);
endmodule

Test Bench:

module mux16by1_tb_v;

// Inputs
reg e;
reg [15:0] i;
reg [3:0] s;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

mux16by1 uut (
.e(e),
.i(i),
.s(s),
.y(y)

68
 );

initial begin
// Initialize Inputs
e = 0;
i = 0;
s = 0;

// Wait 100 ns for global reset to finish

#100;e=1;i=16'haaaa;s=4'h0;
#100;s=4'h1;
#100;s=4'h2;
#100;s=4'h3;
#100;s=4'h4;
#100;s=4'h5;
#100;s=4'h6;
#100;s=4'h7;
#100;s=4'h8;
#100;s=4'h9;
#100;s=4'ha;
#100;s=4'hb;
#100;s=4'hc;
#100;s=4'hd;
#100;s=4'he;
#100;s=4'hf;

end

endmodule

69
Simulation Result:

Schematic Diagram:

Block diagram of 16x1 mux

70
Circuit diagram of 16x1 mux

Circuit Diagram of 2x1 mux

71
 EXPERIMENT-18
2x4 DECODER

Aim: To write a verilog code for 2x1 decoder.

Software tools: Xilinx ISE 9.2i

Verilog code:
module decoder(A0,A1,D0,D1,D2,D3);
input A0,A1;
output D0,D1,D2,D3;
assign D0=!A0&!A1;
assign D1=A0&!A1;
assign D2=!A0&A1;
assign D3=A0&A1;
endmodule

Test Bench:
module decode_tb_v;

// Inputs
reg A0;
reg A1;

// Outputs
wire D0;
wire D1;
wire D2;
wire D3;

// Instantiate the Unit Under Test (UUT)

72
 decoder uut (
.A0(A0),
.A1(A1),
.D0(D0),
.D1(D1),
.D2(D2),
.D3(D3)
);

initial begin
// Initialize Inputs
A0 = 0;
A1 = 0;

// Wait 100 ns for global reset to finish

#100;A0 = 0;A1 = 1;
#100;A0 = 1;A1 = 0;
#100;A0 = 1;A1 = 1;
#100;A0 = 0;A1 = 0;
#100;A0 = 0;A1 = 1;
#100;A0 = 1;A1 = 0;
#100;A0 = 1;A1 = 1;
#100;A0 = 0;A1 = 1;
#100;A0 = 1;A1 = 0;
#100;A0 = 1;A1 = 1;

// Add stimulus here

end

endmodule

73
Simulation Result:

Circuit diagram:

Truth Table:

74
 EXPERIMENT-19
D-FLIP FLOP

Aim: To write a verilog code for D-flip flop.

Software tools: Xilinx ISE 9.2i

Verilog code:
module dflipflop(clk, e, d, q);
input clk;
input e;
input d;
output reg q;
always@(posedge clk or negedge e)
q=d;
endmodule

75
Test bench:

module dflipflop_tb_v;
// Inputs
reg clk;
reg e;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
dflipflop uut (
.clk(clk),
.e(e),
.d(d),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
e = 0;
d = 0;
end
// Wait 100 ns for global reset to finish
always#100 clk=~clk;
always begin
#100;e=1;d=0;
#100;d=1;
#100;
// Add stimulus here
end
endmodule

76
Simulation result:

Schematic:

Block diagram of D flip

flop

Circuit diagram of D flip flop

Exercise:
1. Write the Verilog program for S-R Flip Flop
77
 EXPERIMENT-20
T-FLIP FLOP

Aim: To write a verilog code for T-flip flop.

Software tools: Xilinx ISE 9.2i

Verilog code:
module t_ff(t, clk, rst, q);
input t; input
clk; input rst;
output reg q;
always @ (posedge rst or negedge clk)
begin
if(rst)
q=1'b0;
else
q=~t;

end
endmodule

78
Test bench:

module t_ff_tb_v;

// Inputs

reg t;

reg clk;

reg rst;

// Outputs

wire q;

// Instantiate the Unit Under Test (UUT)

t_ff uut (

.t(t),

.clk(clk),

.rst(rst),

.q(q)

);

initial begin

// Initialize Inputs

clk = 0;

rst = 1;

t=0;

// Wait 100 ns for global reset to finish

79
 #100; rst=0;

end

always #50 clk=~clk;

always begin

#100; t=0;

#100; t=1;

// Add stimulus here

end

endmodule

Simulation waveform:

80
Schematic:

Block diagram of T flip Flop

Circuit diagram of T flip flop

Exercise:
1. Write the Verilog program for J-K Flip Flop

81
 Annexure
1. LM741 IC
Operational Amplifiers often known as Op-Amps are used in a range of circuits. They are
generally used to amplify weak electrical current in a circuit. It is one of the most versatile
devices in all of electronics. Op-amps are integrated circuits that cram the equivalent of many
transistors, resistors and capacitor into a small silicon chip.
The most popular type of Op Amp is the 741 as shown below as 8 pin dual layout IC's. They are
represented in circuit diagrams as follows:

V + : non-
inverting input

V − : inverting
input

Vout: output

VS + : positive
power supply

VS − : negative
power supply

The op-amp is basically a differential amplifier having a large voltage gain, very high input
impedance and low output impedance. The op-amp has a "inverting" or (-) input and "non-
inverting" or (+) input and a single output. The op-amp is usually powered by a dual polarity
power supply in the range of +/- 5 volts to
+/- 15 volts.

82
The chip can be used in a circuit in two ways. If the voltage goes into pin 2 then it is
known as an INVERTING AMPLIFIER.
If the voltage goes into pin 3 then the circuit becomes a NON-INVERTING AMPLIFIER.

2. 555 TIMER

The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse
generation, and oscillator applications. The 555 can be used to provide time delays, as an
oscillator, and as a flip-flop
element.

The connection of the pins for a DIP package is as follows:

Pin Name Purpose

1 GND Ground, low level (0 V)

2 TRIG OUT rises, and interval starts, when this input falls below 1/3 VCC.

3 OUT This output is driven to approximately 1.7V below +VCC or GND.

A timing interval may be reset by driving this input to GND, but the timing does
4 RESET not begin again until RESET rises above approximately 0.7 volts. Overrides

TRIG which overrides THR.

83
5 CTRL "Control" access to the internal voltage divider (by default, 2/3 VCC).

6 THR The interval ends when the voltage at THR is greater than at CTRL.

7 DIS Open output; may discharge a capacitor between intervals. In phase with
collector output.

8 VCC Positive supply voltage is usually between 3 and 15 V.

Modes
The 555 has three operating modes:

Monostable mode: in this mode, the 555 functions as a "one-shot" pulse generator.
Applications include timers, missing pulse detection, bounce free switches, touch switches,
frequency divider, capacitance measurement, pulse-width modulation (PWM) and so on.
Astable: free running mode: the 555 can operate as an oscillator. Uses include LED
and lamp flashers, pulse generation, logic clocks, tone generation, security
alarms, pulse position modulation and so on. The 555 can be used as a simple ADC,
converting an analog value to a pulse length. E.g. selecting a thermistor as timing resistor
allows the use of the 555 in a temperature sensor: the period of the output pulse is
determined by the temperature. The use of a microprocessor based circuit can then
convert the pulse period to temperature, linearize it and even provide calibration
means.
 Bistable mode or Schmitt trigger: the 555 can operate as a flip-flop, if the DIS pin is not
connected
and no capacitor is used. Uses include bounce-free latched switches.

84