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Syllabus of LPV

This document outlines the objectives and outcomes of a course on low power VLSI design. The course focuses on understanding sources of power dissipation in CMOS structures, low power adders and multipliers, low power transforms, and low power static RAM architectures. It covers topics like power dissipation modeling and estimation, behavioral and logic level synthesis for low power, and energy recovery techniques. The course is divided into 6 units that cover these topics in depth over 45 lecture hours and 30 self-study hours.

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80 views2 pages

Syllabus of LPV

This document outlines the objectives and outcomes of a course on low power VLSI design. The course focuses on understanding sources of power dissipation in CMOS structures, low power adders and multipliers, low power transforms, and low power static RAM architectures. It covers topics like power dissipation modeling and estimation, behavioral and logic level synthesis for low power, and energy recovery techniques. The course is divided into 6 units that cover these topics in depth over 45 lecture hours and 30 self-study hours.

Uploaded by

kalaiyarasi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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15VL24 LOW POWER VLSI DESIGN

3204
Course Objectives
 To understand different sources of power dissipation in CMOS & MIS structure.
 To understand the different types of low power adders and multipliers
 To focus on synthesis of different level low power transforms.
 To gain knowledge on low power static RAM architecture & the source of power
dissipation in SRAM
 To understand the various energy recovery techniques used in low power design
Course Outcomes (COs)
1. An ability to analyze different source of power dissipation and the factors involved in.
2. Able to understand the different techniques involved in low power adders and
multipliers
3. Understandings of the impact of various low power transform
4. An ability to identify and analyze the different techniques involved in low power
SRAM.
5. Able to understand various energy recovery techniques.

Unit I
Power Dissipation in CMOS
Sources of power Dissipation–Physics of power dissipation in MOSFET devices, Power
dissipation in CMOS, Power dissipation in Domino CMOS-Low power VLSI design limits.
9 Hours
Unit II
Power Estimation
Modeling of signals- Signal probability calculation-probabilistic techniques for signal activity
estimation-statistical techniques for power estimation-estimation of glitch power-sensitivity
analysis-power estimation at the circuit level-estimation of maximum power.
9 Hours
Unit III
Synthesis for Low power
Behavioral level transforms-Algorithm using First –Order, second, Mth Order Differences-
Parallel Implementation Pipelined Implementation- Logic level optimization– Technology
dependent and Independent– -Circuit level-Static, Dynamic ,PTL,DCVSL, PPL.
9 Hours
Unit IV
Low power static RAM Architectures
Organization of a static RAM, MOS static RAM memory cell, Banked organization of SRAMs,
Reducing voltage swings on bit lines, Reducing power in the write diver circuits, Reducing
power in sense amplifier circuits.
9 Hours
Unit V
Low energy computing using energy recovery techniques
Energy dissipation in transistor channel using an RC model, Energy recovery circuit design,
Designs with partially reversible logic, Supply clock generation.
9 Hours
Unit VI$
Power and energy calculations for various VLSI circuits – measurement of glitches

$
Includes Self Study topics of all 5 units and considered for Continuous Assessment only.
Total: 45+30 Hours
Reference(s)
1. K.Roy and S.C. Prasad, Low Power CMOS VLSI Circuit Design, Wiley, 2000.
2. K.S. Yeo and K.Roy, Low-Voltage, Low-Power VLSI Subsystems, Tata McGraw-Hill,
2004.
3. Dimitrios Soudris, Chirstian Pignet and Costas Goutis, Designing CMOS Circuits for
Low Power, Kluwer, 2009
4. James B. Kuo and Shin – Chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits,
John Wiley and Sons, 2001.
5. J.B Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley, 1999.
6. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer, 1997.

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