EE310

Solved Problems on MOSFETs

Sedra/Smith 5th/6th ed.

By Turki Almadhi,
EE Dept., KSU,
Riyadh, Saudi Arabia
25/07/36
 I D n  I D  p
k n W n k W
 V OV   p  p  V OV 
2 2

2 L 2 L
k n W n  k p W p , but k n  n  C ox and k p   p  C ox
  n  C ox W n   p  C ox W p ,
Wp n n
or  n W n   p W p     2.5
Wn  p 0.4 n

1 1 1
rDS     238 

k n  
W n  W n 
 V OV k n   L   V GS V t 
50  10 6
  20    5  0.8 
 Ln   n 

v DS  i D  rDS  1 103  238  238 mV

Wp W
 2.5 n  50
Lp Ln
 1 1
rDS  
k n   n  V OV k n   n   V GS V t 
W W
 Ln   Ln 
for V GS V t and very close to V t , rDS will be very large  no worries!
for V GS  5, there is a risk that rDS will fall below 1 k.
1 1
 1 k   1000
 
k n   n   V GS V t   
6    5  0.8 
W  W
100  10   n
6

 Ln   1  10 
420000 W n  1  W n  2.38  m
a)
 r (ox )   o 3.9  8.854  1012
C ox   9
 2.3  103 F/m 2  2.3  10 7 F/cm 2
t ox 15  10
k n  n  C ox  550  2.3  107  1.265  10 4 A/V 2  126.5  A/V 2
b)
k n W  k n W   126.5   16 
  v GS V t  , i D    V OV    V OV 
2 2 2
iD     100   
2 L  2 L   2   0.8 
 V OV 
2
 0.07905 V OV  0.2812V, select V OV   0.2812V
V OV V GS V t (for NMOS) V GS V OV V t  0.2812  0.7  0.9812 V
VDS (min) V DS (sat ) V OV
c)
1 1
rDS   1000   V OV  0.3953V
k n   n  V OV  16 
W 6
126.5  10    V OV
 Ln   0.8 
V GS V OV V t  0.3953  0.7  1.0953V

4.19
I D1  2 mA @ VDS 1  4 V
VGS is constant; Find ro ,  , and VA .
I D 2  2.2 mA @ VDS 2  8 V
VDS (8  4)
ro    20 k
I D (2.2  2)  103
kn W
  (VGS  Vt ) 2  (1  VDS 1 ) (1  VDS 1 )
I D1 I
 2 L  D1   (1  VDS 2 ) I D1  (1  VDS 1 ) I D 2 

I D 2 kn  W  (V  V ) 2  (1  V ) I D 2 (1  VDS 2 )
GS t DS 2
2 L
I D 2  I D1 1
  0.0278 V 1  VA   36 V
VDS 2  I D1  VDS 1  I D 2 
 4.20
VA 50 VA 50
@ I D  0.1 mA, ro    500 k @ I D  1 mA, ro    5 0 k
I D 0.1  103 I D 1  103
VDS VDS 1
ro  ,  I D   ,
I D ro 500  103
For the I D =0.1 mA case,
 I D   1  
   100   3 
 0.1 103   100  2%
 ID   500  10  
For the I D =1 mA case,
VDS 1  I   1  
I D   ,  D   100   3 
 1 103   100  2%
ro 50  10  I D 
3
 50  10  

W
k p   80  A/V 2
L
Case 1: VD  4 V,
VSG  5  0  5 V  Vt  not cutoff! VDG  4  0  4 V is not  Vt  in Triode!
  5  4 
2
W  VSD 2 
I D  k p  (VSG  Vt )  VSD  2   I D  80  10 (5  1.5 )  5  4  
6

L    2 
 1
I D  80  106 3.5    240  A
 2
Case 3: VD  0 V,
VSG  5  0  5 V  Vt  not cutoff! VDG  0  0  0 V  Vt  in Saturation!
k p
W
ID  (VSG  Vt ) 2 (1   VSD )

2 L
80  106
ID  (5  1.5 ) 2 1  0.02   5  0   I D  40  106  3.52  1.1  539  A
2
Assuming that the lower MOSFET is in saturation:
kn' W V  (5)
(V2  1) 2  2  V22  2V2  1 = V2  5
2 L 1

1  1  [4 1 (4)] 1  17
 V22  V2  4 = 0  V2 = = = 1.56 V or -2.56 V
2 1 2
We choose -2.56 V for which VGS > Vt (to avoid cutoff).
kn' W
 ID = (V2  1) 2 = 1103  (2.56  1) 2  2.433 mA.
2 L

2.56  (5)
OR I D =  2.44 mA (difference due to rounding!)
1
The upper MOSFET is in saturation because VGD  Vt (-5  1) 

kn' W
(5  V1  1) 2 = 2.44  V12  8V1  13.56  0
2 L

V1  2.44 V or 5.562 V, we choose 2.44 V for which VGS > Vt (to avoid cutoff).

To verify that the lower MOSFET is in saturation:

VGD = VG  VD  0  V1  2.44 V which is indeed  Vt  saturated as assumed.
Both MOSFET's are in saturation because VDG  0  Vt ;

Considering the upper MOSFET:

kn' W 1
ID = (10  V6  2) 2  2 = (10  V6  2) 2  V62  16V6 + 64 = 4
2 L 2

Solving for V6 by any mehod:

V6  6 V or 10 V, we choose 6 V for which VSG > Vt (to avoid cutoff).

For the lower MOSFET:

kn' W 1
ID = (6  V7  2) 2  2 = (6  V7  2) 2  V72  8V7 + 16= 4
2 L 2

Solving for V7 by any mehod:

V7  2 V or 6 V, we choose 2 V for which VSG > Vt (to avoid cutoff).

The 200- A current will divide equally between Q1 and Q 2 because
their gates are at the same potential (VGS 1 = VGS 2 ,  = 0)  I D1 = I D 2 = 100  A.

Assuming both MOSFET's are in saturation:

kn' W 100 106
I D1 = (0  V3  1)  V3  1  
2
 V3  1  0.1  1.32 V or -0.684 V
2 L 100 106  20
2
Select the first value because it implies that VGS  V t and thus I D  0 (to avoid cutoff)
Now,
V1  V2  5  0.1103  40  103  1 V.
To make sure both MOSFET's are actually in saturation, we find VGD1 and VGD 2 :

VGD1 = 0  V1  1  Vt  saturated as assumed!

VGD1 = 0  V2  1  Vt  saturated as assumed!

 Problem 4.77, page 370, 5th ed. Sedra/Smith

a) If the transistor has V t  1 V, and k n  2 mA/V 2 , verify that the bias circuit establishes
V GS  2 V, I D  1 mA and V D  7.5 V.
b) Find g m , and ro if V A  100 V.
v gs vo vo
c) Find R in , , , .
v sig v gs v sig
a)
5  10
Rth  10 M 5 M   3.34 M.
5  10
 5 
Vth     15  5 V.
 5  10 
VG  Vth (IG  0), VGS  2 (given),
VGS  VG  VS  VS  VG  VGS  Vth  VGS  3 V
VS 3
ID    1 mA
RS 3  103
VD  VDD  I D  RD  15  1  7.5  7.5 V
b)
2I D 2  1  103
gm    2  103 S
VGS  Vt 2 1
VA 100
ro    100 k
I D 1  103
c)
Let's call (RG1 RG1 )  RG = 3.34 M, and (R D RL )  RL  4.29 k
Rin  RG1 RG1  RG =3.34 M
 RG  vgs RG 3.34
vgs     vsig (VDR)     0.97 V/V
R R v R  R 3.34  0.1
 G sig  sig G sig

v
vo   g m  vgs   RL ro   o   g m   RL ro  =  2  10 3   4.29 100   8.23 V/V
vgs
vo v v
 gs  o  0.97   8.23  7.98 V/V
vsig vsig vgs