2015 ITRS 2.0 Beyond CMOS - Decrypted

INTERNATIONAL
TECHNOLOGY ROADMAP
FOR
SEMICONDUCTORS 2.0
2015 EDITION
BEYOND CMOS
THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY
COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015 i

ii THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015
TABLE OF CONTENTS
Emerging Research Devices
1. Introduction
1.1 Scope of ERD and Beyond-CMOS Focus Team
1.2 Difficult Challenges
1.3 Nano-Information Processing Taxonomy
2. Emerging Memory Devices
2.1 Taxonomy
2.2 Emerging Memory Devices
2.3 Memory Selector Devices
2.4 Storage Class Memory Devices
3. Emerging Logic and Alternative Information Processing Devices
3.1 Taxonomy
3.2 Devices for CMOS Extension
3.3 Beyond-CMOS Devices
4. Emerging Devices for More-than-Moore
4.1 Emerging Devices for Hardware Security
4.2 Emerging Devices with Learning Capabilities
4.3 Emerging Devices for Low-Power Sensor Node
5. Emerging Research Architectures
5.1 Introduction
5.2 Storage Class Memory Architectures
5.3 Emerging Computing Architectures
6. Emerging Memory and Logic Device Assessment
6.1 Introduction
6.2 Quantitative Emerging Logic Device Benchmark
6.3 Survey based Emerging Memory and Logic Device Assessment
7. Grand Challenges
8. Endnotes/References
THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

LIST OF FIGURES
Figure ERD1. Relationship of More Moore, More-than-Moore, and Beyond CMOS (Courtesy of
Japan ERD.
Figure ERD2. A Taxonomy for emerging research information processing devices (The technology
entries are representative but not comprehensive.)
Figure ERD3. Taxonomy of emerging memory devices.
Figure ERD4. Taxonomy of memory select devices.
Figure ERD5. Comparison of performance of different memory technologies.
Figure ERD6. Taxonomy of options for emerging logic devices. The devices examined in this
chapter are differentiated according to (1) whether the structure and/or materials are
conventional or novel, and (2) whether the information carrier is electron charge or
some non-charge entity. Since a conventional FET structure and material imply a
charge-based device, this classification results in a three-part taxonomy.
Figure ERD7. Two variants of learning devices for configuration.
Figure ERD8. Taxonomy for traditional and emerging models of computation.
Figure ERD9. Median delay, energy, and area of proposed devices in NRI benchmark (normalized
to ITRS 15-nm CMOS), based on principal investigators’ data. (a) 2011 benchmark
results; (b) 2010 benchmark results.
Figure ERD10. List of devices considered in Intel benchmark with their computational variables
and classification.
Figure ERD11. (a) Energy vs. delay plot of 32bit ALU built from benchmarked devices; (b) power
vs. throughput of 32bit ALU built from these devices, reflecting power-constrained
(< 10 W/cm2) throughput.
Figure ERD12. Survey of emerging memory devices in 2014 ERD Emerging Memory Workshop
(Albuquerque, NM).
Figure ERD13. Survey of emerging logic devices in 2014 ERD Emerging Logic Workshop
(Albuquerque, NM).
Figure ERD14. Comparison of emerging memory devices based on 2013 critical review.
Figure ERD15. Comparison of emerging logic devices based on 2013 critical review: (a) CMOS
extension devices; (b) Charge-based beyond-CMOS devices; (c) Non-charge-based
beyond-CMOS devices.

LIST OF TABLES
Table ERD 1 Transition Table for Emerging Research Devices

Table ERD 2 Emerging Research Devices Difficult Challenges
Table ERD 3 Current Baseline and Prototypical Memory Technologies
Table ERD 4a Emerging Research Memory Devices—Demonstrated and Projected Parameters
Table ERD 4b Emerging Research Memory Devices—Redox RAM Demonstrated and Projected
Parameters
Table ERD 5 Experimental demonstrations of vertical transistors in memory arrays
Table ERD 6 Benchmark Select Device Parameters
Table ERD 7a Experimentally demonstrated two-terminal memory select devices
Table ERD 7b Experimentally demonstrated self-selecting memory devices
Table ERD 8 Target device and system specifications for SCM
Table ERD 9 Potential of the current prototypical and emerging research memory candidates for
SCM applications
Table ERD 10a MOSFETS: Extending MOSFETs to the End of the Roadmap
Table ERD 10b Charge-Based Beyond CMOS: Non-Conventional FETs and Other Charge-Based
Information Carrier Devices
Table ERD 10c Alternative Information Processing Devices
Table ERD 11 Figure-of-merit of three reconfigurable architectures
Table ERD 12 Anticipated Important Properties of Emerging Memories as driven by application
need
Table ERD 13 Likely desirable properties of M (memory) type and S (Storage) type Storage Class
Memories
Table ERD 14 Categories of non-CMOS emerging architectures
Table ERD 15 A selection of reported measured results for implemented crossbars

Emerging Research Devices 1
EMERGING RESEARCH DEVICES

1. INTRODUCTION
1.1 SCOPE OF ERD AND BEYOND-CMOS FOCUS TEAM
Continued dimensional and functional scaling i of CMOS is driving information processing ii technology into a broadening
spectrum of new applications. Many of these applications are enabled by performance gains and/or increased complexity
realized by scaling. Because dimensional scaling of CMOS eventually will approach fundamental limits, several new
alternative information processing devices and microarchitectures for existing or new functions are being explored to
extend the historical integrated circuit scaling cadence and sustain performance gain beyond CMOS scaling. This is
driving interest in new devices for information processing and memory, new technologies for heterogeneous integration
of multiple functions (a.k.a. “More than Moore”), and new paradigms for system architecture. This chapter, therefore,
provides an ITRS perspective on emerging research device technologies and serves as a bridge between CMOS and the
realm of nanoelectronics beyond the end of CMOS dimensional and equivalent functional scaling. (Material challenges
related to emerging research devices are addressed in a complementary chapter entitled Emerging Research Materials.)
An overarching goal of this chapter is to survey, assess and catalog viable new information processing devices and system
architectures for their long-range potential, technological maturity, and to identify the scientific/technological challenges
gating their acceptance by the semiconductor industry as having acceptable risk for further development. Another goal is
to pursue long-term alternative solutions to technologies addressed in More-than-Moore (MtM) ITRS entries.
This is accomplished by addressing two technology-defining domains: 1) extending the functionality of the CMOS
platform via heterogeneous integration of new technologies, and 2) stimulating invention of new information processing
paradigms. The relationship between these domains is schematically illustrated in Figure ERD1. The expansion of the
CMOS platform by conventional dimensional and functional scaling is often called “More Moore”. The CMOS platform
can be further extended by the “More-than-Moore” approach, which was first introduced into ERD chapter in 2011. On
the other hand, new information processing devices and architectures are often called “Beyond CMOS” technologies and
have been the main subjects of this chapter. The heterogeneous integration of “Beyond CMOS”, as well as “More-than-
Moore”, into “More Moore” will extend the CMOS platform functionality to form ultimate “Extended CMOS”.
Figure ERD1 Relationship of More Moore, More-than-Moore, and Beyond CMOS (Courtesy of Japan ERD).
i
Functional Scaling: Suppose that a system has been realized to execute a specific function in a given, currently available, technology. We say that
system has been functionally scaled if the system is realized in an alternate technology such that it performs the identical function as the original system
and offers improvements in at least one of size, power, speed, or cost, and does not degrade in any of the other metrics.
ii
Information processing refers to the input, transmission, storage, manipulation or processing, and output of data. The scope of the ERD Chapter is
restricted to data or information manipulation, transmission, and storage.

2 Emerging Research Devices
The chapter is intended to provide an objective, informative resource for the constituent nanoelectronics communities
pursuing: 1) research, 2) tool development, 3) funding support, and 4) investment, each directed to developing a new
information processing technology. These communities include universities, research institutes, and industrial research
laboratories; tool suppliers; research funding agencies; and the semiconductor industry. The potential and maturity of
each emerging research device and architecture technology are reviewed and assessed to identify the most important
scientific and technological challenges that must be overcome for a candidate device or architecture to become a viable
approach.
The chapter is divided into five sections: 1) memory devices, 2) information processing or logic devices, 3) More-than-
Moore device technologies, 4) emerging research architectures, and 5) assessment of emerging memory and logic
devices. Some detail is provided for each entry regarding operation principles, advantages, technical challenges, maturity,
and current and projected performance. Also included is a device and architectural focus combining emerging research
devices offering specialized, unique functions as heterogeneous core processors integrated with a CMOS platform
technology. This represents the nearer term focus of the chapter, with the longer-term focus remaining on discovery of an
alternate information processing technology beyond digital CMOS.
The memory device section is expanded to include a new technology entry: novel STTRAM devices. “Molecular
memory” has been removed as a technology entry and included in the discussion of ultimately scaled memory devices.
“Macromolecular memory” is included in the category of ReRAM, defined by polymer-based materials. The logic device
section is organized based on state variables and novelty of materials/structures. “Piezotronic transistor” is added as a new
entry. “Atomic switch” is removed as a logic device entry but included in the discussion of CBRAM. “BisFET” and
“Excitonic FET” are removed in this version due to limited progress. The “More-than-Moore” section introduces new
discussions on devices for hardware security. Devices with learning capabilities continue to be included. Emerging
devices for RF applications are included in the discussion of low-power sensor nodes for growing applications of Internet
of Things (IoT). Finally, the critical assessment section continues to cover a survey-based benchmark and quantitative
benchmarks reported in literature to provide a balanced assessment of these emerging devices. The chapter ends with a
brief section of a set of fundamental principles that will likely govern successful extension of information processing
technology substantially beyond that attainable solely with ultimately scaled CMOS. Table ERD1 summaries the in and
out transition of emerging research devices in this chapter.
Table ERD1 Transition Table for Emerging Research Devices.
1.2 DIFFICULT CHALLENGES

1 1.2.1 Introduction
The semiconductor industry is facing three classes of difficult challenges related to extending integrated circuit
technology to new applications and to beyond the end of CMOS dimensional scaling. One class relates to propelling
CMOS beyond its ultimate density and functionality by integrating a new high-speed, high-density, and low-power
memory technology onto the CMOS platform. Another class is to extend information processing substantially beyond that
attainable by CMOS using an innovative combination of new devices, interconnect and architectural approaches for
extending CMOS and eventually inventing a new information processing platform technology. The third class is to invent
and reduce to practice long-term alternative solutions to technologies that address existing MtM ITRS topical entries.
These difficult challenges, all addressing the long-term period of 2020 – 2030, are presented in Table ERD1.

Table ERD2 Emerging Research Devices Difficult Challenges

Difficult Challenges  Summary of Issues and opportunities
SRAM and FLASH scaling in 2D will reach definite limits within the next several
years (see PIDS). These limits are driving the need for new memory
technologies to replace SRAM and FLASH memories.
Scale high-speed, dense, embeddable, volatile/nonvolatile Identify the most promising technical approach(es) to obtain electrically
memory technologies to replace SRAM and FLASH in accessible, high-speed, high-density, low-power, (preferably) embeddable
appropriate applications. volatile and nonvolatile memories.
The desired material/device properties must be maintained through and after high
temperature and corrosive chemical processing. Reliability issues should be
identified & addressed early in the technology development.
Develop 2nd generation new materials to replace silicon (or InGaAs, Ge) as an
alternate channel and source/drain to increase the saturation velocity and to
further reduce Vdd and power dissipation in MOSFETs while minimizing
leakage currents for technology scaled to 2020 and beyond.
Develop means to control the variability of critical dimensions and statistical
Extend CMOS scaling distributions (e.g., gate length, channel thickness, S/D doping concentrations,
etc.)
Accommodate the heterogeneous integration of dissimilar materials.
The desired material/device properties must be maintained through and after high
temperature and corrosive chemical processing. Reliability issues should be
identified & addressed early in this development.
Discover and reduce to practice new device technologies and primitive-level
Extend ultimately scaled CMOS as a platform technology
architecture to provide special purpose optimized functional cores (e.g.,
into new domains of application.
accelerator functions) heterogeneously integrable with CMOS.
Invent and reduce to practice a new information processing technology eventually
to replace CMOS as the performance driver.
Ensure that a new information processing technology has compatible memory
technologies and interconnect solutions.
A new information processing technology must be compatible with a system
Continue functional scaling of information processing architecture that can fully utilize the new device. Non-binary data
technology substantially beyond that attainable by representations or non-Boolean logic may be required to employ a new device
ultimately scaled CMOS. for information processing, which will drive the need for new system
architectures.
Bridge the gap that exists between materials behaviors and device functions.
Accommodate the heterogeneous integration of dissimilar materials.
Reliability issues should be identified & addressed early in the technology
development.
The industry is now faced with the increasing importance of a new trend, “More
than Moore” (MtM), where added value to devices is provided by
incorporating functionalities that do not necessarily scale according to
Invent and reduce to practice long-term alternative "Moore's Law“.
solutions to technologies that address existing MtM ITRS
Heterogeneous integration of digital and non-digital functionalities into compact
topical entries.
systems that will be the key driver for a wide variety of application fields,
such as communication, automotive, environmental control, healthcare,
security, and entertainment.
2 1.2.2 Device Technologies

Difficult challenges gating development of emerging research devices are divided into three parts: those related to
memory technologies, those related to information processing or logic devices, and those related to heterogeneous
integration of multi-functional components, a.k.a. More-than-Moore (MtM) or Functional Diversification.
One challenge is the need of a new memory technology that combines the best features of current memories in a
fabrication technology compatible with CMOS process flow and can be scaled beyond the present limits of SRAM and
FLASH. This would provide a memory device fabrication technology required for both stand-alone and embedded
memory applications. The ability of an MPU to execute programs is limited by interaction between the processor and the
memory, and scaling does not automatically solve this problem. The current evolutionary solution is to increase MPU
cache memory, thereby increasing the floor space that SRAM occupies on an MPU chip. This trend eventually leads to a
decrease of the net information throughput. In addition to auxiliary circuitry to maintain stored data, volatility of

semiconductor memory requires external storage media with slow access (e.g., magnetic hard drives, optical CD, etc.).
Therefore, development of electrically accessible non-volatile memory with high speed and high density would initiate a
revolution in computer architecture. This development would provide a significant increase in information throughput
beyond the traditional benefits of scaling when fully realized for nanoscale CMOS devices.
A related challenge is to sustain scaling of CMOS logic technology beyond 2020. One approach to continuing
performance gains as CMOS scaling matures in the next decade is to replace the strained silicon MOSFET channel (and
the source/drain) with an alternate material offering a higher potential quasi-ballistic-carrier velocity and higher mobility
than strained silicon. Candidate materials include strained Ge, SiGe, a variety of III-V compound semiconductors, and
carbon materials. Introduction of non-silicon materials into the channel and source/drain regions of an otherwise silicon
MOSFET (i.e., onto a silicon substrate) is fraught with several very difficult challenges. These challenges include
heterogeneous fabrication of high-quality (i.e., defect free) channel and source/drain materials on non-lattice matched
silicon, minimization of band-to-band tunneling in narrow bandgap channel materials, elimination of Fermi level pinning
in the channel/gate dielectric interface, and fabrication of high-κ gate dielectrics on the passivated channel materials.
Additional challenges are to sustain the required reduction in leakage currents and power dissipation in these ultimately
scaled CMOS gates and to introduce these new materials into the MOSFET while simultaneously minimizing the
increasing variations in critical dimensions and statistical fluctuations in the channel (source/drain) doping concentrations.
The industry is now addressing the increasing importance of a new trend, “More than Moore” (MtM), where added value
to devices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Law“. A MtM
section was first introduced into the ERD chapter in 2011 with the initial coverage on wireless technologies. The 2013
version added devices with learning capabilities. This version further expands the coverage to emerging devices for
hardware security. Traditionally, the ITRS has taken a “technology push” approach for roadmapping “More Moore”,
assuming the validity of Moore’s law. In the absence of such a law, different methodologies are needed to identify and
guide roadmap efforts in the MtM-domain.
A longer-term challenge is invention and reduction to practice of a manufacturable information processing technology
addressing “beyond CMOS” applications. For example, emerging research devices might be used to realize special
purpose processor cores that could be integrated with multiple CMOS CPU cores to obtain performance advantages.
These new special purpose cores may provide a particular system function much more efficiently than a digital CMOS
block, or they may offer a uniquely new function not available in a CMOS-based approach. Solutions to this challenge
beyond the end of CMOS scaling may also lead to new opportunities for such an emerging research device technology to
eventually replace the CMOS gate as a new information processing primitive element. A new information processing
technology must also be compatible with a system architecture that can fully utilize the new device. A non-binary data
representation and non-Boolean logic may be required to employ a new device for information processing. These
requirements will drive the need for new system architectures.
3 1.2.3 Materials Technologies
The most difficult challenge for Emerging Research Materials is to deliver materials with controlled properties that will
enable operation of emerging research devices in high density at the nanometer scale. To improve control of material
properties for high-density devices, research on materials synthesis must be integrated with work on new and improved
metrology and modeling. These important objectives are addressed in Emerging Research Materials.
0 1.3 NANO-INFORMATION PROCESSING TAXONOMY

Information processing systems to accomplish a specific function, in general, require several different interactive layers of
technology. The objective of this section is to carefully delineate a taxonomy of these layers to further distinguish the
scope of this chapter from that of the Emerging Research Materials chapter and the Design chapter.
One comprehensive top-down list of these layers begins with the required application or system function, leading to
system architecture, micro- or nano-architecture, circuits, devices, and materials. As shown in Figure ERD2 below, a
different bottom-up representation of this hierarchy begins with the lowest physical layer represented by a computational
state variable and ends with the highest layer represented by the architecture. In this schematic representation focused on
generic information processing at the device/circuit level, a fundamental unit of information (e.g., a bit) is represented by
a computational state variable, for example, the position of a bead in the ancient abacus calculator or the charge (or
voltage) state of a node capacitance in CMOS logic. A device provides the physical means of representing and
manipulating a computational state variable among its two or more allowed discrete states. Eventually, device concepts

may transition from simple binary switches to devices with more complex information processing functionality perhaps
with multiple fan-in and fan-out. The device is a physical structure resulting from the assemblage of a variety of materials
possessing certain desired properties obtained through exercising a set of fabrication processes. An important layer,
therefore, encompasses the various materials and processes necessary to fabricate the required device structure, which is
the domain of the ERM chapter. The data representation is how the computational state variable is encoded by the
assemblage of devices to process the bits or data. Two of the most common examples of data representation are binary
digital and continuous or analog signal. This layer is within the scope of the ERD chapter. The architecture plane
encompasses three subclasses of this taxonomy: 1) nano-architecture or the physical arrangement or assemblage of
devices to form higher level functional primitives to represent and execute a computational model, 2) the computational
model that describes the algorithm by which information is processed using the primitives, e.g., logic, arithmetic,
memory, cellular nonlinear network (CNN); and 3) the system-level architecture that describes the conceptual structure
and functional behavior of the system exercising the computational model. Subclass 1) is within the scope of the ERD
chapter, and subclasses 2) and 3) above are within the scope of the Design chapter.
The elements shown in the red-lined yellow boxes represent the current CMOS platform technology that is based on
electronic charge as a binary computational state variable. This state variable serves as the foundation for the von
Neumann computational system architecture. The other entries grouped in these five categories summarize individual
approaches that, combined in some yet to be determined highly innovative fashion, may provide a new highly scalable
information processing paradigm.
A Taxonomy for Nano Information Processing Technologies
Multicore Architecture Morphic
Von Neumann Analog Quantum
Data Representation
Digital
Analog Patterns Quantum state
Device Spintronics Quantum

Scaled CMOS
SETs Molecular Ferromagnetic
Material Carbon Strongly correlated mat’ls
Silicon Ge & III-V mat’ls Nanostructured mat’ls
State Variable Phase Spin orientation
Electric charge Molecular state Strongly correlated

electron state
Figure ERD2 A Taxonomy for emerging research information processing devices (The
technology entries are representative but not comprehensive.)

2. EMERGING MEMORY DEVICES

The emerging research memory technologies tabulated in this section are a representative sample of published research
efforts (circa 2014 – 2015) describing attractive alternative approaches to established memory technologies. iii The scope
of this section also includes updated subsections addressing the “Select Device” required for a crossbar memory
application and an updated treatment of “Storage Class Memory” (including Solid State Disks).
Figure ERD3 is a taxonomy of the prototypical and emerging memory technologies discussed in Table ERD3 and ERD4.
An overarching theme is the need to monolithically integrate each of these memory options onto a CMOS technology
platform in a seamless manner. Fabrication technologies are sought that are modifications of or additions to established
CMOS platform technologies. A goal is to provide the end user with a device that behaves similar to the familiar silicon
memory chip.
Because each of these new approaches attempts to mimic and improve on the capabilities of a present day memory
technology, key performance parameters are provided in Table ERD3 for existing baseline and prototypical memory
technologies. These parameters provide relevant benchmarks against which the current and projected performance of each
new research memory technology may be compared.
The emerging research memory technology entries in the current version of the roadmap differ in several respects from
the 2013 edition. These changes are described in the Transition Table for emerging research memory devices (Table
ERD4). Major changes are as follows. First, due to significant research activity in the area of Redox memory (ReRAM)
section has been expanded into a separate table (ERD5b) with subcategories describing four distinct device categories.
Second, Nanoelectricalmechanical Memory has been removed from Table ERD5a and an entry for Carbon memory
added. The motivations for these changes are given in Table ERD4.
This memory portion of this section is organized around a set of five technology entries shown in the column headers of
Table ERD5a and four in ERD5b. These entries were selected using a systematic survey of the literature to determine
areas of greatest worldwide research activity. Each technology entry listed has several sub-categories of devices that are
grouped together to simplify the discussion. Key parameters associated with the technologies are listed in the table. For
each parameter, three values for performance are given: 1) theoretically predicted performance values based on
calculations and early experimental demonstrations, 2) up-to-date experimental values of these performance parameters
reported in the cited technical references.
The last row in Tables ERD5a and ERD5b contains the number of papers on the particular device technology published in
the last two years. It is meant to be a gauge of the amount of research activity currently taking place in the research
community and was a primary metric in determining which of the candidate devices were included in this table. The
tables have been extensively footnoted and details may be found in the indicated references. The text associated with the
table gives a brief summary of the operating principles of each device and as well as significant scientific and
technological issues, not captured in the table, but which must be resolved to demonstrate feasibility.
The purpose of many memory systems is to store massive amounts of data, and therefore memory capacity (or memory
density) is one of the most important system parameters. In a typical memory system, the memory cells are connected to
form a two-dimensional array, and it is essential to consider the performance of memory cells in the context of this array
architecture. A memory cell in such an array can be viewed as being composed of two fundamental components: the
‘storage node’ and the ‘select device’, the latter of which allows a given memory cell in an array to be addressed for read
or write. Both components impact scaling limits for memory. For several emerging resistance-based memories, the
storage node can, in principle, be scaled down below 10 nm, 1 and the memory density will be limited by the select device.
Thus the select device represents a serious bottleneck for ReRAM scaling to 10 nm and beyond. Planar transistors (e.g.
FET or BJT) are typically used as select devices. In a two-dimensional layout using in-plane select FETs the cell layout
area is Acell=(6-8)F2. In order to reach the highest possible 2-D memory density of 4F2, a vertical select transistor can be
used. Table ERD6 shows several examples of vertical transistor approaches currently being pursued for select devices.
Another approach to obtaining a select device with a small footprint is a two-terminal nonlinear device, e.g. a diode,
either as a separate device or a strong nonlinearity intrinsic to a resistive memory element. Table ERD7 displays
iii
Including a particular approach in this section does not in any way constitute advocacy or endorsement. Conversely, not including a particular
concept in this section does not in any way constitute rejection of that approach. This listing does point out that existing research efforts are exploring a
variety of basic memory mechanisms.

benchmark parameters required for a 2-terminal select device and Table ERD8 summarizes the operating parameters for
several candidate 2-terminal select devices.
Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high
performance and robustness, with the archival capabilities and low cost per bit of conventional hard-disk magnetic
storage. Such a device requires a nonvolatile memory technology that can be manufactured at a very low cost per bit.
Table ERD9 lists a representative set of target specifications for SCM devices and systems, which are compared against
benchmark parameters offered by existing technologies (HDD, NAND Flash, and DRAM). Two columns are shown, one
for the slower S-class Storage Class Memory, and one for fast M-class SCM, as described in Section 4.1.4. These
numbers describe the performance characteristics that will likely be required from one or more emerging memory devices
in order to enable the emerging application space of Storage Class Memory. Table ERD10 illustrates the potential for
storage-class memory applications of a number of prototypical memory technologies (Table ERD3) and emerging
research memory candidates (Table ERD5). The table shows qualitative assessments across a variety of device
characteristics, based on the target system parameters from Table ERD9. These tables are discussed in more detail in
Section 4.1.4.
Table ERD3 Current Baseline and Prototypical Memory Technologies.
Table ERD4a Emerging Research Memory Devices—Demonstrated and Projected Parameters.
Table ERD4b Emerging Research Memory Devices—Redox RAM Demonstrated and Projected Parameters.
2.1 MEMORY TAXONOMY

Figure ERD3 provides a simple visual method of categorizing memory technologies. At the highest level, memory
technologies are separated by the ability to retain data without power. Nonvolatile memory offers essential use
advantages, and the degree to which non-volatility exists is measured in terms of the length of time that data can be
expected to be retained. Volatile memories also have a characteristic retention time that can vary from milliseconds to (for
practical purposes) the length of time that power remains on. Nonvolatile memory technologies are further categorized by
their maturity. Flash memory is considered the baseline nonvolatile memory because it is highly mature, well optimized,
and has a significant commercial presence. Flash memory is the benchmark against which prototypical and emerging
nonvolatile memory technologies are measured. Prototypical memory technologies are at a point of maturity where they
are commercially available (generally for niche applications), and have a large scientific, technological, and systems
knowledge base available in the literature. These prototypical technologies are covered in Table ERD3, and in the PIDS
Chapter. The focus of this section is Emerging Memory Technologies. These are the least mature memory technologies
in Fig. ERD3, but have been shown to offer significant potential benefits if various scientific and technological hurdles
can be overcome. This section provides an overview of these emerging technologies, their potential benefits, and the key
research challenges that will allow them to become viable commercial technologies.
Figure ERD3 Taxonomy of emerging memory devices

2.2 EMERGING MEMORY DEVICES
4 2.2.1 Redox Memory

The redox-based nanoionic memory operation is based on a change in resistance of a MIM structure caused by ion
(cation or anion) migration combined with redox processes involving the electrode material or the insulator material, or
both 2,3,4 . Three classes of electrically induced phenomena have been identified that involve chemical effects, i. e. effects
which relate to redox processes in the MIM cell. In these three ReRAM classes, there is a competition between thermal
and electrochemical driving forces involved in the switching mechanism. Starting in 2013, ERD has categorized these
using the type of switching (bipolar versus unipolar), metal oxide (involving oxygen vacancy motion) versus conducting
bridge (involving metal ion motion), and filamentary versus non-filamentary. Most of the literature fits into four
categories: electrochemical metallization bridge (EMB), metal oxide-bipolar filamentary (MO-BF), metal oxide-unipolar
filamentary (MO-UF), and metal oxide-bipolar nonfilamentary (MO-BN). 5
The material class for redox memory is comprised of oxides, higher chalcogenides (including glasses), semiconductors, as
well as organic compounds including polymers. In most cases, the conduction is of a filamentary nature, and hence a one-
time formation process is required before the bi-stable switching can be started. If this effect can be controlled, memories
based on this bi-stable switching process can be scaled to very small feature sizes. The switching speed is limited by the
ion transport. If the active distance over which the anions or cations move is small (in the < 10 nm regime) the switching
time can be as low as a few nanoseconds. Many of the finer details of the ReRAM switching mechanisms are still
unknown. Developing an understanding of the physical mechanisms governing switching of the redox memory is a key
challenge for this technology. Nevertheless, recent experimental demonstrations of scalability, 6 retention, 7 and
endurance 8 are encouraging.
44 2.2.1.1 Electrochemical Metallization Bridge ReRAM
Electrochemical metallization bridge (EMB) ReRAM (also referred in literature as Conductive Bridge RAM (CBRAM),
Programmable Metallization Cell (PMC), or as electrochemical metallization cells) utilizes electrochemical control of
nano-scale quantities of metal in thin dielectric films or solid electrolytes to perform the resistive switching operation. 9
The basic EMB cell is a metal–ion conductor–metal (MIM) system consisting of an electrode made of an
electrochemically active material such as Ag, Cu or Ni, an electrochemically inert electrode such as W, Ta, or Pt, and a
thin film of solid electrolyte sandwiched between both electrodes. 10 Large, non-volatile resistance changes are caused by
the oxidation and reduction of the metal ions by the application of low bias voltages. Key attributes are low voltage, low
current, rapid write and erase, good retention and endurance, and the ability for the storage cells to be physically scaled to
a few tens of nm. The material class for the dielectric film or the solid electrolyte is comprised of oxides, higher
chalcogenides (including glasses), semiconductors, as well as organic compounds including polymers.
EMB ReRAM is a strong emerging memory candidate primarily due to scalability (~10nm), 11 ultra-low energy operations
due to fast read, write and erase times, and low voltage requirements. 12 Maturity of the EMB technology development can
be assessed by the fact that many companies are either shipping products based on EMB or in advance stages of
commercialization. A recent publications show that CBRAM technology application in various markets including
SSDs, 13 embedded NVM, 14 and serial interface nonvolatile memory replacement. 15 In 2012, an EMB based serial NVM
replacement product became commercially available. 16 In 2014, a 16 GB ReRAM array based on a CuTe EMB cell was
demonstrated. 17,18 Such efforts are critical to identify core technology challenges 19 and also on fundamental materials and
mechanisms. 20 Novel applications such as reconfigurable switch 21 and synaptic elements in Neuromorphic systems 22
based on EMB ReRAM are also gaining prominence and are expected to expand the application base for this technology.
As with other filamentary ReRAM technologies, EMB ReRAM is challenged by bit level variability, 19 the random nature
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of reliability failure such as retention or endurance and random telegraph noise potentially contributing to read disturbs. 23
Such issues require large populations of bits to be studied, which suggests collaboration between universities and industry
may be beneficial. Focus on fundamental understanding and simultaneously addressing some mitigation path such as
error correction schemes, redundancy and algorithm development would enable closing the technology gap.
Engineering hurdles include the availability and integration of new materials used in EMB ReRAM at advanced process
nodes especially when there could be issues with compatibility of thermal budgets and process tooling. The availability of
integrated array level information suggests that some of these challenges are being resolved in the recent years 15 , 21 .
X X X X
Active participation from semiconductor equipment vendors and material suppliers would assist overcoming
manufacturing hurdles rapidly.

45 2.2.1.2 Metal Oxide-Bipolar Filamentary ReRAM

Metal oxide-bipolar filamentary (MO-BF) ReRAM operates on valence change mechanism of the dielectrics, or redox
reaction of the dielectrics between electrodes. 24,25 It typically consists of one or a few layers of insulating materials 26 (i.e.
oxide AlOx, HfOx, TaOx, TiOx, WOx, ZrOx, oxynitrides AlOxNy, or nitrides including AlNx and CuNx) sandwiched by two
different electrodes. The electrode with relatively active metal interacts with dielectric material to generate vacancies of
the anions (oxygen or nitrogen etc.) under fabrication or electroforming processes. 27 The counter electrode is typically
inert to provide an electrical contact and form a relatively high electronic barrier at the interface (e.g. Schottky-like
barrier) 28 . Among the mentioned material systems, TaOx and HfOx are still the leading candidates of this category due to
their overall superior performance and CMOS.
Most MO-BF switches require a one-time electroforming process to establish a filament linking both electrodes. The
subsequent switching, operated at significantly smaller voltages, is believed to rupture and recover a portion of the
filament in the vicinity of the inert metal electrodes. 29 The electroforming is an electrochemical process of reduction of
the oxide or nitride dielectrics. 27 ,30 A thinner dielectric layer combined with a anion scavenging layer is typically adopted
X X
to mitigate the electroforming process and obtain electroforming-free devices. 27 X X
Since the demonstration of a single crossline HfOx devices with a 10 nm dimension in 2011 31 , scaling to a smaller size
was achieved by employing a sidewall electrode in a 1×3 nm2 cross-sectional HfOx-based MO-BF device with reasonable
performance in terms of both endurance and retention. 32 In terms of repeatability, up to 1012 cycles has been demonstrated
with Zr:SiOx sandwiched by graphene oxide layers recently. 33 This is comparable to the previous endurance record with a
Ta2O5-x/TaO2-x structure developed in 2011. 34 The fastest MO-BF was demonstrated on a TaOx device with a programing
duration about 100 ps in 2011. 35 Remarkable progress has been made on improvement of the MO-BF reliability,
especially for TaOx. Extrapolated retention at 85°C by stressing TaOx in the temperature range from 300°C to 360°C is
estimated to be 5×105 years with an activation energy of 1.6 eV. 36
Unconventional electrodes (e.g., graphene, carbon nanotube) have been utilized for RRAM, e.g., graphene electrode on
HfOx-based RRAM with low write/erase energy of ~230 fJ/bit 37 , graphene/CNT edge electrodes on bi-layer Ta2O5-x/TaOy
RRAM in a 3D array to explore the limit of RRAM cell size 38 . Notice that carbon nanotube biased AlOx MO-BF device
has exhibited even lower write/erase energy per transition in the ranging from 0.1 to10 fJ per bit. 39
Large-scale integration of MO-BF switching based on 1T1R schemes has been reported. In 2013, a 32Gb RRAM test chip
has been demonstrated using 24 nm CMOS process. 40 An encapsulated cell structure with an Ir/Ta2O5/TaOx/TaN stack
was implemented in a 2-Mbit chip at 40nm node in 2014. A 16Mb array of HfOx/TaOx bi-layer RRAM with built-in
verification function and a capacitive surge current reduction circuit was also reported in 2015 41 . In addition, passive
integration of 1S1R scheme has been reported by Crossbar on a 4-Mbit chip but the material stack of the MO-BF switch
was not revealed. 42
Despite the significant advancement of MO-BF ReRAM, there are still a number of technical challenges for
commercialization with those MO-BF ReRAM. The current for switching normally reported is still a bit too high for MO-
BF devices. In addition, the variability of switching parameters (i.e. switching voltages, resistance distributions) is
associated with the stochastic nature of the filament formation and rapture, which has a negative impact on applications
like multilevel cell memory. But on the other hand, such variability of switching processes provides a way to realize
stochastic learning rule. Moreover, passive integration of MO-BF switches requires either external selecting devices or
built-in IV nonlinearity. An ideal external selecting device with good scalability, fast sweep, suitable operation current,
and good ON/OFF ratio still remains to be demonstrated.
46 2.2.1.3 Metal Oxide-Unipolar Filamentary ReRAM
Metal Oxide - Unipolar filamentary (MO-UF) ReRAM is another resistive switching device, also referred to in the
literature as thermochemical memory (TCM) 2 due to its primary switching mechanism. The device structure is consists
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of a top electrode metal/insulator/bottom electrode metal (MIM) structure. Typical insulator materials are metal-oxides
such as NiOx, HfOx, etc., and common metal electrodes include TiN, Pt, Ni, and W. In general, the device can be
asymmetric (i.e. top electrode material differs from bottom electrode material), but unlike other types of ReRAM,
asymmetry is not required.
The first reported resistive switching in these MIM structures was unipolar in nature (see reference 43 for the first
integrated device work that put metal oxide ReRAM in the spotlight). Unipolar is defined as switching where the same
polarity of voltage has to be applied for changing the resistance from high to low (SET) or from low to high (RESET).
Note that in the general case, polarity is still important (e.g. repeatable SET/RESET switching only occurs for one

polarity of voltage with respect to one of the electrodes 44 ). Only in symmetric structures (e.g. Pt/HfO2/Pt), a-polar
behavior can be obtained, where SET and RESET are occurring irrespective of voltage polarity 45 .
The switching process is generally understood as being filamentary, where conduction is caused by a filamentary
arrangement of defects (oxygen vacancies) throughout the thickness of the insulator film. As with other filamentary
ReRAM, an initial high voltage “forming” step is required to form this conductive filament, while subsequent
RESET/SET switching is thought to occur through local breaking/restoration of this conductive path.
The unipolar character of the switching indicates that drift (of charged defects) in an electric field does not play a role (as
it does in bipolar switching resistive memory), but that thermal effects probably dominate. 46,47 On the other hand, polarity
effects indicate anodic oxidation (e.g. at Ni or Pt electrodes) is responsible for RESET. 44 These findings suggest a
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thermo-chemical “fuse” model for describing this unipolar switching. It has been shown for different MIM structures that
both unipolar and bipolar switching mechanisms can be induced, depending on the operation conditions. 48,49,50,51 An
interesting work reporting on the Scaling Effect on Unipolar and Bipolar Resistive Switching of Metal Oxides was
recently published 52 .
A unipolar switching device is seen as advantageous for making scaled memory arrays, as it enables the use of simple
selector devices as a diode that can be stacked vertically with the memory device in a dense crossbar array 43 . Also, the
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use of a single program voltage polarity greatly simplifies the circuitry.

On the other hand, as has been exemplified in mixed mode (unipolar/bipolar) operation of memory cells, there are
important trade-offs between the unipolar and bipolar switching modes. On the plus side, unipolar switching mode
typically shows a higher on/off resistance ratio. On the minus side, unipolar switching is typically obtained at higher
switching power (higher currents) than the bipolar mode, and also endurance is much more limited. As a result, major
research and development work on resistive memories has shifted towards bipolar switching mechanisms. Yet, some
interesting recent development work is reported in references 53 , 54 , 55 , 56 , 57 , and 58 . Reference 53 shows an endurance of
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over 106 cycles with a resistive window of over 5 orders of magnitude (and a reset current ~1mA). References 54 , 55 , andX X X X
56 demonstrate how unipolar RRAM elements can be integrated in a very simple way in an existing CMOS process
X X
(known as Contact ReRAM technology). This may provide a very inexpensive embedded ReRAM technology. Recently,
integration unipolar ReRAM with a 29 nm CMOS process was reported. 56 The key attributes were a small cell size (0.03
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µm2), switching voltage of less than 3V, RESET current of less than 60 µA, endurance > 106 cycles, and short SET and
RESET times of 500 ns and 100 µs, respectively. Reference 57 shows 4Mb array data using this same Contact-RRAM
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technology, fabricated using a 65 nm CMOS process. To accommodate for the low logic VDD process, on-chip charge
pump was applied. Set and reset voltages are less than 2V. Reference 58 reports on a novel approach using thermal
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assisted switching to lower the switching current.

As stated above, large on to off resistance ratio are an attribute of unipolar switching. The low resistance window and
large intrinsic variability of bipolar switching ReRAM may require complex and time consuming verify schemes. Further
study of the stability and control of the large resistance window (at low current levels), is required to determine if unipolar
ReRAM variability can be improved, potentially even allowing for multi-level cell operation.
Major challenges to be resolved are the high switching current that seems inherently to the unipolar operation mode. As
shown in references 54 , 55 ,and 56 , reset currents less than 100 µA are achieved but need further reduction to less than 10
X X X X X X
µA. Recently, a possible solution incorporating thermally assisted switching has been presented. 58 X
47 2.2.1.4 Metal Oxide-Bipolar Non-Filamentary ReRAM

The Bipolar Non-Filamentary ReRAM is a non-volatile bipolar resistive switching device composed of one or more
oxide layers. One layer is a conductive metal oxide (CMO), which is usually a perovskite such as PrCaMnO3 or
Nb:SrTiO3. 59 In contrast to Unipolar and Bipolar Filamentary ReRAM devices – typically based on binary oxides such
as TiOx, NiOx, HfOx, TaOx or combinations thereof – the resistance change effect of the Bipolar Non-Filamentary
ReRAM is uniform. Depending on materials choice and structure the current is conducted across the entire electrode area,
or at least across the majority of this area. A forming step to create a conductive filament is not needed. Non-volatile
memory functionality is achieved by the field-driven redistribution of oxygen vacancies close to the contact resulting in a
change of the electronic transport properties of the interface (e.g. by modifying the Schottky barrier height). Oxygen can
be exchanged between layers due to the exponential increase in ion mobility with field at high fields. Low current
densities, uniform conduction, and bipolar switching imply that substantial self-heating is not involved. Typical ROFF to
RON ratios are on the order of 10.

One class of the Bipolar Non-Filamentary ReRAM includes a deposited ion conductive tunnel layer (Tunnel ReRAM),
e.g. ZrO2. Here, a redistribution of oxygen vacancies causes a change of the electronic transport properties of the tunnel
barrier. Low current densities and area scaling of device currents enable ultra-high density memory applications. Set,
reset, and read currents scale with device area. In addition set, reset, and write currents are controlled by the tunnel oxide
and hence, can be adjusted by changing the tunnel barrier thickness. Both set and reset IV characteristics are highly
nonlinear enabling true 1R cross-point architectures without the need for an additional selector device for asymmetric
arrays up to 512x4096 bit. No external circuitry is needed for current control during set operation. A continuous transition
between on and off state allow straightforward multi-level programming without the need for precise current control.
The typical thickness of the CMO is greater than 5 nm and the tunnel barrier is typically 2-3 nm. If a tunnel barrier is
present, the adjacent electrode has to be an inert metal such as Pt to prevent oxidation during operation. For the case of
PCMO cell, low deposition temperatures less than 425 °C of all layers enables back end integration schemes.
Currently the technology is in the R&D stage. Depending on material system and structure cycling endurance over 10,000
cycles and up to a billion cycles as well as data retention from days to months at 70 °C has been achieved on single
devices. 60,61,62 Within the Bipolar Non-Filamentary RRAM device family the Tunnel RRAM is probably the furthest
developed technology. Single device functionality is demonstrated down to 30nm. Set, reset, and read currents scale with
area and tunnel oxide thickness facilitating sub µA switching currents with read currents in the order of a few nA to a few
100 nA. BEOL integration schemes and CMOS/RRAM functionality are verified for 200nm devices on 200mm CMOS
wafers. True cross-point array (1R) functionality utilizing the self-selecting non-linear device IV characteristics and
transistor-less array operation is demonstrated on fully decoded 4kb true cross-point arrays (1R) build on top of CMOS
base wafers. SLC and MLC operations are demonstrated within 4kb arrays.
Major challenges to be resolved towards the commercialization of Bipolar Non-filamentary RRAM are, in order of
priority, a) improvement of data retention, b) the integration of conductive metal oxide layer (perosvkites) via ALD or the
replacement of CMO by more process friendly materials, and c) the replacement of Pt electrodes by a non-reactive more
process friendly electrode material.
The most important issue is the improvement of retention and the “voltage-time dilemma.” This dilemma hypothesizes
physical reasons as to why it is difficult in a particular device and material system to simultaneously obtain a long
retention, with short low read voltages, and fast switching at moderate write voltages. 63 Even though the exact
mechanism is still under investigation there is a common agreement that oxygen vacancies are moved by the external
electric field resulting in different resistance states of the memory cell. Vacancy drift at room temperature is possible due
to a field dependent mobility, which increases exponentially with field at fields of 1 MV/cm and larger. However, current
models based on a field dependent mobility underestimate the experimentally observed ratio between set/reset times and
data retention indicating that the mechanism is only partly understood. More theoretical work is needed to understand the
kinetics of programming and retention mechanisms. Once understood, materials have to be chosen to maximize the ratio
between set/reset and retention times. Goal is to set/reset devices at low temperatures and meet retention requirement of
10 years at 70°C, 85°C, and 125°C, depending on the application.
Memory cells with a conductive perovskites as an electrode have proven to show excellent device-to-device and wafer-to-
wafer reproducibility with yields close to 100%. One of the reasons might be that perovskites display high oxygen
vacancy mobilities and tolerate large variations in the oxygen content while maintaining its crystal structure. From an
integration perspective, ALD is the method of choice for advanced technology nodes and future 3D integration schemes.
Key issues are the control of the metals ratio (perovskites are ternary or quaternary oxides), the control of the oxygen
stroichiometry in the cell, oxygen loss in the presence of reducing atmospheres like H2, as well as high temperatures
required for crystallization. Eventually a migration to binary oxides with comparable properties might be required to
resolve the integration challenges.
Platinum or other noble electrodes display superior device performance over fab friendly electrodes like TiN. On the one
hand it was observed that the oxidation resistance of TiN is not sufficient to prevent oxidation and the formation of TiO2
during operation. On the other hand, inert electrodes such as Pt or Pt-like metals are difficult to integrate. New oxidation
resistant electrodes and Pt alternatives are required to reduce integration challenges and enable 3D integration schemes.
48 2.2.1.5 Macromolecular (Polymer) ReRAM
Macromolecular, also referred to as polymer ReRAM is a subcategory of redox RAM which focuses structures
incorporating a layer of polymer. Via the two terminals, the resistance of the memory is modified and also read-out, using
pulsed voltage. The polymers contain mainly carbon atoms and are largely amorphous. Non-volatile memory effects with

a non-destructive read have been reported for a surprisingly large variety of polymeric materials and blends of polymers
with nanoparticles. Unlike the other four categories, this category is based on the material used in the switching layer(s)
of the cell, but the mechanism in not specificed. Both bipolar and unipolar (all pulses of the same polarity) switching have
been demonstrated. Macromolecular ReRAM may have a mechanism placing it in one of the four main ReRAM
categories listed above. For this reason, macromolecular ReRAM is not tracked in the ERD 4 Tables.
Depending on the structure of the polymer, a variety of mechanism can be operative. For polymers supporting transport of
inorganic ions formation of metallic filaments is reported. In semiconducting polymers supporting ion transport, dynamic
doping due to migration of inorganic ions occurs. Ferroelectric polymers in blends with semiconducting material give rise
to a memory effect based modification of charge injection barriers by the ferroelectric polarization. However, for many
polymeric materials, the origin of the resistive switching is not well understood. To date no specific design criteria for the
polymer are known, although clear correlations between memory effect and electronic properties of the polymer have
been demonstrated. A number of studies have indicated the importance of certain interfaces and interlayers of the
polymers with other conducting and semiconducting materials. In some cases, the mechanism and its relation between
polymer structure seems obvious, but in many cases the mechanism of operation is largely unknown. In summary the
macromolecular memory category encompasses a large variety of mechanisms.
Stability of the memory states at high temperatures (85oC, 2  104 s) has been demonstrated. 64,65 Programming at very
low power (70 nW) has been realized. 65 Assuming a 15 ns switching time determined for the same system, one might
X X
acheive a write energy of 6  10-15 J/bit. Furthermore low programming voltages have been realized: +1.4 and -1.3 V for
the two states with good retention time (>104 s) 66 . Downscaling of polymer resistive memory cell to the 100 nm length
scale has been reported. 67 At this length scale, integration of memory cells into an 8  8 array could be shown. Polymer
memory cells on flexible substrate have been shown. 68 For amorphous carbon, downscaling to nanometer sized cell has
been published (1  103 nm2 69 ). Using carbon nanotubes as macromolecular electrodes and aluminum oxide as interlayer,
isolated, non-volatile, rewriteable memory cells with an active area of essentially 36 nm2 have been achieved, requiring a
switching power less than 100 nW, with estimated switching energies below 10 fJ per bit. 70 With regards to the
mechanism of operation, extensive work on the class of polyimide polymers has shown clear correlations between
electronic structure of the polymer and memory effects, although a no comprehensive picture for the operation has yet
emerged. A number of studies have indicated an active role of the interface between macromolecular material and
(native) oxide layers in the operation of the memory involving charge trapping. 71,72
In macromolecular memory, a large variety of operation mechanisms can be operative. A key research question concerns
distinguishing different mechanisms and evaluating the potential and possibilities of each mechanism. A second
subsequent step would be to identify model systems for each mechanism. Having such a model system then provides a
possibility to benchmarking the operation of the macromolecular materials. These research steps would be crucial for
establishing and securing the collaboration of chemical industry; for design, synthesis and development of the next
generation macromolecular materials for memory applications, clear guidelines on the required structural and electronic
properties of the macromolecular material are needed. For instance, memory effect originating for metallization and
formation of metallic filaments requires macromolecular materials that support transport of ions and have appropriate
internal free volume for ion conduction. Here the field could benefit from interaction with the field of polymer batteries.
Ferroelectric polymers have been shown to give rise to resistive memory 73 and could benefit enormously from
development of new macromolecular polymeric materials with combined ferroelectric switching and semiconducting
structural units. Finally, a number of macromolecular memories involve oxide layers. Here mutually beneficial interaction
with the (research) community on metal oxide ReRAM switching could spring, because at the macromolecular / oxide
interface trap states can be engineered by tuning the electron levels of the macromolecular material.
5 2.2.2 Ferroelectric Memory
Coding digital memory states by the electrically alterable polarization direction of ferroelectrics has been successfully
implemented and commercialized in capacitor-based Ferroelectric Random Access Memory (covered in the PIDS section
and Table ERD3). However, in this technology the identification of the memory state requires a destructive read operation
and largely depends on the total polarization charge on a ferroelectric capacitor, which in terms of lateral dimensions is
expected to shrink with every new technology node. In contrast to that, alternative device concepts, such as the
ferroelectric field effect transistor (FeFET) and the ferroelectric tunnel junction (FTJ), allow for a non-destructive
detection of the memory state and promise improved scalability of the memory cell. Current status and key challenges of
these emerging ferroelectric memories will be assessed within this section.

49 2.2.2.1 Ferroelectric FET

The FeFET is best described as a conventional MISFET that contains a ferroelectric oxide in addition to or instead of the
commonly utilized SiOx, SiON or HfO2 insulators. The former case requires the direct and preferably epitaxial contact of
the ferroelectric to the semiconductor channel (metal-ferroelectric-semiconductor-FET, MFSFET), whereas the latter and
commonly applied case maintains a buffer layer between the channel material and the ferroelectric (metal-ferroelectric-
insulator-semiconductor-FET, MFISFET). When additionally introducing a floating gate in-between the buffer layer and
the ferroelectric, a metal-ferroelectric-metal-insulator-semiconductor structure (MFMISFET) may be obtained that shares
its equivalent circuit representation with the MFISFET approach. By applying a sufficiently high voltage pulse to the gate
of the FeFET (i.e. voltage drop across the ferroelectric layer larger than its coercive voltage Vc) the polarization direction
of the ferroelectric can be set to either assist in the inversion of the channel or to enhance its accumulation state. This
results in a polarization dependent shift of the threshold voltage VT, which allows for a non-destructive read operation and
a 1T memory operation comparable to that of FLASH devices.
In order to assess the material and device requirements for a reliable and scalable FeFET technology the following two
intrinsic relations in a ferroelectric gate stack need to be considered. First it is important to note that the extent of the
aforementioned VT-shift (memory window) in FeFET devices is primarily determined by the VC of the implemented
ferroelectric rather than by its remanent polarization Pr 74 . This results in a scaling versus memory window trade-off as Vc
is proportional to the coercive field Ec and thickness dFE of the ferroelectric. The inability of the commonly utilized
perovskite-based FeFETs to laterally scale beyond the 180 nm node is therewith not solely based on the insufficient
thickness scaling of perovskite ferroelectrics 75,76 , but rather due to their low Ec (SBT: 10-100 kV/cm, PZT: ~50 kV/cm,
summarized in 77 ) that in order to maintain a reasonable memory window requires compensation by a large dFE. A solution
to this scaling retardation is provided by the high coercive field (1-2 MV/cm) and thickness scalable FE-HfO2 78 . This
CMOS-compatible material innovation enabled the demonstration of a FeFET technology scaled to the 28 nm node
utilizing a conventional HKMG technology already used in high volume production 79 . The close resemblance of the
HKMG transistor and the FE-HfO2-based memory transistor proves especially useful for the realization of an embedded
memory solution with greatly reduced mask counts as compared to embedded FLASH.
The second noteworthy and important characteristic of the FeFET gate stack is related to its intrinsic capacitive voltage
divider, which causes a significant gate voltage drop and buildup of electric field not only across the ferroelectric, but also
across the non-ferroelectric insulator in the gate stack. When additionally considering the incapability of the linear
insulator to fully compensate the polarization charge of the ferroelectric layer, it becomes apparent that even in the case of
no external biasing the capacitive voltage divider leads to a buildup of a permanent electric field. The so called
depolarization field building up in the ferroelectric is opposed to the polarization direction of the ferroelectric and to the
electric field induced in the insulator 80 . The capacitive voltage divider is therefore directly responsible for the retention
loss during stand-by as well as for the gate voltage distribution and the corresponding charge injection during write
operations. This retention and endurance critical distribution of the electric field within the gate stack may be optimized
by choosing the insulator capacitance as high as possible and the ferroelectric capacitance as low as possible. In the
perovskite-based FeFET this is achieved by utilizing high-k buffer layers and is additionally fostered by the unavoidably
large physical thickness of the perovskite ferroelectrics 81 . In the case of the aggressively scaled FE-HfO2-based FeFET,
the small thickness of the ferroelectric is compensated by the comparably low permittivity of HfO2 and the possibility to
use ultra-thin interfacial layers as well as by the depolarization resilience of the high Ec 77 ,82 . This leads to the situation
X X
that despite the markedly different stack dimensions and materials used, the electrically obtained characteristics are quite
similar. Fast switching speed (≤100 ns), switching voltages in the range of 4-6 V, 10-year data retention and endurance in
the range of 1012 switching cycles have been demonstrated for FE-HfO2- 78 , 79 ,83,84 as well as for perovskite-based
X X X X
FeFETs 81 ,85,86 . In the case of cycling endurance, however, the high Ec of FE-HfO2 and the correspondingly large electric
X X
field in the insulator facilitates charge trapping during write operation, which was identified as the root cause for the
limited endurance of 105 cycles observed in FE-HfO2-based FeFETs with ultra-thin interfacial layer enabling excellent
data retention 87 . Nevertheless, in an alternative approach utilizing a thicker insulator and sub-loop operation it was
demonstrated that at the cost of retention a cycling endurance >1012 may still be obtained 83 . In the current stage of
X X
development this endurance versus retention trade-off may be tailored spanning the application range from embedded
NOR-FLASH replacement with high retention requirements to low refresh rate 1T DRAM requiring high cycling
endurance.
Entirely overcoming this endurance versus retention trade-off will require an improved stack design that may include a
tailored polarization hysteresis (low Pr and high Pr/Ps ratio) 74 , a reduced trap density at the interfaces 87 , an optimized
X X X X
capacitive voltage divider by area scaling in the MFMISFET approach 88 or the realization of a MFSFET device by

implementing recent breakthroughs in the epitaxial growth of FE-HfO2 89 . Despite promising results obtained for
perovskite-based FeFET devices implemented into 64Kb NAND-Arrays at a feature size of 5 µm 86 , little is known about
X X
the variability and array characteristics of FeFET devices scaled to technology nodes approaching the grain or domain
size of the implemented ferroelectrics. Most recently first data showing a clear low and high VT separation in a sub-kB
FE-HfO2-based FeFET array with LG: 34 nm nm has been demonstrated 90 . Nevertheless, in order to fully judge the
variability of ferroelectric phase stability at the nanoscale and to guide material optimization and fundamental
understanding of the phenomenon, larger array statistics in the kB to Mb range and high resolution PFM data will be
required.
2.2.2.2 Ferroelectric Tunnel Junction
The ferroelectric tunnel junction, a ferroelectric ultra-thin film commonly sandwiched by asymmetric electrodes and/or
interfaces, exhibits ferroelectric polarization induced resistive switching by a non-volatile modulation of barrier height.
With the tunneling current depending exponentially on the barrier height, the ferroelectric dipole orientation either codes
for a high or a low resistance state in the FTJ, which can be read out non-destructively. The resulting tunneling
electroresistance (TER) effect of FTJs, the ratio between HRS and LRS, is usually in the range of 10 to 100 ( 91 and
references therein). However, giant TER of > 104 has most recently been reported in a super-tetragonal BiFeO3 based FTJ
by Yamada et al. 92 . A similarly high TER was demonstrated by Wen and co-workers 93 for a BaTiO3 tunnel barrier by
replacing one metal electrode of the FTJ with a semiconducting electrode. With this new junction design the modulation
of tunneling current does not only rely on barrier height, but due to a variable space charge region in the semiconductor,
also on a barrier width modification. With these most recent findings, two strategies to achieve giant TER have been
identified: either use a ferroelectric barrier with a large polarization such as BiFeO3 or use a semiconductor as electrode
material to modulate the barrier width by field-induced carrier depletion.
The MFM-based structure of FTJs may be able to enable a retention time (> 10 years) and very high cycling endurance (>
1014) properties of conventional FRAM. Nonetheless, in order to have a significant tunneling current, ferroelectric films
in FTJs usually have a thickness ranging from several unit cells to ~5 nm, which is much thinner than in commercialized
1T-1C FRAM (> 50 nm). Due to larger interface contributions and increased leakage currents at reduced thickness,
experimental data of these material systems might strongly deviate from their thick film behavior and need to be assessed
separately 94 . However, even though only limited data are available up to this point, promising single cell characteristics
have already been demonstrated, such as the most recent demonstration of 4x106 endurance cycles and extrapolated data
retention of 10 years at room temperature for a BiFeO3-based FTJ 95 . In the context of retention it should be noted that
despite improved TER, the newly proposed MFS-FTJ structure will give rise to a depolarization field, which will most
likely degrade memory retention in a similar manner as described for the FeFET in section 5.2.2.1. The highly energy
efficient electric field switching, common to all ferroelectric memories, enables fast (10 ns 96 ) and low voltage (1.4 V 95 )
X X
switching in FTJ devices and results in a minimal power consumption during write operation (1.4 fJ/bit, calculation based
on the device characteristics given 97 ). Due to the availability of non-destructive read-out and the further reduced
ferroelectric thickness in FTJ devices as compared to conventional FRAM, improved voltage scaling and total energy
consumption may be expected from this technology.
Similar like for most other two-terminal resistor based memories with insufficient self-rectification, the elimination of
sneak currents in large crossbar arrays is most efficiently suppressed utilizing 1T-1R or 1D-1R cell architecture. In terms
of scaling, this two-element memory cell, as well as the scalability of the selector device itself, has to be considered 98 .
Simply based on the lateral dimensions of the FTJ element (assuming unlimited scalability of the selector), scaling below
50 nm2 97 and based on PFM data 99 most likely beyond appears possible. However, with further scaling a simultaneous
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enhancement of the LRS current density is required to maintain readability in massively parallel memory architectures. A
recent breakthrough of 1.4x105 A/cm² current density at 300 nm feature size has been achieved by Bruno et al. 100 utilizing
low resistivity nickelate electrodes. Based on these results maintaining 10 µA read current for feature sizes <100 nm
appears possible.
FTJ based memories are currently at a very early development stage. Further investigations reaching beyond single device
characterization will be needed to fully judge the scalability of FTJ as well as its MLC capability suggested in 101 . So far
no conclusions can be drawn on retention and statistical distribution of the polarization induced resistance states in large
arrays. However, when considering the collective phenomenon of ferroelectricity with multiple dipoles contributing to a
resistance change as opposed to filament-type resistive switching, advanced scalability may be expected. First results
have shown that the FTJ is very similar to ReRAM in terms of electrical behavior and memory design, albeit distinct
physical mechanisms. It should be noted that current prototypes could actually have both FTJ and ReRAM traits, as
resistive switching is common among oxides including ferroelectric perovskites ( 102 and references therein). For future

development, the ferroelectric film in an ideal FTJ should be as thin as possible to allow scalability (while maintaining
sufficient read current) as well as much less defective than that in ReRAM (e.g., with less oxygen vacancies), so that the
mechanism of ferroelectric switching can dominate electrical behavior with little influences from mechanisms related to
conducting filaments. The manufacturability of the rather complex electrode-ferroelectric-system of the FTJ concept will
largely rely on the availability of high throughput and CMOS-compatible epitaxial growth techniques for large substrates
or alternatively on the unrestricted feasibility demonstration of a polycrystalline FTJ. However, polycrystalline
ferroelectrics, unless very thin, tend to have other leakage current contributions overwhelming the desired tunneling
current as well as an increased variability of FE-properties at the nanoscale. In this context it is worth noting that the
CMOS-compatibility and advanced thickness scalability of FE-HfO2 84 as well as recent breakthroughs in its epitaxial
X X
growth 89 , might yield great potential for the manufacturability of competitive FTJs.
X X
6 2.2.3 Carbon Based Memory

Recently, various allotropes of carbon, such as amorphous carbon (α-C) and diamond-like (DLC) carbon, carbon
nanotubes and graphenic carbon were explored for memory applications 103 . The device structure consists of an
electrode/carbon/electrode capacitor structure, whose resistance can be changed by appropriate current pulses. One of the
proposed switching mechanism is creation and destruction of conductive sp2-bonds in an otherwise insulating carbon
matrix consisting of sp3-bonds 104 . Another switching mechanism is creation and closing of nanogaps. This can occur in
low mass density carbon, like carbon nanotube ribbons or foams and in open systems like graphene or graphitic break-
junctions which are operated in air or even vacuum 105 . In both cases the structures are not embedded by a protecting
insulating layer but are held in air or in a vacuum, like a probe chamber, SEM or TEM. Even an unknown atmosphere is
possible for integrated memory cells produced by the encapsulation process. By applying a high enough current density, a
nanogap is created by evaporating carbon into the vacuum or hollow structure of the low density carbon material. Joule
heating originating from the field emission current in the nanogap will cause atom diffusion and rearrangement of carbon,
eventually supported by trapping of hydrocarbons from ubiquitous gas background contamination 105 . Recent Raman X X
studies support the creation of carbon chains in the gap region 106,107 .
Not considered here as carbon-based memories are experiments, which are diffusing oxygen or metal ions through
insulating phases of carbon 108 or graphene oxide 109 to form a redox-based resistive memory 105 . X X
Recently reported unipolar switching in 22 nm thick DLC relies on single cells with 360 nm diameter 104 . The SET pulse X X
was 50 ns for 1.2V and pulses smaller than 25 ns at 0.4 V were needed for RESET. ON resistance varied between 2 kΩ -
10 kΩ. Switching currents, retention and endurance were not reported. Scaling of the cell diameter to 120 nm and SET
voltage scaling to 0.8 V by reducing the DLC thickness to 16 nm has been demonstrated 110 . Unipolar switching has also
been reported in single cells with 18 nm thick a-C:H films with cell diameters of 49 nm 111 . The FORMING voltage was
4V, SET pulses were 30 ns 4 V, and RESET was achieved after 5 ns at 4 V. ON resistance were around 10 kΩ , OFF to
ON resistance ratio was 1000, 15 cycles and 16 hours retention have been demonstrated. For nanogap-based cells, the
most advanced demonstration features a 4 Mbit chip established with carbon nanotube ribbons (NRAM) 112,113 , where 108
write cycles in bipolar mode have been demonstrated on 256 bytes 113 with 114nm bottom electrode, but operating
X X
voltages and currents were not disclosed. On individual cells, with external transistors as current limiter, an endurance of
1012 write cycles with 20 ns pulses of 3.5 V for RESET and −2.4 V for SET have been demonstrated 114,115 . Data
retention has been demonstrated with a 168 hours 250°C bake 116 , again on different samples.
Memory cells integrated with on-chip transistors for current compliance need to be employed to study DLC a-C, and a-
C:H based memory cells further and demonstrate the scalability to low current operation. It has already be shown that the
reset pulse needs to be extremely short (<20 ns) not to induce strengthening of the filament 104 , 111 . The voltage drop on the
X X X X
bitline will collapse during a successful RESET in arrays, leaving the cell in the OFF-state with a much higher bias
voltage, which could induce a SET operation again. The complete history of FORMING, SET, RESET voltages and
currents needs to be revealed in the case of NRAM cells. Nothing is known about the virgin cell state after fabrication and
whether the first operation is a SET or a RESET and how much current it will take. The origin of the bipolar operation of
the NRAM cell needs to be investigated, especially in the context that water and acid-based spin-on deposition of CNTs
can induce to the formation of WOx on the tungsten plug.
7 2.2.4 Mott Memory
Mott memory is a metal/insulator/metal capacitor structure consisting of a correlated electron insulator (or Mott
insulator). Correlated electron insulators often show the electronic phase transition accompanied by a drastic change in
their resistivity under external stimuli such as temperature, magnetic field, electric field, and light. Mott memory exploits
this electronic phase transition (called Mott metal-to-insulator transition or Mott transition 117 ) induced by an electric field.

A mechanism of the Mott memory has been theoretically proposed in terms of the interfacial Mott transition induced by
the carrier accumulation at a Schottky-like interface between a metal electrode and a correlated electron insulator 118 . The
theory also predicted that the resistive switching due to the interfacial Mott transition has a nonvolatile-memory
functionality, because the Mott transition is a first-order phase transition due to its nature 117 . In addition, Mott memory X X
based on the Mott transition involving a large number of carriers (more than 1022 cm-3) has in principle an advantage in
device scaling, because there are a sufficient number of carries for the Mott transition even in a nanoscale device.
The Mott transition induced by an electric field or carrier injection has been experimentally demonstrated in a correlated
electron material of Pr1-xCaxMnO3. 119 After this demonstration, two-terminal devices such as switches and memories have
been intensively studied with using such correlated electron oxides as Pr1-xCaxMnO3, 120,121 VO2, 122,123,124 SmNiO3, 125
NiO, 126,127 Ca2RuO4, 128 and NbO2, 129,130 and using Mott-insulator chalcogenides of AM4X8 (A=Ga, Ge; M=V, Nb, Ta;
X=S, Se). 131,132,133,134 In addition to these inorganic materials, recently, reversible and nonvolatile resistive switching
based on the electronic phase change between charge-crystalline state and quenched charge glass has been demonstrated
in the organic correlated materials of -(BEDT-TTF)2X (where X denotes an anion). 135
Scalability has been demonstrated down 110 × 110 nm2 in Mott memristors consisting of NbO2 that shows the
temperature-driven Mott transition from a low-temperature insulator phase to a high-temperature metal phase. The
switching speed, energies, and endurance of the NbO2-Mott memristors have been evaluated to be less than 2.3 ns, of the
order of 100 fJ, and >109, respectively. 129 , 130 The programing and read voltages reported so far are < 2 V and < 0.2 V,
X X X X
respectively. 127 The nonvolatile resistive switching of AM4X8 single crystals was induced by the electric field of less than
X X
10 kV/cm. 131 , 132 , 133 , 134 This suggests that if the device consisting of a 10-nm-thick AM4X8 film is fabricated, the
X X X X X X X X
switching voltage will be less than 0.01 V.

Although nonvolatile switching has been reported in the devices based on AM4X8 and -(BEDT-TTF)2X, their retention
characteristics are not elucidated in detail. 131 , 132 , 133 , 134 , 135 In addition, the NbO2-Mott memristors and VO2-based devices
X X X X X X X X X X
are volatile switch. 122 , 123 , 124 , 129 130 The retention is thus a major concern of Mott memory. In principle, the Mott transition
X X X X X X X XX X
can be driven even by a small amount of carrier doping to the integer-filling or half-filling valence states of transition
element. 117 However, because of disorders, defects, and spatial variation of chemical composition, rather large amount of
X X
carriers of more than 1022 cm-3 are required to drive the Mott transition in actual correlated electron materials, resulting in
a relatively large switching voltage required in the Mott memory. Therefore, one of the key challenges is the control of
crystallinity and chemical-composition in the thin films of correlated electron materials, including the integration of the
correlated electron materials onto Si platform. There are some theoretical mechanisms proposed for Mott memories such
as the interfacial Mott transition 118 and the formation of conductive filament generated by local Mott transition. 131 , 133 , 134
X X X X X X X X
However, a thorough understanding of the mechanism has not been achieved yet. Therefore, the elucidation of detailed
mechanism is also a major research challenge.
8 2.2.5 Novel STT-RAM
Recently, some novel mechanisms have been discovered to switch spin-transfer-torque RAM (STT-RAM). Among them,
voltage-incuded magnetization switching and spin Hall effects are the most promising candidates.
Voltage pulse induction of magnetization switching has emerged as a candidate for a high efficiency nonvolatile
memory. 136 The voltage driven nature of the technology allows us to use high resistance magnetic tunneling junctions and
fits to the existing CMOS design. It has the potential to offer ultra-low power, high speed and long endurance memory
cells beyond conventional STT-MRAM technology, which is based on a spin-polarized current injection.
The voltage writing technique is based on a magnetic anisotropy change because of application of an electric field at the
interface between magnetic metal and an insulator. The change in magnetic anisotropy switches magnetization from
perpendicular to in-plane for a quasi-static process. With high-speed pulse application, however, the magnetization
undertakes a precessional switching within around 1 nsec. 137 Since the precessional switching is a toggle switching, a
read procedure is required before a writing pulse. Alternative method to use voltage effect is a combination with spin-
transfer effect. For this case a precise control of device parameters 138 or a special pulse shape 139 is required. Voltage
torque MRAM (VT-MRAM) is a very attractive candidate as for a storage class memory, DRAM and/or cash memory.
For magnetic cells less than 20 nm in diameter, however, development of a material with a higher voltage effect is
essential.
Voltage switching of magnetization requires the effect that cancels the magnetic anisotropy. Since smaller magnetic cell
requires larger magnetic anisotropy to keep its retention, it also requires larger voltage effect. Here, both magnetic

anisotropy and voltage effects are proportional to the spin-orbit interaction. Therefore, larger voltage effect is expected
for the smaller cells, in which materials with a larger spin-orbit interaction is implemented.
Endurance and temperature range of the VT-MRAM can be as good as STT-MRAM. Retention of the cells used in
published papers are not enough. Write energy and current are already smaller than those in STT-MRAM but voltage
higher. An integrated VT-MRAM array has not yet been demonstrated. 137 X
Huge voltage effects associate with redox reaction, charge trapping, and/or atom migration has been reported. 140 In such
cases, the effect can be slow (1 µsec or longer), hysteretic and the endurance can be limited. In addition, smaller pure
electronic effects are an alternative mechanism. The largest effect, which is claimed as a purely electronic mechanism,
has been observed in Cr/FeB/MgO system. 140 The size of the effect only allows to control 30 nm or larger cells. To
X X
switch 1x nm cells, an effect of 3x larger will be required.

VT-MRAM requires a major breakthrough to enable application implementation. Three advances are needed to make the
VT-MRAM viable. The first is to create a much larger electronic voltage effect on the magnetic anisotropy. Efforts are
needed which explore new combinations of ferromagnetic metal and insulating barrier material. The effect needs to be
imporved by a factor 3 or more. The second necessary breakthough is enhancement of the switching speed and endurance
of the redox type voltage effect. Finally, a STT-VT hybrid device array should be demonstrated. 138 However, the first
X X
pursuit should be to explore methods of having a larger and pure electronics voltage effect. Then, it is also important to
make clear error rate of the voltage writing. After that we may start to think about array test designing peripheral circuits.
The spin Hall effect (SHE) refers to the conversion of a charge current to a transverse pure-spin current in non-magnetic
materials 141,142 . Its origin stems from the asymmetric deflection of charge carriers via spin orbit coupling. The spin
currents generated using the SHE can transfer spin angular momentum to an adjacent magnetic layer through the STT
effect allowing for the controllable manipulation of magnetization using proximate electrical currents 143,144,145,146,147 . The
effect is distinct from the conventional STT, whereby the spin current is created by passing a charge current through a
ferromagnetic layer to spin-polarize the charge currents 148,149 .
To date, the materials showing large SHE include Pt, β-Ta, β-W, and oxygen doped tungsten with spin Hall angles, ,
of 0.05-0.1 145 ,150,151 , -0.12 143 , -0.33 152 , and -0.49 153 respectively. However, the largest
X X X X to date have been reported in
topological insulators 154,155 . Typically high are observed in highly resistive materials, and a challenge is to look for
low-resistivity materials with large in order to minimize the device power consumption. Furthermore, materials
with large tend to increase the damping of the magnetic material through the spin pumping effect 156 ; minimizing
this effect would be beneficial for applications as the switching current threshold for spin torque switching is directly
proportional to the Gilbert damping constant. It is also important that the interface is transparent to the spin currents to
achieve maximum efficiency in spin angular momentum transfer 150 , 151 . A closely related effect to the SHE is the Rashba
X X X X
effect 157 , 158 , 159 that originates from the interfacial electric fields between dissimilar materials. In the reference frame of
the moving electron, these interfacial electric fields appear as an effective magnetic field and causes the spins of the
electrons to be re-oriented. This effect thus gives rise to a charge to spin current conversion, similar to the SHE.
The STT originating from SHE and Rashba effects are collectively known as spin orbit torques 160 . They have been used
as the writing mechanism in magnetic tunnel junction (MTJ) devices 143 . One particular advantage of this writing
X X
mechanism is that it does not require large voltages through the MTJ tunnel barrier, which can, over extended time
periods, lead to dielectric breakdown of the tunnel barrier. However, it does require a three terminal device, and is limited
mostly to in-plane magnetized MTJ devices, although some recent promising studies have shown that through
engineering the device structure to produce a field like spin orbit torque or applying an in-plane magnetic field,
deterministic switching of perpendicular magnetized devices can be achieved 158 . The SHE- STT can also be used for the
X X
current induced manipulation of magnetic domain walls in perpendicular magnetized materials as in racetrack memory
devices 146 , 147 .
X X X X
2.3 MEMORY SELECT DEVICE

The capacity (or density) is one of the most important parameters for memory systems. In a typical memory system,
memory devices (cells) are connected to form an array. A memory cell in an array can be viewed as being composed of
two components: the ‘storage node’, which is usually characterized by an element with switchable states, and the
‘selector’, which allows the storage node to be selectively addressed for read and write. Both components impact scaling
limits of memory. It should be noted that for several advanced concepts of resistance-based memories, the storage node

could in principle be scaled down below 10 nm 161 , and the memory density is often limited by the selector devices. Thus
the selector device represents a serious bottleneck for emerging memory scaling to 10 nm and beyond.
The most commonly used memory selector devices are transistors (e.g., FET or BJT), as in DRAM, FRAM, etc. Flash
memory is an example of a storage node (floating gate) and a selector (transistor) combined in one device. Planar
transistors typically have the footprint around (6-8)F2. In order to reach the highest possible 2D memory density of 4F2, a
vertical transistor selector needs to be used. However, transistors as selector devices are generally unsuitable for 3D
memory architectures. Two-terminal memory selector devices are preferred for scalability and can be used in crossbar
memory arrays to achieve 4F2 footprint 162,163 . The function of selector devices is essentially to minimize leakage through
unselected paths (“sneak paths”). Two-terminal selector devices can achieve this through asymmetry (e.g., rectifying
diodes) or nonlinearity (e.g., nonlinear devices) 164 . Volatile switches can also be used as selector devices. Figure ERD4
shows a taxonomy of memory selector devices. In addition to external selector device, some storage elements may have
inherent self-selecting properties (e.g., intrinsic nonlinearity or self-rectification), which may enable functional crossbar
arrays without external selectors.
Memory Selector Devices
Transistor Diodes Volatile switch Nonlinear devices
Planar Si diodes Threshold Tunneling-based

switch nonlinear selector
Vertical Oxide/oxide
heterojunctions Mott switch MIEC
Metal/oxide Schottky Complementary

junctions structures
Reverse-conduction Intrinsic
diodes nonlinearity
Self-rectification
Figure ERD4. Taxonomy of memory select devices
9 2.3.1 Vertical transistors

Several examples of experimental demonstrations of vertical transistors used as selectors in memory arrays are presented
in Table ERD5. While a vertical transistor selector allows for the highest planar array density (4F2), it is challenging to
integrate transistor selector into stacked 3D memory. For example, to avoid thermal stress on the memory elements on
the existing layers, the processing temperature of the vertical transistor in 3D stacks must be low. Also, making contact to
the third terminal (gate) of vertical transistors constitutes an additional integration challenge, which usually results in cells
size larger than (4F2) 165 ; although true 4F2 arrays can, in principle, be implemented with 3-terminal selector devices 166 .
Table ERD5 Experimental demonstrations of vertical transistors in memory arrays.
10 2.3.2 Diode selector devices

General requirements for two-terminal selector devices are sufficient ON currents at proper bias to support read and write
operations and sufficient ON/OFF ratio to enable selection. The minimum ON current required for fast read operation is ~
1A (Table ERD6). The required ON/OFF ratio depends on the size of the memory block, m×m: for example using a
standard scheme of array biasing the required ON/OFF ratio should be in the range of 107-108 for m=103-104, in order to
minimize the ‘sneak’ currents 167 . These specifications are quite challenging, and the experimentally demonstrated selector
devices can rarely meet them. Thus, selector devices are becoming a critical challenge of emerging memory. It should be
noted that different application targets of resistance-based memories also impact selector device requirements.
Table ERD6 Benchmark Select Device Parameters.

The simplest realization of diode selectors uses semiconductor diodes, such as a pn-junction diode, Schottky diode, or
heterojunction diode. Such devices are suitable for a unipolar memory cell. For bipolar memory cells, selectors with bi-
directional switching are needed. Proposed examples include Zener diodes 168 , BARITT diodes 169 , reverse breakdown
Schottky diode 170 .
2.3.2.1 Si diode selector devices
Both single-crystal Si 171 and poly-Si 172 , 173 , 174 diodes have been developed as selector devices for PCM arrays. To
X X X X X X
provide high ON current, the contact resistivity needs to be reduced to < 10-7 cm2, which was achieved by engineering
the metal electrodes and electrode-Si interface 172 . A short-time annealing technique helps to reduce the OFF current and
enlarge the ON/OFF ratio. Poly-Si technology can achieve ON current density of 107 A/cm2 (at ~ 1.8V) and ON/OFF
ratio of 108. It is believed that Si diode can be scaled beyond 20nm or 10nm. Poly-Si diode selector devices have been
integrated in PCM crossbar arrays, 3D vertical chain-cell type PCM 173 , and a 1Gb PCM test chip 174 . A major challenge
of Si diodes is the high processing temperature (above 1000C) required to crystallize Si to reduce contact resistivity and
OFF current.
52 2.3.2.2 Oxide diode selector devices
Oxide-based heterojunction 175 , 176 , 177 , 178 or Schottky junction 181 , 182 , 183 , 184 diodes may be fabricated at lower temperature
X X X X X X X X X X X X X X X X
and used as selector devices. They are particularly suitable for oxide-based RRAM devices. A p-NiOx/n-TiOx diode has
demonstrated a rectification ratio of 105 at 3V and ON current density of 5103 A/cm2 (at ~ 2.5V) 175 . A p-CuOx/n-
InZnOx diode achieved higher ON current density of 104 A/cm2 (at ~ 1.3V) and was integrated with NiOx RRAM in a 2-
layer 88 crossbar array 176,177 and with Al2O3 antifuse in a one-time-programmable (OTP) memory 178 . Si substrates can
be used as a part of heterojunction diodes as demonstrated in n-ZnO/p-Si 179 and n-Ge-nanowire/p-Si diodes 180 . In a TiOx-
based diodes with Pt electrodes, temperature-dependent current-voltage (I-V) characteristics confirms a Schottky barrier
of ~0.55eV at the TiOx/Pt interface 181 . The rectification ratio is ~ 1.6104 at 1V but ON current density is low (~
13A/cm2) due to large size. A Pt/TiO2/Ti diode with Pt as the Schottky contact and Ti the ohmic contact achieved higher
rectification ratio of 107 – 109 at 1V 182 . Another demonstration of Pt/TiO2/Ti Schottky diodes improved ON current
density to ~ 3105 A/cm2 at 2V on a 4µm2 area 183 . Measurement showed that current is not uniform across the diode
area, probably due to edge leakage. Therefore, current density is higher at smaller diode size. An Ag/n-ZnO Schottky
diode with non-alloyed Ti/Au ohmic contact demonstrated a rectification ratio of 105 and forward current density over 104
A/cm2 at 2V 184 . In addition to oxide Schottky diodes, Si Schottky diodes are also utilized as selector devices, e.g., Al/p-
Si 185 . The ON current of oxide-based heterojunction diodes is often limited by both contact resistance and density of
states of the oxide materials.
2.3.3 Volatile switch as selector devices
Volatile resistive switching devices can also be utilized as selector devices. They provide access to a selected memory
element in their ON state and block sneak paths in OFF state. The device structure and physics of operation of these
devices are sometimes similar to those of the storage nodes. The main difference is that nonvolatility is required for the
storage node, while for select devices volatile switching characteristics allow them to be switched quickly between ON
and OFF states.
53 2.3.3.1 Mott switch
This device is based on metal-insulator transition (i.e., Mott transition) and exhibits a low resistance above a critical
electric field (threshold voltage, Vth). It recovers to a high-resistance state if the voltage is below a hold voltage (Vhold). If
the electronic conditions that triggered Mott transition can relax within the memory device operation time scale, the Mott
transition device is essentially a volatile resistive switch and can be utilized as a selector device. A VO2-based device has
been demonstrated as a selector device for NiOx RRAM element 186 . However, the feasibility of the Mott-transition switch
as selector devices still needs further research. It should be noted that VO2 undergoes a phase transition to the metallic
state at temperature around 68°C, which restricts its operation temperatures and limits practical applications of VO2
selector as current specifications require operational temperature of 85°C. Suitable Mott materials with higher transition
temperatures need to be investigated. Metal insulator transitions at ~ 130°C and electrically driven switching were
observed in thin films of SmNiO3 187 .

54 2.3.3.2 Threshold switch

This type of device is based on the threshold-switching effect observed in thin-film MIM structures caused by electronic
charge injection. Significant resistance reduction occurs at Vth and this low-resistance state quickly recovers to the
original high-resistance state when the applied voltage falls below Vhold. It was reported that chalcogenide-based
threshold switches could be used as access devices in PCM arrays 188 . Niobium oxide is found to possess both memory
switching and threshold switching properties at different compositions, based on which a hybrid memory (W/bi-layer-
NbOx/Pt) was demonstrated in a 1kb array 189 . NbOx-based selectors have also been integrated with TiOx/TaOx based
RRAM in crossbar arrays at 5xnm node 190 . In Si-As-Te ternary alloy, the composition (controlled by the sputtering
power during deposition) determines the emergence of threshold switching 191 . Both Vth and Vhold vary with composition,
which may provide a method to optimize the selector device operation window. Another threshold switch device based
on chalcogenide AsTeGeSiN was shown to be scalable to 30nm with current density exceeding 10MA/cm2 and endurance
over 108 cycles 192, 193 . It was integrated with TaOx-based RRAM devices. An unavoidable finite delay time was found in
this selector device due to intrinsic properties of the chalcogenide material, which may limit the selector speed. Another
doped-chalcogenide (material undisclosed) based selector demonstrates low Vhold (0.2V), large on/off ratio (>107), fast
speed (<10ns), long endurance (>109 cycles) and good thermal stability (180C) 194 . A so-called “FAST” (Field Assisted
Superliner Threshold) selector was recently reported, with abrupt switching (<5mV/dec), high on/off ratio (107), and long
endurance (108 cycles) 195 . Unlike other threshold switch selectors, this device doesn’t exhibit recovery to OFF-state at
certain Vhold, which appears more like a nonlinear selector. A 4Mb 1S1R crossbar RRAM array has been demonstrated
based on this selector.
12 2.3.4 Nonlinear selector devices

Similar to volatile switches, nonlinear selector devices can be used with bipolar memory elements, which is an advantage
over rectifying diode selectors.
55 2.3.4.1 Nonlinear selector devices
Nonlinearity in device characteristics can be introduced with non-ohmic transport mechanisms, e.g., tunneling. A
Ni/TiO2/Ni nonlinear selector device is integrated with HfO2-RRAM to demonstrate a 1S1R memory structure 196 .
Another selector device with Pt/TiO2/TiN structure is combined with a bi-layer Pt/TiO2-x/TiO2/W RRAM for a functional
memory device 197 . A so-called “varistor” selector device is based on a sandwiched TaOx/TiO2/TaOx structure 198 . It was
found that the substitution of Ti4+ in TiO2 by Ta5+ ions increases the conductivity of the initially insulating TiO2 layer.
The ON-current of nonlinear selector devices can be modulated by oxide thickness and oxidation conditions. Another
multi-oxide stack (Ta2O5/TaOx/TiOx) based selector also leverages various interface engineering techniques to obtain high
ON-current density (>107 A/cm2), high nonlinearity ratio (~104), and low OFF-current (<100nA) 199 . It is integrated with
CBRAM in a 1kb crossbar array. A back-to-back diode structure, n+/p/n+ poly-Si, is also suggested as a selector device,
where the middle p-layer is fully depleted and a drain induced barrier lowering (DIBL) effect causes exponential current
increase with applied voltage 200 .
56 2.3.4.2 MIEC switch
The device is made from Cu-containing “mixed ionic and electronic conduction” (MIEC) materials sandwiched between
an inert top electrode (TE) (e.g., TiN, W) and a bottom electrode (BE). Negative voltage applied on TE pulls Cu+ in
MIEC away from the BE and create vacancies near BE. The hole and vacancy concentrations depend exponentially on
the applied voltage. Symmetrical diode-like I-V characteristics is achieved with two inert electrodes. Large fraction of
mobile Cu+ enables high current density (> tens of MA/cm2) 201 . Endurance above 108 cycles has been demonstrated on
MIEC devices in small arrays 202 . The MIEC selector devices were also integrated with PCM in a 512kb testing array
using 180nm CMOS process 203 . The scalability of MIEC select devices was tested to below 30nm in diameter and below
12nm in thickness 204 .
57 2.3.4.3 Complementary resistive switches
Complementary resistive switch (CRS) provides a self-selecting memory by connecting two bipolar RRAM devices anti-
serially 205 . It may be considered as “constructed nonlinearity”. Both states “0” and “1” have high resistance in CSR,
which helps to minimize leakage through sneak paths. In either state, one of the two RRAMs is in LRS and the other in
HRS. When reading a “1” state, the HRS device is switched to LRS and both devices end up in LRS. When reading a
“0” state, no switching occurs and CSR remains in HRS. Notice that the reading operation is destructive, although non-

destructive readout method was also proposed 206 . CRS has been demonstrated in different resistive switching devices,
e.g., Cu/SiO2/Pt bipolar resistive switches 207 , amorphous carbon-based RRAM 208 , TaOx–based RRAM 209 , multi-layer
TiOx device 210 , HfOx RRAM 211 , ZrOx/HfOx bi-layer RRAM 212 , Cu/TaO2 atomic switch 213 , Nb2O5−x/NbOy RRAM 214 , etc.
Table ERD7a summarizes experimentally demonstrated parameters of some two-terminal select devices, including
diodes, volatile switches, and nonlinear devices. Table ERD7b summarizes the parameters of some reported self-
rectifying memories. It should be emphasized that these summary tables can only capture a snapshot of selector device
characteristics; however, the functionality of these devices depends on their actual voltage in arrays with random data
patterns and the balance between selectors and storage elements. Therefore, these parameter tables should only be used
for illustration purpose, not for rigorous benchmark or assessment.
It remains a great challenge for the demonstrated selector devices to meet all the requirements in Table ERD6. For scaled
two-terminal select devices, two fundamental challenges are contact resistance 172 and lateral depletion effects 215,216 .
X X
Very high doping concentration is needed to minimize both effects. However, high doping concentrations result in
increased reverse bias currents in classical diode structures and therefore reduced Ion/Ioff ratio. For switch-type selector
devices the main challenges are identifying the right material and the switching mechanism to achieve the required drive
current density, Ion/Ioff ratio, and reliability.
Table ERD7a Experimentally demonstrated two-terminal memory select devices.
Table ERD7b Experimentally demonstrated self-selecting memory devices (self-rectifying).
2.4 STORAGE CLASS MEMORY DEVICES
13 2.4.1 Traditional storage: HDD and Flash solid-state drives

Conventionally, magnetic hard-disk drives are used for nonvolatile data storage. The cost of HDD storage in $/GB is
extremely low and continues to decrease. Although the bandwidth with which contiguous data can be streamed is high,
the poor random access time of HDDs limits the maximum number of I/O requests per second (IOPs). In addition, HDDs
have relatively high energy consumption, a large form factor, and are subject to mechanical reliability failures in ways
that solid state technologies are not. Despite these issues, the sheer number and growth in HDD shipments per year
(380,000 Petabytes in 2012, growing at 32% per year) means that magnetic disk storage is highly unlikely to be
“replaced” by solid-state drives at any time in the foreseeable future 217 .
Nonvolatile semiconductor memory in the form of NAND flash has become a widely-used alternative storage technology,
offering faster access times, smaller size and lower energy consumption when compared to HDD. However, there are
3 5
several serious limitations of NAND flash for storage applications, such as poor endurance (10 – 10 erase cycles), only
modest retention (typically 10 years on a new device, but only 1 year at the end of rated endurance lifetime), long erase
time (~ms), and high operating voltage (~15V). Another difficult challenge of NAND Flash SSD is posed by its
page/block-based architecture. By not allowing for direct overwrite of data, sophisticated procedures for garbage
collection, wear-leveling and bulk erase are required. This in turn requires additional computation – which reduces
performance and increases cost and power because of the need for a local processor, RAM, and logic – as well as over-
provisioning of the SSD which further increases cost per effective user-bit of data 218 .
Although flash memory technology continues to project for further density scaling, inherent performance characteristics
such as read, write and erase latencies have been nearly constant for more than a decade 219 . While the introduction of
multi-level cell (MLC) flash devices extended flash memory capacities by a small integral factor (2-4), the combination
of scaling and MLC have resulted in the degradation of both retention time and endurance, two parameters critical for
storage applications. The migration of NAND Flash into the vertical dimension above the silicon has continued this trend
of improving bit density (and thus cost-per-bit) while maintaining or in some cases, even slightly degrading the latency,
retention, and endurance characteristics of present-day NAND Flash.
This outlook for existing technologies has opened interesting opportunities for prototypical and emerging research
memory technologies to enter the non-volatile solid-state-memory space.

14 2.4.2 What is Storage Class Memory?

Storage-class memory (SCM) describes a device category that combines the benefits of solid-state memory, such as high
performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. 220,221
Such a device requires a nonvolatile memory (NVM) technology that could be manufactured at a very low cost per bit.
A number of suitable NVM candidate technologies have long received research attention, originally under the motivation
of readying a “replacement” for NAND Flash, should that prove necessary. Yet the scaling roadmap for NAND Flash has
progressed steadily so far, without needing any replacement by such technologies. So long as the established commodity
continues to scale successfully, there would seem to be little need to gamble on implementing an unproven replacement
technology instead.
However, while these NVM candidate technologies are still relatively unproven compared to Flash, there is a strong
opportunity for one or more of them to find success in applications that do not involve simply “replacing” NAND Flash.
Storage Class Memory can be thought of as the realization that many of these emerging alternative nonvolatile memory
technologies can potentially offer significantly more than Flash, in terms of higher endurance, significantly faster
performance, and direct-byte access capabilities. In principle, Storage Class Memory could engender two entirely new
and distinct levels within the memory and storage hierarchy. These levels would be differentiated from each other by
access time, with both levels located within the more than two orders of magnitude between the latencies of off-chip
DRAM (~80ns) and NAND Flash (20µs).
58 2.4.2.1 Storage-type SCM
The first new level, identified as S-type storage-class memory (S-SCM), serves as a high-performance solid-state drive,
accessed by the system I/O controller much like an HDD. S-SCM must provide at least the same data retention as Flash,
allowing S-SCM modules to be stored offline, while offering new direct overwrite and random access capabilities (which
can lead to improved performance and simpler systems) that NAND flash devices cannot provide. However, because of
the modest (perhaps 10x) advantage in read latency over NAND Flash, it is critical that the eventual cost-per-bit for S-
SCM be no worse than 3-10x higher than NAND Flash. While such costs need not be realized immediately at first
introduction, it would need to be very clear early on that costs could steadily approach such a level relative to Flash.
Note however that such system cost reduction can come from other sources than the raw cost of the device technology: a
slightly-higher-cost NVM technology that enabled a simple, low-cost SSD by eliminating or simplifying costly and /or
performance-degrading overhead components would achieve the same overall goal. If the cost per bit could be driven low
enough through ultrahigh memory density, ultimately such an S-SCM device could potentially replace magnetic hard-disk
drives in enterprise storage server systems as well as in mobile computers (subject to the same issues mentioned above in
terms of needing numerous IC fabs to ship the many petabytes of HDD delivered to those markets 217 ).
X X
59 2.4.2.2 Memory-type SCM

The second new level within the memory and storage hierarchy, termed M-type storage-class memory (M-SCM), should
offer a read/write latency of less than ~200 ns. These specifications would allow it to remain synchronous with a memory
system, allowing direct connection from a memory controller and bypassing the inefficiencies of access through the I/O
controller. The role of M-SCM would be to augment a small amount of DRAM to provide the same overall system
performance as a DRAM-only system, while providing moderate retention, lower power-per-GB and lower cost-per-GB
than DRAM. Again, as with S-SCM, the cost target is critical. It would be desirable to have cross-use of the same
technology in either embedded applications or as a standalone S-SCM, in order to spread out the development risk of an
M-SCM technology. The retention requirements for M-SCM are less stringent, since the role of non-volatility might be
primarily to provide full recovery from crashes or short-term power outages, requiring non-volatility over a period of
perhaps 3-20 days.
Particularly critical for M-SCM will be device endurance, since the time available for wear-leveling, error-correction, and
other similar techniques is limited. The volatile portion of the memory hierarchy will have effectively infinite endurance
compared to any of the non-volatile memory candidates that could become an M-SCM. Even if device endurance can be
9
pushed well over 10 cycles, it is quite likely that the role of M-SCM will need to be carefully engineered within a
cascaded-cache or other Hybrid Memory approach 222 . That said, M-SCM offers a host of new opportunities to system
designers, opening up the possibility of programming with truly persistent data, committing critical transactions to M-
SCM rather than to HDD, and performing commit-in-place database operations.

15 2.4.3 Target Specifications for SCM

Since the density and cost requirements of SCM transcend the straightforward scaling application of Moore’s Law,
additional techniques will be needed to achieve the ultrahigh memory densities and extremely low cost demanded by
SCM, such as (1) 3-D integration of multiple layers of memory, currently implemented commercially for write-once
solid-state memory 223 , and/or (2) Multiple level cell (MLC) techniques.
Table ERD8 lists a representative set of target specifications for SCM devices and systems compared with benchmark
parameters of existing technologies (HDD and NAND Flash). As described above, SCM applications can be expected to
naturally separate based on latency. Although S-class SCM is the slower of these two targeted specifications, read and
write latencies should be in the 1-5 μsec regime in order to provide sufficient performance advantage over NAND Flash.
Similarly, endurance of S-class SCM should offer at least 1 million program-erase cycles, offering a distinct advantage
o
over NAND Flash. In order to support off-line storage, 10 year retention at 85 C should be available.
In order to make overall system power usage (as shown in Table ERD8) competitive with NAND Flash and HDD, and
since faster I/O interfaces can be expected to consume considerable power, the device-level power requirements must be
extremely minimal. This is particularly important since low latency is necessary but not sufficient for enabling high
bandwidth – high parallelism is also required. This in turn mandates a sufficiently low power per bit access, both in terms
of peripheral circuitry and device-level write and read power requirements. Finally, standby power should be made
extremely low, offering opportunities for significant system power savings without loss of performance through rapid
switching between active and standby states.
In order to achieve the desired cost target of within 3-10x of the cost of NAND Flash, the effective areal density will
similarly need to be quite similar to 1X-node planar NAND Flash. This low cost structure would then need to be
maintained by subsequent SCM generations, through some combination of further scaling in lateral dimension, by
increasing the number of multiple layers, or by increasing the number of bits per cell.
Also shown in Table ERD8 are the target specifications for M-type SCM devices. Given the faster latency target (which
enables coherent access through a memory controller), program-erase cycle endurance must be higher, so that the overall
non-volatile memory system can offer a sufficiently large lifetime before needing replacement or upgrade. Although some
studies have shown that a device endurance of 1e7 is sufficient to enable device lifetimes on the order of 3-10 years 224 , we
anticipate that the need for sufficient engineering margin would suggest a minimum cycle endurance of 1e9 cycles. While
such endurance levels support the use of M-class SCM in memory support roles, significantly higher endurance values
would allow M-class SCM to be used in more varied memory applications, where the total number of memory accesses
may become very large.
Table ERD8 Target device and system specifications for SCM.
Table ERD9 Potential of the current prototypical and emerging research memory candidates for SCM
applications.
16 2.4.4 First SCM products reach the market

In July 2015, Intel and Micron jointly announced a new nonvolatile memory technology, called “3D-Xpoint.” This
technology is said to offer 1000x lower latency and 1000x higher endurance than NAND Flash, at a density that is 10x
higher than DRAM 225,226 . (Note that it is most likely that the latency referred to here is write latency rather than read
latency, since NAND write latency is much slower than its read latency.) 3D-Xpoint technology, said to have been
implemented at the 128Gbit chip level, is based on a two-layer stacked crossbar array, with each intersection point
containing a nonvolatile memory device and a nonlinear access device [Micron3DXpoint]. The particular nonvolatile
memory device was not specified, other than that it depends on bulk changes of resistance 227 , nor was the nonlinear
access device described. Speculation based on patent searches and job solicitations suggest that the technology may be a
combination of some variant of phase change memory and an Ovonic Threshold Switching access device 227 . X X
While the details of the devices involved may still be uncertain, the projected array specifications and the target
applications are, for all intents and purposes, indistinguishable from those described above for S-type Storage Class
Memory. Thus we can consider 3D-Xpoint as the first commercial implementation of the Storage Class Memory concept
first described in 2008 220 , 221 . Furthermore, in a later presentation, a second, “Performance-focused” form of 3D-Xpoint
X X X X
memory was described as being under active development 228 . Compared to the initial “Cost-focused” form of 3D-Xpoint

memory, this variant is said to offer even faster latencies and higher endurance (Figure ERD5). Thus this second variant
of 3D-Xpoint is somewhat similar to M-type SCM as described above, both in terms of its specifications and in terms of
potential applications. The only major difference, as observed in Figure ERD5, is the strong similarity between the
expected volatility of Performance-focused 3D-Xpoint and the known volatility of DRAM. In contrast, one of the
benefits of M-type SCM was supposed to be its non-volatility. Ideally, retention of data for perhaps 1-2 weeks would
permit successful recovery of server data, even after a power outage due to a natural disaster or other major event.
Figure ERD5 Comparison of performance of different memory technologies
3. EMERGING LOGIC AND ALTERNATIVE INFORMATION PROCESSING

DEVICES
3.1 TAXONOMY
One of the central objectives of this chapter is to review recent research in devices beyond silicon transistors and to
forecast the development of novel logic switches that might replace the silicon transistor as the device driving
technological development within the semiconductor industry. Such a replacement is thought potentially to be viable if
one or more of the following capabilities is afforded by a novel device: (1) an increase in device density (and
corresponding decrease in cost) beyond that achievable by ultimately scaled CMOS; (2) an increase beyond CMOS in
switching speed, e.g., through improvements in the normalized drive current or reduction in switched capacitance; (3) a
reduction beyond CMOS in switching energy, associated with a reduction in overall circuit energy consumption; or (4)
the enabling of novel information processing functions that cannot be performed as efficiently using conventional CMOS.
The organization of this section is intended to reflect a progression of options that might enable an orderly transition from
CMOS to devices that depart increasingly from CMOS in terms of structure, materials, or operation. That organization is
depicted in Figure ERD6.
The resulting taxonomy of emerging logic devices is conveyed in the three tables associated with this section. Table
ERD10a is titled “Extending MOSFETs to the End of the Roadmap” and tabulates characteristics of the devices in the
lower-left quadrant of Figure ERD5. These devices are reviewed below in Section 3.2. Table ERD10b, titled “Charge-
Based Beyond CMOS: Non-Conventional FETs and Other Charge-Based Information Carrier Devices,” consists of those
devices in the lower-right quadrant of the figure, which are reviewed in Section 3.3. Finally, Table ERD10c details the
“Alternative Information Processing Devices” that are listed in the upper-right quadrant of Figure ERD5 and that are
reviewed below in Section 3.4.

Figure ERD6 Taxonomy of options for emerging logic devices. The devices examined in this chapter are differentiated according
to (1) whether the structure and/or materials are conventional or novel, and (2) whether the information carrier is electron charge
or some non-charge entity. Since a conventional FET structure and material imply a charge-based device, this classification
results in a three-part taxonomy.
Table ERD 10a MOSFETS: Extending MOSFETs to the End of the Roadmap.
Table ERD 10b Charge-Based Beyond CMOS: Non-Conventional FETs and Other Charge-Based Information
Carrier Devices
Table ERD 10c: Alternative Information Processing Devices

3.2 DEVICES FOR CMOS EXTENSION
17 3.2.1 Carbon Nanotube FETs

For many researchers, the search for an ideal semiconductor to be used in FETs succeeded when single-walled carbon
nanotubes (CNTs) were first shown to yield promising devices more than 15 years ago. Owing to their naturally ultrathin
body (~1 nm diameter cylinders of hexagonally bonded carbon atoms), superb electron and hole transport properties, and
reasonable energy gap of ~0.6 – 0.8 eV, CNTs offer solutions in most of the areas that other semiconductors
fundamentally fail when scaled to the sub-10 nm dimensional scale. CNT FETs operate as Schottky barrier transistors
with nearly transparent barriers to carrier injection achieved for both n- and p-type transport. They are intrinsic
semiconductors and cannot be doped in the traditional sense; hence, no inversion layers of charge form to allow current
flow. Rather, the gate field lowers the energy barrier in the CNT channel to allow for carriers to be injected from the
metal contacts. The most prominent advantages of CNT FETs over other options for aggressively scaled devices are the
room temperature ballistic transport of charge carriers, the reasonable energy gap, the demonstrated potential to yield high
performance at low operating voltage, and scalability to sub-10 nm dimensions with minimal short channel effects.
In the past several years, significant advances have been made in understanding & enhancing device performance in CNT
FETs. These include (1) realizing end-bonded contacts having an effective contact length of 0 nm with reasonable
performance, 229 (2) detailing the impact of contact scalability in CNT FETs, 230 (3) maintaining performance as the
channel length is scaled down to 9 nm without observing short channel effects, 231 (4) fabricating complementary gate-all-
around FETs, 232 (5) fabricating an FET with an intrinsic fT of 153 GHz, 233 (6) fabricating CMOS inverters and pass-
transistor logic operating at 0.4 V with a non-doped CNT, 234 (7) fabricating a carbon nanotube computer composed of
178 FETs, 235 (8) progress towards reducing the variability in CNT FETs, 236 (9) understanding origins of hysteresis, 237
and (10) fabricating CNT FETs with ON-current of 0.5 mA/µm. 238
In addition to improvements at the device level, continuous progress has been achieved toward overcoming the dominant
material challenges,239 including the need to achieve purified and sorted semiconducting CNTs with a relatively uniform

diameter distribution and then position the CNTs into aligned, closely packed arrays with consistent pitch. With a target
purity of 99.9999% semiconducting CNTs and placement density of > 125 CNTs/µm (< 8 nm pitch), much work still
remains. However, it is important to note that progress continues to be steady and without fundamental obstacles barring
these goals from being realized. There also remains need for further research toward improving other device-level
aspects, including further reduction of contact effects at small contact lengths, demonstrated reduction in variability,
improved control of gate dielectric interfaces and properties, and the experimental study of devices and circuits fabricated
using the most scaled and relevant device structures and materials. In short, much work remains for CNT FETs, but with
some of the most substantial (and already demonstrated) potential in high-performance, low-voltage, sub-10 nm scaled
transistor applications.
18 3.2.2 Graphene FETs

Graphene materials offer the potential of extremely high carrier mobilities that can exceed those of carbon nanotubes, and
also offer the promise of patterning graphene nanoribbons using conventional top down processes. Work on graphene
field effect transistors (FETs) is proceeding at a rapid pace, but there are still many issues to address 240 . Beginning with
the first description of the electric field effect in graphene in 2004 241 , graphene FETs using bottom gating 241 , top- X X
gating 242, 243, 244 dual-gating 245, 246 , and side-gating 247 have been demonstrated using exfoliated 248, 249 epitaxial 242 , 243 , 250
X X X X
and CVD-grown graphene 251, 252 .

Research on graphene FETs started with use of exfoliated graphene to form a transistor channel. Recently, there have
been many studies using epitaxial graphene on SiC substrates and CVD-grown graphene. Exfoliated graphene still offers
the highest mobility 253, 254, 255 but is not manufacturable. Back-gated graphene FETs with SiO2 dielectric were typically
shown to have field-effect mobilities up to around 10,000 cm2/Vs 241 (note that although back-gating is not desirable for
X X
FET-based circuitry, this mobility value does act as a useful comparison to top-gate mobility values). It has been
predicted that the room-temperature mobility of graphene on SiO2 is limited to ~40,000 cm2/Vs due to scattering by
surface phonons at the SiO2 substrate 256 . In fact, the highest field effect mobilities were obtained using suspended
graphene. Values as high as 120,000 cm2/Vs and 1,000,000 cm2/Vs at 240 K and liquid-helium temperature,
respectively 253 , 254 , 255 have been measured. Recently, hexagonal boron nitride (hBN), an inert and flat material, was used
X X X X X X
as a substrate for a graphene channel 257,258 , and it was shown that the field effect mobility of such devices can exceed
100,000 cm2/Vs at room temperature. Epitaxial graphene on SiC has exhibited carrier mobilities as high as 15,000 cm2/Vs
and 250,000 cm2/Vs at room and liquid helium temperatures, respectively 259, 260 . On the other hand CVD graphene has
shown carrier mobilities as high as 25,000 cm2/Vs at room temperature 261 .
As for top-gated graphene-channel transistors, field-effect mobilities are in general lower than those shown above,
because the deposition of gate dielectric can degrade the electrical properties of graphene 262 . In order to avoid such
degradation, a buffer layer is often used between graphene and high-k materials 263, 264 . It was also shown that SiO2 layer
formed by vacuum evaporation did not degrade graphene channel so much, and field-effect mobilities as high as 5,400
cm2/Vs were achieved for top-gated transistors 265 . In another case, naturally-oxidized thin aluminum layer was used as a
seeding layer of Al2O3 by atomic layer deposition and field effect mobilities as high as 8600 cm2/Vs were achieved 266 .
The highest field effect mobility of top-gated graphene transistors was obtained using Al2O3 nanowire as gate dielectric,
which was as high as 23,600 cm2/Vs 267 . In this case, exfoliated graphene was used as a channel. Hexagonal boron nitride
has also been employed as a top-gate dielectric layer 268 , however, the mobility of such devices is not yet as high as the
value just shown above. Direct growth of hBN on graphene channels may be necessary for further improvement.
An important limitation of graphene for digital applications is its zero bandgap energy which in turn will result in a very
small Ion/Ioff ratio. Hhowever, several methods to open a bandgap have been proposed. One is to build devices with
graphene nanoribbons(GNRs) 269, 270, 271, 272, 273 . Carrier transport through a GNR was first demonstrated using
nanoribbons fabricated by a top-down approach 269 . An energy gap of ~200 meV was obtained for a GNR with a width of
X X
15 nm. Recently, devices with multipleGNRs with a sub-10 nm half-pitch were fabricated using patterning with directed
self-assembly of block copolymers 274 . The on-off ratios of these devices were, however, still ~10 at room temperature.
GNRs were also made by several other methods 270 , 271 , 272 , 273 . Specifically, it was recently demonstrated that GNRs with
X X X X X X X X
a precisely-controlled uniform width were synthesized by a bottom-up approach using 10,10’-dibromo-9,9’-bianthryl

precursor monomers 275 . The band gap of this nanoribbon was estimated to be ~3.7 eV 276, 277 . Formation of wider GNRs
with a smaller band gap was also demonstrated using a similar approach recently 278 , as well as heterojunctions of GNRs
with different widths (bandgaps) 279,280 .These bottom-up GNRs are typically formed on a clean Au(111) surface in ultra-
high vacuum, and it is still difficult to control their direction and position, which can be an obstacle for device fabrication.
Devices using GNRs with a 2-nm width made by sonication of exfoliated graphite in a chemical solution showed an on-

off ratio of 107, with a field effect mobility of ~200 cm2/Vs 270 . The relatively low mobility was considered to be caused
X X
by scattering at the edges of GNRs. In fact, recent theoretical studies showed that obtaining smooth edges is essential to
obtain good electrical properties 281 . In addition, recent experimental studies suggest that transport in GNRs is greatly
affected by defects at the edges and charged impurities 282, 283, 284 . Recently, however, it was shown that GNRs formed on
SiC can have a ballistic length greater than 10 μm at room temperature, corresponding to mobility higher than 105
cm2/Vs 285 . Although the width of GNRs in this case is relatively wide, typically 40 nm, the results clearly show a high
potential of GNRs. More efforts are, however, required to realize GNR transistors for CMOS.
Another approach to open a band gap in graphene is applying an electric field perpendicular to AB-stacked bilayer
graphene 286, 287, 288, 289, 290 . In fact, a transport gap of 130 meV was obtained at an electrical displacement of 2.2 V nm-1,
providing an on-off ratio of ~100 at room temperature 290 . The on-off ratio is not yet as low as theoretical predictions. In
X X
fact, it was recently pointed out that a small twist of AB-stacking bilayer can cause the bandgap to disappear 291 , which is
a serious problem. Alternatively, a band gap can also be created by molecular doping on one side or both sides of bilayer
graphene 292, 293, 294, 295, 296 . It is predicted that a band gap exceeding 300 meV is formed by sandwiching bilayer graphene
between n-type-dopant molecules and p-type-dopant molecules 295 . A transport gap can also be obtained by making holes
X X
in graphene, namely by making graphene nanomesh 297, 298, 299 . The transport gap can be controlled by the neck (distance
between holes) width. An on-off ratio up to ~100 was obtained at room temperature using this method. Recently, it was
demonstrated that a transport gap is created in graphene by introducing low-density defects with helium ion irradiation 300,
301
. An on-off ratio of ~100 was obtained at room temperature. The approaches introduced here have not yet provided an
on-off ratio large enough for logic applications; therefore, more efforts are required for this approach to be used in CMOS
applications.
An important application space for graphene may be RF with discrete elements and high linearity requirements. There
have been many studies aiming at such high-frequency applications 249 , 252 , 302 . A unity current gain cut-off frequency of
X X X X
427 GHz has been obtained by a self-aligned- processe using exfoliated graphene with a channel length of 67 nm 303 . Cut-
off frequencies as high as 350 GHz and 300 GHz have also been obtained for devices using epitaxial and CVD graphene,
respectively (channel length: 40 nm) 304 . Achieving a high maximum frequency of oscillation is the next important step
for realizing RF applications.
19 3.2.3 Nanowire FETs

Nanowire field-effect transistors are structures in which the conventional planar MOSFET channel is replaced with a
semiconducting nanowire. Such nanowires have been demonstrated with diameters as small as 0.5 nm 305 . They may be
composed of a wide variety of materials, including silicon, germanium, various III-V compound semiconductors (GaN,
AlN, InN, GaP, InP, GaAs, InAs), II-VI materials (CdSe, ZnSe, CdS, ZnS), as well as semiconducting oxides (In2O3,
ZnO, TiO2), etc. 306 Importantly, at low diameters, these nanowires exhibit quantum confinement behavior, i.e, 1-D
ballistic conduction 307 , and match well with the gate-all-around structure that may permit the reduction of short channel
effects and other limitations to the scaling of planar MOSFETs.
Important progress has been made in the fabrication of semiconducting nanowires for use as FET channels, for which
there are two principal methods. The first method is litho&etch, by which semiconducting channels are formed through
lithography and etch, followed by a printing or stamping processiii. The second is catalyzed chemical vapor deposition 308
,309
. In particular, the vapor-liquid-solid (VLS) growth mechanism has been used to demonstrate a variety of nanowires,
including core-shell and core-multishell heterostructures 310,311 . Heterogeneous composite nanowire structures have been
configured in both core-shell and longitudinally segmented configurations using group IV and compound materials. The
longitudinally segmented configurations are grown epitaxially so that the material interfaces are perpendicular to the axis
of the nanowire. This allows significant lattice mismatches without significant defects. Vertical transistors have been
fabricated in this manner using Si 312 , InAs 313,314 and ZnO 315 , with quite good characteristics. Core-shell gate-all-around
configurations 316 display excellent gate control and few short channel effects.
Circuit and system functionality of nanowire devices have been demonstrated, including vertical InAs MOSFETs with
103 GHz switching speed 317 , a down-conversion mixer based on vertical InAs transistors that showed cut-off frequency
of 2 GHz 318 , and extended, programmable arrays (“tiles”) of nonvolatile nanowire-based flash memory that are used to
build circuits such as full-adder, full-substratcor, multiplexer, demultiplexer, clocked D-latch and finite state
machines 319,320 . The measured operating speed of these various nanowire test circuits was limited by off-chip
interconnect capacitance and thus did not achieve the THz operation that is predicted to be the intrinsic capability of
nanowire devices 321,322 . Nearly ideal subthreshold swing of 60 mV/dec has been obtained in gate-all-around nanowire

transistors for both n and p type devices 323 . Intrinsic switching energy as low as 2×10-17 J has also been demonstrated7324 ,
although it is still ~ 3 orders of magnitude higher than predicted theoretically.
Despite the promising results that are mostly obtained from academic research labs, nanowire transistors still face
significant challenges before commercialization is feasible. For both nanoimprint and grown nanowires, there is an urgent
need to improve device yield and uniformity, as well as position registry if the nanowires are to be transferred to a
different substrate. Due to the high surface-volume ratio, the performance of nanowire transistors likely will be strongly
influenced by surface roughness and surface defects, so proper surface treatment and passivation techniques need to be
developed. Additionally, although individual devices with gate length < 40 nm has been demonstrated7, it is unclear
whether high density circuits with pitch size comparable to state-of-the-art CMOS can be fabricated. Instead of channel-
replacement, nanowires may instead be better suited for alternative architectures such as crossbar memory and logic to
fully take advantage of the 1D structure these devices offer. However, effective interface with peripheral circuitry still
needs to be developed and series resistance can significantly limit the array size. Another option is to integrate vertical
nanowire devices directly on top of CMOS circuits, but this approach still remains to be demonstrated on a large scale.

20 3.2.4 P-type III-V Channel Replacement Devices
III-V compound semiconductors as replacements for n-type channel materials have attracted considerable attention
because of their excellent bulk electron mobilities 325 . To create high performance CMOS circuits, high mobility p-
channel materials are also required. Among III-V compound semiconductors, Sb-based semiconductors exhibit high hole
mobilities when used as bulk materials; for example, InSb and GaSb show mobilities of 850 cm2·V-1·s-1 and 800 cm2·V-1·s-
1
, respectively 326 , which are significantly greater than the bulk Si hole mobility of 500 cm2·V-1·s-1. Moreover, hole
mobility can be further increased by introducing biaxial compressive strain. This can be accomplished using
pseudomorphic growth on a material with a smaller lattice constant 326 , 327, 328, 329 . Another method of improving hole
X X
mobility is the application of uniaxial strain 328 , 330, which can be used in a similar manner as used in Si MOSFETs. The
X X
piezoresistance coefficient of p-InGaSb is 1.5 times greater than that of Si when uniaxial strain is applied 331 . Another
advantage of InGaSb is its superior characteristics when used as an n-channel material. InGaSb has an electron mobility
of over 4000 cm2·V-1·s-1. Thus, CMOS circuits can be fabricated using a single channel material system 332 .
The highest hole mobilities when using compressive strain were found in GaSb/AlAsSb heterostructures; they exhibit a
mobility 329 of 1500 cm2·V-1·s-1. In the case of an InGaSb/AlGaSb system, 1500 cm2·V-1·s-1 was also observed 327 . In InSb,
X X X X
the highest mobility 331 is 1230 cm2·V-1·s-1. However, the thickness of the quantum well was 5 nm; a wider well might
X X
provide higher mobility 329 . Regarding device performance, compressively strained InSb quantum well pFETs with a gate
X X
length of 40 nm have an fT value of 140 GHz, a gm of 510 mS/mm, and an Ion of 150 mA/mm at a power supply voltage of
0.5 V. When the gate length was 125 nm, the sub-threshold slope 331 was 90 mV/dec.
X X
A device on a Si substrate is essential as a replacement material for Si channels in MOSFETs. To realize III-V p-FETs on
a Si substrate, some methods are reported. First method is transfer of nano-ribbon 333 , nanowire14 or film15. In case of
nano-ribbon, the peak effective mobility of the device is 820 cm2·V-1·s-1, achieved using an InAs cladding layer for
surface passivation and hole confinement. By employing high-k materials (10-nm-thick ZrO2), the obtained sub-threshold
slope was 130 mV/dec, even at an interface surface density of 1.4 × 1013 cm-2·eV-1. In combination with an InAs channel
using the same technique, CMOS gates were fabricated and the logic operations of NOT and NAND were
demonstrated 334 . In the case of this trial, the peak mobility was reduced to 370 cm2·V-1·s-1 because of the thin well (5 nm)
in the enhancement mode. The obtained sub-threshold slope was 156 mV/dec. In case of nanowire, inverter circuit was
fabricated from single nanowire with InAs and GaSb14. As another possibility of InAs/GaSb nanowire, it can apply tunnel
FET16. Rapid melt growth (RMG) method 17 can also supply GaSb thin film on Si, and transistor operation by RMG was
reported18.
To realize a p-FET using an Sb-based channel, one notable problem is the interface property of metal-insulator-
semiconductor structures. At present, the best I-V properties have been reported for compressively strained InSb quantum
well p-FETs (with a gate length of 40 nm) using an HEMT structure to create a Schottky gate 331 ; a MOS structure is a
X X
preferred choice to achieve low gate leakage currents. In MOSFETs, the lowest sub-threshold slope is limited to 120
mV/dec when the gate length is 5 mm 335 . Although the interface state density is approximately 3 × 1011 cm-2·eV-1 in the
mid-bandgap region, it rises to 1 × 1013 cm-2·eV-1 near the conduction band edge. Moreover, the insulator thickness
(Al2O3) in this trial was limited to 10 nm. Thus, improvements to the method of obtaining a low interface state density
using a thinner insulator are required, because the interface state density strongly depends on the fabrication process 336 .
The requirement of having a high on-current is another problem. For a 5-mm-long MOSFET, an on-current of 70 mA/mm
was reported 335 ; however, shorter gate lengths were not studied in this report. The shortest reported gate length in a p-
X X

MOSFET is 750 nm 336 and the channel dependence shows an inverse relationship between the gate length and the on-
X X
current. In the 750 nm-long device, the highest on-current was 70 mA/mm. Moreover, the estimated on-current in the
InGaSb HEMT structure was 200 mA/mm, even when the gate length was 20 nm 337 . Taking both the significant
degradation of mobility at a high sheet carrier concentration and carrier starvation due to insufficient carrier concentration
due to poor ion implantation in a III-V semiconductor into account, the feasibility of high on currents must be verified.
21 3.2.5 N-type Ge Channel Replacement Devices

High electron mobility in bulk Ge and (111)-inversion layer, which are 2.4 times and 3.1 times the counterpart of Si,
respectively, 338 is considered as a fundamental advantage of Ge-nMOSFETs. In addition, comparable or even higher
ballistic current has been estimated for (111)Ge-nMOSFETs than for GaAs, InAs and InSb nMOSFETs due to the higher
density of states, 339 although the electron mobility Ge is less than those of III-V compound semiconductors. Not only the
performance but also the lower cost of forming CMOS circuits may be another advantage of introducing Ge-nMOSFETs
than forming III-V nFET/Ge pFET dual-channel CMOS configuration. Sub-100-nm FinFET-type Ge-nMOSFETs have
already been demonstrated 340, 341 for the counterpart of Ge-pMOSFETs in 7-nm technology node and beyound. Strain
technologies to enhance the electron mobility using source-drain stressors 342 and stress liners 343 have been demonstrated
and simulated, respectively. Simple CMOS circuits such as invertors and ring oscillators composed of Ge p- and
nMOSFETs have been demonstrated on Ge-on-insulator substrates 344 and on poly-Ge layers on SiO2/Si substrates. 345 A
circuit simulation based on TCAD results for p- and n-channel Ge-on-insulator (GOI) MOSFETs predicted that the GOI-
CMOS outperforms Si-on-insulator CMOS in various elemental circuits and conditions. 346 As a new material, GeSn
semiconductor alloy, in which direct band gap was predicted for a Sn fraction over ~10%, has been examined for CMOS
and Si-photonics devices. 347,348 Theoretical calculations for a lattice-relaxed GeSn-nMOSFET with a Sn fraction around
10% predicted slightly higher carrier injection velocity than in a Ge-nMOSFET thanks to the higher electron population
to the G valley with a lower effective mass.
The best reported inversion electron mobility at a high inversion electron density (Ns) is 429 cm2/Vs at Ns=11013 cm-2 or
488 cm2/Vs at Ns =81012 cm-2. 349,350 It is significant that these high-mobility values were observed for devices with low
EOT values of around 1 nm in terms of implementing Ge-nMOSFETs in scaled CMOS-LSIs. The scaling of gate-length
and EOT has been demonstrated independently down to 35 nm and 0.39 nm, respectively. 340 ,351 The sub-threshold swing
X X
and off-state leakage current of Ge-nMOSFETs are getting better but still slightly worse than those of Ge-pMOSFETs 352 ,
suggesting that the interface state density near the conduction-band edge should be more improved. The drain current for
scaled Ge nMOSFETs have been greatly improved during the latest 2 years and reached to ~250 mA/mm for Lg=40 nm
device at Vdd=1V. 340 However, the current drivability is still lower than that of state-of-the-art Si-nMOSFETs of the
X X
similar gate-lengths. Reducing the high parasitic resistance in the Ge-nMOSFETs is a key technology to obtain acceptable
current drivability as a counterpart of high-performance Ge-pMOSFETs. One of the major problems is the low activation
of n-type dopants in Ge, which is usually saturated up to around 1x1019 cm-3 by means of conventional ion-implantation
and RTA techniques. Theoretical calculation predicted the specific contact resistivity required in the ITRS (< 1x10-8
ohm.cm2) can be satisfied for a metal/0.7-nm-ZnO/n+-Ge contact if an electron density of over 11020 cm-3 is attained in
the Ge layer. 351 Experimentally, enhancing the activation of n-type dopants up to over 21020 cm-3 by Sb ion implantation
X X
and laser annealing processes has been achieved 353 . Reduction in a specific contact resistivity (rc) down to ~310-8
ohm.cm2 for NiGe/n+-Ge contact has been also reported by the 2-step ion-implantation technique. 354
The most significant issue for the implementation of Ge-nMOSFETs in the future high-performance CMOS technologies
is the demonstration of competing short-channel performances with conventional Si-nMOSFETs. Integration of the
contact formation processes to reduce parasitic resistance with the gate-stack formation processes to realize sub-nm-EOT
with low interface state density are key technologies. These should be consistent with integration processes for
technology generations of 7-nm node and beyond. A common gate stack process for p- and n-MOSFETs is also desirable
in terms of the cost merit against III-V/Ge dual channel devices.
22 3.2.6 Tunnel FETs

Tunneling Field Effect Transistors (TFETs) have the potential to achieve a low operating voltage by overcoming the
thermally limited subthreshold swing voltage of 60mV/decade. 355,356,357 In its simplest form, a TFET is a gated reverse-
biased p-i-n junction. There are two mechanisms that can be used to achieve a low voltage turn on. The gate voltage can
be used to modulate the thickness of the tunneling barrier at the source channel junction and thus modulate the tunneling
probability 358,359,360,361 . The thickness of the tunneling barrier is controlled by changing the electric field in the tunneling

junction. Alternatively, it is also possible use energy filtering or density of states switching. If the conduction and
valence band don’t overlap at the tunneling junction, no current can flow. Once they do overlap, current can flow.
Simulations have predicted arbitrarily steep subthreshold swings when relying on density of states switching as the
current is abruptly cutoff when the conduction band and valence band no longer overlap. 357 If phonons or short channel
X X
lengths are accounted for, simulated subthreshold swings on the order of 20-30mV/decade are typical. 362 To get high on-
state currents a small tunneling barrier, low effective mass and direct gap is needed. Group IV materials with indirect and
larger band gaps such as Si 363,364 and Ge 364 ,365,366 have smaller ON-currents. Group III-V materials like InGaAs, 367
X X
InAs, 368 ,369 and InSb 370 have higher ON-currents due to their narrower and direct band gaps. The use of staggered and
broken-gap heterojunctions, such as AlGaSb/InAs 371 and InAs/GaSb 362 , boosts the ON-current further by further
X X
lowering the tunneling barrier.

Following the review by Lu and Seabaugh, 355 there are at least 14 reports of subthreshold swings below 60 mV/decade:
X X
Most of the results are in group IV materials such as Si, 372,373,374,375,376,377 strained SiGe, 378 Si/Ge, 379 and strained Ge. 380
An In0.53Ga0.47As/In0.7Ga0.3As heterojunction TFET that has a subthreshold swing of 58 mV/decade at 1 nA/μm drain
current has been demonstrated. 381 Nanowire III-V TFETs have shown even steeper swings. A InP/GaAs
heterojunction 382 has shown 30 mV/decade at 1 pA/μm. The steepest result ever reported is in a Si/InAs heterojunction 383
of approximately 20 mV/decade. However, there are only a few data points defining this result and most of the reports of
sub-60-mV/decade swing. The most substantial sub-60-mV/decade measurements are given for Si 372 , 375 , 377 and for
X X X X X X
InGaAs. 381 The highest currents at which a subthreshold swing lower than 60mV/decade has ever been observed is at
X X
around 1-10 nA/μm. Even for low power applications, at least 1-10 μA/μm is needed. 384
The experimental results are far worse than what simulations have been predicting. The best experimental results have
typically relied on modulating the tunneling barrier thickness. Unfortunately, it seems that this mechanism typically only
gives a step subthreshold swing at low current densities. 356 Consequently, density of states (DOS) switching may be
X X
preferred. An ideal DOS switch would switch abruptly from zero-conductance to the desired on conductance thus
displaying zero subthreshold swing voltage. 385 Unfortunately, the band edges are not perfectly sharp and so there is a
finite density of states extending into the band gap. Optical measurements of intrinsic GaAs imply a band edge steepness
of 17meV/decade. 386 However, the electrically measured joint DOS in diodes has generally indicated a steepness
>90mV/decade. 387 This broadening is likely due to the spatial inhomogeneity and on heavy doping that appears in real
devices. Effectively, there are many distinct channel thresholds in a macroscopic device, leading to threshold broadening.
This can also be seen from the optical absorption in doped GaAs. When GaAs is heavily doped to 1020/cm3, the
absorption falls of at a rate worse than 60meV/decade. 388 This means that if a tunnel switch is heavily doped, it will be
unable to employ the DOS energy filtering mechanism to achieve a subthreshold swing voltage smaller than
60 mV/decade!
In transistors, the situation is even worse due to gate interface traps. The interface trap density in silicon is typically
around 1010 /cm2 while the density of states in a quantum well is only 1012 to 1013 /cm2. These traps exist in the entire
energy range of the band gap. This effectively means there is no band edge for energy filtering. Experimentally this
results in a thermally activated tunneling process. 389
To overcome these challenges we will need better material perfection than ever before. Every defect or dangling bond
can create a trap that will ruin the band edge. The defects due to doping can be eliminated by electrostatically inducing
carriers. Proof of concept devices can be made by making the device a few nanometers large so that there is a low
probability of having a trap within the device. 2D materials like MoS2 are potentially a path towards atomic perfection as
there will be no dangling bonds at the semiconductor oxide interface.
After reducing the non-ideal band edge DOS, the ideal DOS above the band edge can be optimized by taking advantage
of quantum confinement. Quantum confinement in the direction of tunneling, or reduced dimensionality on each side of a
pn junction can increase the on-state conductance by 10 to 100X. 356 ,390
X X
3.3 BEYOND-CMOS DEVICES: CHARGE-BASED
23 3.3.1 Spin FET and Spin MOSFET Transistors

Spin-transistors are classified as “non-conventional charge-based extended CMOS devices” 391 , and can be further divided
into two categories: the spin-FETs proposed by Datta and Das 392 and spin-MOSFETs proposed by Sugahara and Tanaka.
393
The structures of both types of spin transistors consist of a ferromagnetic source and a ferromagnetic drain which act

as a spin injector and a detector, respectively. Although the devices have similar structures, they have quite different
operating principles. 391 , 394 In spin-MOSFETs, the gate has the same current switching function as in ordinary transistors,
X X
whereas in the spin-FETs, the gate acts to control the spin direction by utilizing the Rashba spin-orbit interaction. Both
types of devices behave as a transistor and function as a magnetoresistive device. The important features of spin
transistors are that they allow a variable current to be controlled by the magnetization configuration of the ferromagnetic
electrodes (spin-MOSFETs) or the spin direction of the carriers (spin-FETs), and they offer the capability for nonvolatile
information storage using the magnetization configurations. These features are very useful for energy-efficient, low-
power circuit architectures that cannot be achieved by ordinary CMOS circuits. Nonvolatile logic and reconfigurable
logic circuits have been proposed using the spin-MOSFET and the pseudo-spin-MOSFETs, which are suitable for power-
gating systems with low static energy. 394 , 395, 396, 397, 398, 399, 400
X X
The read and write operations of spin-FETs 394 , 401 and spin-MOSFETs 394 , 402, 403, 404, 405 have not yet been fully
X X X X
experimentally verified. However, there has been important progress in the underlying technologies. Spin injection,
detection and manipulation are essential 13for realizing fully functional spin transistors. One key development has been
half-metallic ferromagnetic materials for highly efficient spin injector/detectors. Theories 406, 407, 408, 409 also predict that
the insertion of a tunnel barrier between the ferromagnet (FM) and semiconductor (SC) in order to optimize the interface
resistance between FM and SC is a promising method for producing highly efficient spin injection and detection.
Spin injection and detection in Si have been achieved using hot-electron transport 410 and spin-polarized tunneling. 411, 412,
413, 414, 415, 416, 417, 418
The electrical creation and detection of spin accumulation in n-type and p-type Si were demonstrated
using FM/tunnel contacts 411 , 412 , 414 , 415 , 416 , 27, 28 and FM/Schottky-tunnel-barrier contacts 419 up to room temperature (RT).
X X X X X X X X X X
Electrical spin injection into Si channels has also been demonstrated up to 500 K 413 by using a spin relaxation X X
measurement method (Hanle measurement). A relatively long spin lifetime has been observed in heavily doped Si at
RT. 412 , 415 , 416 , 28 Spin transport in SC has been studied intensively in various kinds of tunnel and channel materials.
X X X X X X
Observation of spin signals in heavily doped Ge 420, 421, 422 and GaAs 423, 424 at RT has also been reported. Another
study 425, 426 reported low-resistance spin injection and detection into Si using a graphene and a boron nitride tunnel
barriers. Local magnetoresistance signal up to RT have been observed in long channel devices with FM/MgO tunnel
barrier/Si lateral spin valve structures. 427, 428 Recently, basic read operation was demonstrated 15 at room temperature by
using spin-MOSFETs with a back-gated structure and an interface technology in which the local magnetoresistance signal
is observed at RT.
Since the reported 15 difference in the drain current between parallel and antiparallel spin configurations is very small at
room temperature, the development of half-metallic ferromagnetic materials on SC is expected to be very important. Half-
metallic Heusler alloys 429, 430, 431, 432, 433 are one of the most promising half-metallic ferromagnetic materials, because they
are relatively easy to preparation. In addition to the progresses shown in the 2013 edition of the ITRS and references, spin
injection and detection has been reported that is more efficient in SCs using a Heusler compound than in the ordinal CoFe
electrodes 434, 435, 436, 437 . More efforts to improve the qualities of Heusler compounds and FM/SC interfaces are required
in order to observe large differences in drain current between parallel and antiparallel spin configurations. It should be
noted that half-metallic materials are a required technique for spin-FETs, because the current switching function needs to
be controlled by spin precession induced by the action of the gate voltage. In spin-MOSFETs, however, since the relative
magnetization configurations of the source and drain are used to modify the output current, half-metallic materials might
not be required for spin-MOSFET.
Alternative approaches for realizing spin-MOSFETs have been proposed. 394 , 399 , 402 , 438, 439 Pseudo-spin-MOSFETs are
X X X X X X
circuits that reproduce the functions of spin-MOSFETs using an ordinary MOSFET and a magnetic tunnel junction (MTJ)
which is connected to the MOSFET in a negative feedback configuration. Although pseudo-spin-MOSFET offer the same
functionality as spin transistors, such as the ability to drive variable current, pseudo-spin-MOSFETs have larger resistance
than spin-FETs or spin-MOSFETs.
In terms of spin manipulation, spin precession of polarized carriers in the channel controlled by a gate voltage has been
observed experimentally at low temperature. 440 This result confirms that spin-orbit interaction can be controlled by gate
voltage. Materials with a strong spin-orbit interaction, such as InGaAs, InAs and InSb, are required 394 in order for the X X
channel to sufficiently induce the Rashba spin-orbit interaction. However, materials with a strong spin-orbit interaction
decrease spin life time. The use of a narrow wire channel structure 441, 442, 443 and the so-called persistent spin helix
condition. 444, 445, 446, 447, 448 has been proposed in order to increase spin life time. The experimental proof of spin injection,
detection and manipulation at RT is needed in order to create spin-FETs with a channel material having strong spin-orbit
interaction. Spin-MOSFET 12, 13 and the pseudo-spin-MOSFET 394 8, 49 use spin-transfer-torque (STT) switching, similar to
X X
the STT-MRAM that was commercialized at the end of 2012. 449

To date, long channel devices with center-to-center spacing between the FM source/drain electrodes larger than lFM-FM >
1000 nm have been investigated. To realize full read and write operations in spin-MOSFETs and spin-FETs at RT,
experimental studies using short channel devices with lFM-FMl < 100 nm are needed.
24 3.3.2 Negative Gate Capacitance FET

Based on the energy landscapes of ferroelectric capacitors, it has been suggested 450 that by replacing the standard
insulator of a MOSFET gate stack with a ferroelectric insulator of appropriate thickness, it should be possible to
implement a step-up voltage transformer that will amplify the gate voltage. Such a device is called a negative gate
capacitance FET. The gate operation in this device would lead to subthreshold swing (STS) lower than 60 mV/decade and
might enable low voltage/low power operation. The main advantage of such a device 451 is that it is a relatively
straightforward replacement of conventional FET. Thus, high Ion levels, similar to advanced CMOS would be achievable
with lower voltages. An early experimental attempt to demonstrate a low-STS NCFET, based on a P(VDF-TrFE)/SiO2
organic ferroelectric gate stack, was reported in 2008 452 and subsequently in 2010 453 in a more controlled structure. These
experiments thus established the proof of concept of <60mV/decade operation using the principle of negative capacitance.
In addition to the above experiments on polymer based ferroelectrics, negative differential capacitance was demonstrated
in a crystalline capacitor stack. 454 Essentially, it was demonstrated that in a bi-layer of dielectric Strontium Titanate
(SrTiO3: STO) and Lead Zirconate Titanate (PbxZr1-xTiO3: PZT), the total capacitance is larger than what it would be for
just the STO of the same thickness as used in the bi-layer. Note that capacitance of two serially connected capacitors
would normally be smaller than either constituent. It can be larger only if one of those constituent capacitors has a
negative differential capacitance. Thus the enhanced capacitance demonstrates the stabilization of PZT at a state of
negative differential capacitance. More recently, in a single PZT capacitor, a direct measurement of negative capacitance
was demonstrated. 455 More specifically, it was showed that when a ferroelectric capacitor is pulsed with an input voltage
it shows an ‘inductance-like’ discharging in addition to a capacitive charging.
In the last few years a significant advance has been achieved in ferroelectric materials where it has been shown that it is
possible to grow ferroelectric materials using the atomic layer deposition process (ALD) by doping the frequently used
gate dielectric HfO2 by constituents such as Zr, Al or Si. 456 Using this doped Hf based ALD ferroelectric, a number of
recent experiments have demonstrated the negative capacitance effect. 457,458,459 For example, by using HfZrO2 as a gate
dielectric <60 mV/decade was demonstrated 459 in FINFETs with Lg=30 nm for both NFET and PFET structures. Future
X X
research will have to focus on the understanding of ALD ferroelectric material so that optimized structures can be
designed for the ultra-scaled nodes.
25 3.3.3 NEMS Switch

Micro/Nano-Electro-Mechanical (M/NEM) switches are devices which employ electrostatic force to actuate a movable
structure to make a conductive path between two electrodes. Mechanical switches feature two fundamental properties
which are unattainable in MOSFETs: zero off-state leakage and zero subthreshold swing 460 . The first property provides
for zero standby power dissipation, while the second property suggests the potential to operate at very low voltage for low
dynamic power dissipation as well. Another advantage is that a mechanical switch can be operated with either positive or
negative voltage polarity due to the ambipolar nature of the electrostatic force, so that an electrostatically actuated relay
can be configured as a pull-down or pull-up device, respectively 461 . Additional advantages of mechanical devices include
robust operation across a wide temperature range 462 , immunity to ionizing radiation and compatibility with inexpensive
substrates such as glass or even plastic. Since M/NEM switches comprise only conductive electrodes and air gaps, they
can be fabricated at relatively low process temperatures in a modular fashion over CMOS circuitry. Indeed, since the
most advanced CMOS technology in production today incorporates air-gapped interconnects 463 , it is conceivable for
NEM switches to be implemented using multiple interconnect layers in an advanced back-end-of-line (BEOL) process 464 .
Potential applications for mechanical switches in a hybrid NEMS-CMOS technology include CMOS power gating 465 ,
configuration of CMOS FPGAs 466 , and non-volatile storage of information in SRAM and CAM cells 464 . X X
M/NEM switches can be fabricated using conventional planar processing techniques (thin-film deposition, lithography
and etch steps), with a final release step in which a sacrificial material such as silicon dioxide, photoresist, polyimide or
silicon is selectively removed to form the actuation and contact air-gaps. (The gap in the contact region(s) can be made
smaller than the actuation gap to reduce the switching delay and energy as well as the contact velocity for reduced wear
and contact bounce.) The smallest actuation and contact gap demonstrated to date for a functional NEM structure
fabricated using a top-down approach is 4 nm. 467 This device is a vertically actuated switch featuring a 30 nm-thick, 300
nm-wide, 1.4 mm-long doubly clamped TiW beam with a pull-in voltage of approximately 0.4 V. As expected, the off-

state current is immeasurably low and the sub-threshold swing is practically zero. However, it is a 2-terminal device, not
suitable for logic switch application.
In a digital logic circuit, it is necessary to connect multiple switches in series to implement various logic functions. To
avoid having the state of a switch depend undesirably on the state of other switches in the series stack, a reference
electrode is needed, such that the voltage applied between the control (“gate”) electrode and the reference (“body”)
electrode determines the state of the switch, i.e. whether current can flow between the output (“source” and “drain”)
electrodes 468 . By biasing the reference electrode, the operating voltage of a relay can be minimized. Similarly as for
MOSFETs, a constant-field scaling methodology can be applied to scale M/NEM switches for improved device density,
switching delay and switching energy. 469 The ultimate device density achievable may be comparable to that for
MOSFETs, in principle. However, the switching delay of a mechanical logic switch (relay) is much longer than that of a
MOSFET, because it is dominated by the mechanical (motional) delay, ~1 ns, 460 rather than the electrical
X X
(charging/discharging) delay. Because of the large ratio between the mechanical and electrical delays of a relay, an
optimized IC design should arrange for all mechanical movement to happen simultaneously, i.e. relay-based digital logic
circuits should be comprised of single-stage complex gates so that the delay per operation is essentially one mechanical
delay. 461 This generally results in significantly lower device counts as compared to the optimal CMOS implementations,
X X
especially since a relay can pass both low and high logic levels and the body electrode also can be connected to a logic
signal. By incorporating multiple pairs of source and drain electrodes into each gated structure, 470 and/or by partitioning
the gate electrode into multiple input electrodes, 471 the device count and hence the area required can be further reduced.
A variety of relay-based computational and memory building blocks have been experimentally demonstrated to
date. 472,473
Since an optimized relay-based logic circuit has a topology that is very different from that of an optimized CMOS logic
circuit, an assessment of the prospective benefits of NEM switch technology must be made at the level of complete circuit
blocks. Such circuit-level assessments (e.g. of full adder and multiplier circuits) indicate that relays can provide for more
than 10× reduction in energy per operation as compared with MOSFETs, and can reach clock speeds in the GHz
regime. 474 Thus, a major potential advantage of NEM switch technology is improved energy efficiency. Moreover, by
engineering the contact adhesive force and structural stiffness, bi-stable operation can be achieved, making scaled
mechanical switches attractive for embedded non-volatile memory applications. 475
Reliable operation is necessary for practical application of M/NEM switches in electronic circuits. Due to their extremely
small mass (less than 1 ng), mechanical vibration/shock is not an issue. Structural fatigue is easily avoided by designing
the movable electrode such that the maximum induced strain is well below the yield strength. Mechanical wear and Joule
heating at the contacting points leads to increased real contact area and eventually stiction-induced device failure. This
issue can be mitigated by using a refractory material to minimize wear and material transfer, and by reducing the device
operating voltage. (It should be noted that the higher associated contact resistance would not significantly compromise
performance, since the speed of an optimally designed relay-based logic circuit is limited by the mechanical delay rather
than the electrical delay. The on-state resistance of a logic relay can be as high as ~10 kW. 461 ) MEM switches with
X X
tungsten contacts have been demonstrated to have endurance up to 1 billion on/off cycles at 2.5 Volts, for a relatively
large load capacitance of 300 pF (i.e. exaggerated electrical delay). 476 Endurance exceeding 1016 on/off cycles is
projected for operating voltage below 1 Volt and load capacitance below 1 pF. A gradual increase in contact resistance
caused by surface oxidation or the formation of friction polymers during the course of device operation can lead to circuit
failure and is the primary reliability challenge for M/NEM logic switches today. Stable conductive oxide contact
materials and/or hermetic packaging are potential solutions to this issue.
Contact adhesive force sets the minimum spring restoring force of the movable electrode (to ensure that the switch turns
off), which in turn sets a lower limit on the electrostatic actuation force (to ensure that the switch turns on) and hence the
switching energy. For ultimately scaled contacts, the surface adhesion energy will be set either by metallic bonding or by
van der Waals force (for oxidized contacting surfaces). The minimum switching energy for a nanoscale relay is
anticipated to be on the order of 10 aJ, which compares well against the switching energy for an ultimately scaled
MOSFET. 477,478
In conclusion, M/NEM switches are intriguing candidates for ultra-low-power applications because they have negligible
off-state leakage current and abrupt switching behavior which, in principle, enables very low operating voltage. Practical
challenges remain to be solved, to achieve stable on-state resistance ((RON) and to minimize contact adhesive force within
RON limits. A circuit-level assessment of energy vs. delay performance indicates that nanoscale relays should provide for
more than 10 improvement in energy efficiency as compared with CMOS transistors, for applications requiring clock
speeds below 100 MHz. Thus, they are poised to lead a resurgence in mechanical computing for the Internet of Things.

26 3.3.4 Mott FET

Mott field-effect transistor (Mott FET) utilizes a phase change in a correlated electron system induced by a gate as the
fundamental switching paradigm 479,480 . Mott FETs could have a similar structure as conventional semiconductor FET,
with the semiconductor channel materials being replaced by correlated electron materials. Correlated electron materials
can undergo Mott insulator-to-metal phase transitions under an applied electric field due to electrostatically doped
carriers. 481,482 Besides electric field excitation, the Mott phase transition can also be triggered by photo- and thermal-
excitations for optical and thermal switches. Defects created by environmental exposure to chemicals or electrochemical
reactions can also induce Mott transition via carrier doping. The critical threshold for inducing phase change can be tuned
via stress.
Mott FET structure has been explored with different oxide channel materials 480 . Among several correlated materials that
X X
could be explored as channel materials for Mott FET, vanadium dioxide (VO2) has attracted much attention due the sharp
metal-insulator transition near room temperature (nearly five orders in single crystals) 483 . The phase transition time
constant in VO2 materials is in sub-picosecond range determined by optical pump-probe methods 484 . Device modeling
indicates that the VO2-channel-based Mott FET lower bound switching time is of the order of 0.5 ps at a power
dissipation of 0.1 µW 485 . VO2 Mott channels have been experimentally studied with thin film devices and the field effect
has been demonstrated in preliminary device structures 486, 487, 488 . Recently, prototypes of VO2 transistors using ionic
liquid gating have shown larger ON/OFF ratio at room temperature than with solid gate dielectrics like hafnia. 489, 490 The
conductance modulation happens at a slow speed however, due to the large charging time constants. 491 The possibility of
electrochemical reactions must also be carefully examined in these proof-of-principle devices due to the instability of the
liquid-oxide interfaces and the ease of cations in such complex oxides to change valence state. 491 , 492, 493 On the other
X X
hand, unlike traditional CMOS that is volatile and digital, electrochemically gated transistors exhibit non-volatile and
analog behaviors, which can be utilized to demonstrate synaptic transistors 494 and circuits 495 that mimic neural activities
in the animal brains. Voltage induced phase transitions in two-terminal Mott switches have also been implemented to
realize neuron-like devices 496 and steep-slope transistors 497 .
Experimental challenges with correlated electron oxide Mott FETs include fundamental understanding of gate oxide-
functional oxide interfaces and local band structure changes in the presence of electric fields. Methods to extract
quantitatively properties (such as defect density) of the interfaces are an important topic that have not been explored much
to date. The relatively large intrinsic carrier density in many of the Mott insulators requires the growth of ultra-thin
channel materials and smooth gate oxide-functional oxide interfaces for optimized device performance. It is also
important to understand the origin of low room-temperature carrier mobility in these materials. 481 Theoretical studies on
X X
the channel/dielectric interfacial electronic band structure are needed for the modeling of subthreshold behaviors of Mott
FETs. Understanding the electronic transition mechanisms while de-coupling from structural Peierls (lattice) distortions is
also of interest and important in the context of energy dissipation for switching.
While the electric field-induced transitions are typically explored with Mott FET, nanoscale thermal switches with Mott
materials could also be of substantial interest. Recent simulation studies of “ON and “OFF” times for nanoscale two-
terminal VO2 switches indicate possibility of sub-ns switching speeds in ultra-thin device elements in the vicinity of room
temperature. 498,499 Such devices could also be of interest to Mott memory 500 . One can in a broader sense visualize such
correlated electron systems as ‘threshold materials’ wherein the conducting state can be rapidly switched by a slight
external perturbation, and hence lead to applications in electron devices. Electronically driven transitions in perovksite-
structured oxides such as rare-earth nickelates 501,502 or cobaltates 503 with minimal lattice distortions would also be
relevant in this regard. Three-terminal devices are being investigated using these materials and will likely be an area of
growth. 504, 505, 506, 507, 508 SmNiO3 with its metal-insulator transition temperature near 130ºC and nearly hysteresis-free
transition is particular interesting due to the possibility of direct integration onto CMOS platforms. Floating gate
transistors have recently been demonstrated on silicon 509 . It has been found that non-thermal electron doping in SmNiO3
can lead to a colossal increase in its resistivity, which has been utilized to demonstrate a solid-state proton-gated transistor
with large on/off ratio 510 . Clearly, these preliminary results suggest the promise of correlated oxide semiconductors for
logic devices, while the doping process indicates slower dynamics than possible with purely electrostatic carrier density
modulation. The non-volatile nature of the Mott transition in 3-terminal devices suggest combining memory operations
into a single device and could be explored further. Architectural innovations that can create new computing modalities
with slower switches but at lower power consumption can benefit in the near term with results to date while in the longer
term transistor gate stacks need to be studied further for these classes of emerging semiconductors.

27 3.3.5 Piezotronic Logic Transduction Device

A promising approach to achieve low voltage transistors is transduction where an electrical signal is transformed into an
intermediate form internal to the logic gates and then backs to an electrical signal. This transduction allows for novel
switching mechanisms that do not have the subthreshold swing limitations of conventional MOSFETs. Piezotronic
transduction logic devices convert an electrical signal to a mechanical stress using a piezoelectric. This is then converted
back to an electrical signal using either a piezoresistor or another piezoelectric. The Piezoelectric Transistor (PET)
operates by applying a voltage to a piezoelectric pillar which expands and compresses a piezoresistive
element. 511 512 513 514 515 The piezoresistor undergoes a metal-insulator transition, lowering the resistance of the channel
and turning the device on. Theoretically, the PET is projected to switch with voltages as low as 0.1V, with a 104 on/off
ratio. By limiting the height to 20 nm mechanical speeds around 5 picoseconds should be achievable. As all materials are
in continuous contact it is expected that this structure should not have the same stiction and contact induced wear out
mechanisms of a nanomechanical relay.
An alternative piezotronic device uses a piezoelectric transformer in the gate stack. 516 A voltage is applied to one
piezoelectric, causing it to expand and squeeze a second piezoelectric. This induces a voltage across the second
piezoelectric that can be higher than the applied voltage. Multiple piezoelectric layers can be used to increase the stress in
the lowest layer and therefore the voltage amplification. A 12.5X voltage amplification has been theoretically predicted.
This voltage amplification reduces the energy to charge wires, but does not reduce the switching energy of the transistor
as the transistor itself still operates at the same voltage. AC piezoelectric voltage transformers are commercially
available, but a nanoscale DC transformer has not been demonstrated yet.
Proofs of concept Piezoelectric transistors have been fabricated. 512 , 515 In the initial demonstration, the piezoelectric
X X X X
(PZT) and the piezoresistor (SmSe) were fabricated separately on different substrates and brought together in the test
setup. The piezotronic switching mechanism was demonstrated, but 20 volts were required to achieve a 7X on/off
ratio. 512 The device could switch at 100 kHz and lasted for 2x109 cycles. A monolithically integrated device was also
X X
demonstrated with worse performance (Vg=20V only gave Ion/Ioff = 1.5). 515 The performance was limited by large
X X
dimensions and degradation of the piezoelectric polarization. In order to achieve low voltage switching, piezoelectrics
such as PMN-PT with larger piezoelectric coefficients need to be integrated in nanoscale devices. There are also
significant materials challenges in integrating both piezoelectric and piezoresistive materials in a single process. For
instance, PZT, a metal oxide is readily depleted of oxygen which is electrically leaky and SmSe oxides readily and is
unstable in air. Consequently encapsulation and compartmentalization becomes a significant design consideration.
Furthermore, the devices need to be fully scaled down to 10’s of nanometers to achieve low switching voltages. High
levels of strain in the scaled devise may also pose reliability challenges.
3.4 BEYOND-CMOS DEVICES: ALTERNATIVE INFORMATION PROCESSING
28 3.4.1 Spin Wave Device

Spin Wave Device (SWD) is a type of magnetic logic devices exploiting collective spin oscillation (spin waves) for
information transmission and processing 517,518 . The basic elements of the SWD include: (i) magneto-electric cells (e.g.
multiferroic elements) aimed to convert voltage pulses into the spin waves and vice versa; (ii) magnetic waveguides - spin
wave buses for spin wave signal propagation between the magneto-electric cells, (iii) magnetic junctions to couple two or
several waveguides, and (iv) phase shifters to control the phase of the propagating spin waves. SWD converts input
voltage signals into the spin waves, computes with spin waves, and converts the output spin waves into the voltage
signals. Computing with spin waves utilizes spin wave interference, which enables functional nanometer scale logic
devices. Since the first proposal on spin wave logic, 517 SWD concept has evolved in different ways encompassing
X X
volatile 519 and non-volatile, 520 Boolean 520 and non-Boolean, 521 single-frequency and multi-frequency circuits. 522 The
X X
primary expected advantage of SWD over Si CMOS are the following: (i) the ability to utilize phase in addition to
amplitude for building logic devices with a fewer number of elements than required for transistor-based approach; (ii)
power consumption minimization by exploiting built-in non-volatile magnetic memory, and (iii) parallel data processing
on multiple frequencies in a single core structure by exploiting each frequency as a distinct information channel.
Micrometer scale SWD MAJ gate has been experimentally demonstrated. 523 It is based on Ni81Fe19 structure, operates
within 1-3 GHz frequency range, and demonstrates ~10 signal-to-noise ratio at Room Temperature demonstrated 523 . TheX X
internal delay of SWD is defined by the spin wave group velocity (e.g. 3.1×106 cm/s in Ni81Fe19 waveguides). Power
dissipation in SWD is mainly defined by the efficiency of the spin wave excitation. Recent experiments with synthetic

multiferroics comprising piezoelectric (lead magnesium niobate-lead titanate PMN-PT) and magnetostrictive (Ni)
materials have demonstrated spin wave generation by relatively low electric field (e.g. 0.6MV/m for PMN-PT/Ni). 524 The
later translates in ultra-low power consumption (e.g. 1aJ per multiferroic switching).
Recently, it was proposed a new type of SWD - Magnonic Holographic Memory (MHM). 521 The principle of operation
X X
of MHM is similar to optical holographic memory, while spin waves are utilized instead of optical beams. The first 2-bit
MHM prototype based on yttrium iron garnet structure has been demonstrated. 525 MHM also possesses unique
capabilities for pattern recognition by exploiting the correlation between the phases of the input waves and the output
interference pattern. Pattern recognition using MHM has been recently demonstrated. 526 The potential advantage of spin
wave utilization includes the possibility of in-chip integration with the conventional electronic devices via multiferroic
elements. Also, magnonic holograms may have enormous capacity (about 1Tb/cm2) due to their nanometer scale
wavelength. According to estimates, the functional throughput of magnonic holographic devices may exceed 1018
bits/s/cm2. 521 X
There are several important milestones to be achieved for further SWD development: (i) nanomagnet switching by spin
wave (e.g. by the combined effect of the voltage-assisted anisotropy change and a magnetic field produced by the
incoming spin wave); (ii) integration of several magneto-electric cells on a single spin wave bus. In order to have an
advantage over Si CMOS in functional throughput, the operational wavelength of SWDs should be scaled down below
100nm. 520 The success of the SWD will also depend on the ability to restore/amplify spin waves (e.g. by multiferroic
X X
elements or spin torque oscillators).
29 3.4.2 Nanomagnetic Logic

Nanomagnetic Logic (NML) uses fringing field interactions between magnetic islands to perform Boolean 527 and non-
Boolean 528,529,530 logic operations. Binary information is represented via magnetization state. Most work with NML has
focused on devices that couple in-plane (iNML). Recent work has also employed devices with out-of-plane, perpendicular
magnetic anisotropy (PMA). Perpendicular magnetic logic (pNML) devices typically switch through nucleation and
domain wall propagation. 531,532 This reversal behavior is markedly different from in-plane permalloy nanomagnets, which
remain nearly single-domain during switching and rotate coherently. That said, Bhowmik et al. report using the spin Hall
effect (SHE) to clock devices with PMA. 533 With this approach, devices are placed in an in-plane, metastable state.
In all implementations of NML, externally supplied switching energy is generally needed to re-evaluate (i.e., “clock”) a
magnet ensemble with new inputs. 534 A clock modulates the energy barriers between magnetization states of the devices
that comprise an NML circuit. With iNML, subgroups of devices are usually placed in a metastable state when clocked,
and an input signal at one end is allowed to propagate through a part of said subgroup. 535 The other “end” of the
subgroup is held in a metastable state to prevent back propagation of data. While pNML devices could be clocked in a
similar manner (e.g., via the SHE 533 ), it is also possible to globally clock a large ensemble of pNML devices (e.g., with an
X X
oscillating, out-of-plane magnetic field 530 ). With either approach fine grain pipelining (and consequently improved
X X
throughput) could be achieved. (Subgroup size in iNML circuits will likely be limited by the granularity of the clock
structure.)
Notably, either NML implementation is capable of retaining state without power and could be radiation hard. Moreover,
it is possible that NML devices would dissipate less than 40 kT per switching event for a gate operation. 527 When clock
X X
overhead is considered, projections suggest that NML ensembles could still best low power CMOS equivalents in terms
of metrics such as energy delay product, etc. Finally, NML appears to be scalable to ultimate limits using individual
atomic spins. 536
(iNML): Fanout structures, 537 a 1-bit full adder, 538 etc. have been experimentally demonstrated and successfully re-
evaluated with new inputs. Both field-coupled 539,540 and spin transfer torque (STT) 541,542,543 electrical inputs have been
realized. For electrical output, multiple NML-magnetic tunnel junction hybrids 544 have been proposed and simulated.
Field based, CMOS compatible line clock structures have been used to simultaneously switch the states of multiple
magnetic islands, 545 as well as to re-evaluate NML lines and gates with new inputs. 546 Additionally, recent experiments
have considered materials-based solutions to further reduce field/energy requirements for line clock structures. Notably,
results from Li et al. 547,548 suggest that component energy metrics could be further reduced by as much as 16X.
Voltage controlled clocking – e.g., multiferroics 549 and magnetostriction 550 – have also been proposed as potential
clocking mechanisms for iNML. With respect to magnetostriction, Salehi et al. 550 suggest that stress-based clocking
X X

would lead to clock energy dissipation of just ~200 kT per device. The SHE could be employed as a path to reduced
energy clocking (i.e., 10-100X). 551
(pNML): Experimental results suggest that appropriately irradiated pNML structures 552 (to define dataflow directionality)
can be controlled by a uniform, homogeneous, oscillating, global clock field. 553 Majority gates, 554 AF-lines, 553 multi- X X
plane signal crossings, 555 and full adders 530 ,556 have all been experimentally demonstrated with this approach. Notably,
X X
Irina et al. 557 report the experimental demonstration of a three-dimensional majority gate (where input magnets reside in
different planes). Each input combination was tested 50 times at room temperature. In each instance – and given the
same clock window – the gate produced the correct output value. This could enable other compact and robust circuits
(such as the five magnet full adder discussed in Perricone et al. 558 ). When considering I/O and clocking, field coupled
electrical inputs have been demonstrated. 559 Also, large arrays of pNML devices could be controlled with on-chip
inductor structures 560 that could be coupled with a capacitance in an LC oscillator – which opens the door to adiabatic
energy recycling. Devices with PMA are also amenable to voltage controlled clocking. 561
Indeed, as noted above, small lines of pNML devices have been clocked via the SHE. 533 If 100 ps pulses are achievable,
X X
Bhowmik et al. 533 report that the energy-delay product (EDP) of a pNML-based 32-bit adder would best that of low
X X
power CMOS. Individual pNML devices have also been clocked with on-chip inductor structures at 10 MHz. 562
Simulation-based studies 562 suggest that a NAND/NOR operation would require just 2.8 aJ (assuming 200 nm x 200 nm
X X
devices and 50 MHz frequency and 10 functional layers of devices.)

Reliable switching: Work from 2008 suggests that in a soliton operating mode, dipole-to-dipole coupling could be
insufficient to prevent thermal noise from inducing premature/random switching. 563 At the device-level,
magnetocrystalline biaxial anisotropy could further promote hard axis stability of an iNML ensemble. 563 Alternatively,
X X
adiabatic switching 564 and/or field gradients could potentially mitigate the effects of premature switching. Simulations
suggest that NML circuits could tolerate some field misalignment. 565 Whether or not a circuit ultimately exhibits reliable
and deterministic switching is very much a function of how it is clocked – and requires additional study.
Fault tolerant architectures should be explored. As one example, stochastic computing (SC) could be an effective
architectural strategy. Here, serial bit streams or parallel “bundles” of wires are used to encode probability values to
represent and processes information. 566 While bit streams/wire bundles are digital, information is conveyed through the
statistical distribution of the logical values. With physical uncertainty, the fractional numbers correspond to the
probability of occurrence of a logical one versus a logical zero. Computations in the deterministic Boolean domain are
transformed into probabilistic computations in the real domain. Complex functions with simple logic are possible.
Bit flips afflict all the bits in the stream with equal probability. The result of bit flips is a mere fluctuation in the statistics
of the stream, not a catastrophic error. Thus, SC enables meaningful computation even with high device error rates. 566 X X
Furthermore, the SC architecture is pipelineable by nature. As the length of the stochastic bit stream increases, the
precision of the value represented by it also increases. This allows a system to tradeoff precision with computation time.
Thus, higher error rates that NML might experience can be tolerated by SC architectures. Pipelined SC architectures are a
natural fit for inherently pipelined NML. Venkatesan et al. 567 and Perricone et al. 568 report examples of initial circuit
design and benchmarking efforts in this area.
Energy efficient clocking: Voltage controlled clocking should continue to be pursued – not only for benefits with respect
to energy (e.g,. as articulated by Nikonov and Young 569 ), but also with respect to the fine-grained control it provides for
an NML ensemble (which is useful in reducing error rates 570 as well as architecturally 560 ). Domain-wall based switching
X X
could be another viable alternative for clocking. 571
30 3.4.3 Spin Torque Majority Logic Gate

Spin torque majority gate (STMG) relies on spin torque switching mechanism for its operation 572 . STMG consists of a
nanoscale ferromagnet, which serves as a common free layer for four fixed nanoscale ferromagnets separated from the
free layer by a tunnel barrier 573 . Three of the fixed nanomagnets serve as input terminals of STMG and one fixed
nanomagnet serves as the output terminal. Positive and negative voltage pulses applied to the input terminals cause spin
torque switching of the free layer according to the majority of the input voltage pulse polarities. The output voltage is
determined by the state of the free layer magnetization via the tunneling magneto-resistance effect.
The primary advantage of STMG over CMOS is non-volatility. The state of the free layer retains its latest state at zero
standby power. Another advantage is relatively low footprint of the majority gate.

The best reported results to date are based on micromagnetic simulations for free layer with out-of-plane magnetization
due to perpendicular magnetic anisotropy 574 . A simple cross geometry with three input and one output cross arms was
considered. Switching current of 0.05 mA was predicted for this system. The footprint for this gate was 0.01 um^2. The
switching speed is limited by the speed of domain wall propagation, which limits the switching time to approximately 0.1
ns. There are some notable recent publications or results since June 2013 575,576,577 .
Materials with higher spin torque efficiency should be developed in order to further reduce power consumption during the
gate operation. Materials with higher domain wall speed should be studied for increased speed of operation of the gate –
materials with strong interfacial Dzyaloshinskii-Moriya interaction are of particular interest. Another scheme of STMG is
based on phase locking of spin torque oscillators – micromagnetic simulations for this type of STMG are needed.
One of the highest research priorities is first experimental realization of the proposed STMG – experimental studies of the
device may reveal challenges not foreseen in simulations. Identification of materials with higher spin torque efficiency is
important for realization of a competitive STMG.
31 3.4.4 All Spin Logic

The recently proposed concept of all spin logic (ASL) 578 uses magnets to represent non-volatile binary data while the
communication between magnets is achieved using spin currents in spin coherent channels with the energy coming from
the power supply. The ASL concept is based on key scientific advancements of the last decade. 579,580,581,582,583,584,585, 586
These advancements have blurred the distinction between spintronics and magnetics, creating the possibility of a device
capable of providing a low power alternative to charge-based information processing. In particular, the two key recent
advances are (1) the demonstration of spin injection into metals 579 , 586 ,587 and semiconductors
X X X X
588
from magnetic
585 , 586
contacts and (2) the switching of a second magnet by the injected spins. X X These demonstrations suggest an all-spin
X X
approach to information processing. Magnets inject spins and spins turn magnets (digital bits) forming a closed
“ecosystem” which takes advantage of both analog (spin currents) and digital (bistable magnets) properties without the
need to convert to charge. It has been shown that ASL can potentially reduce the switching energy-delay product 589 by a
significant amount, but there are major challenges to be overcome. One is the room temperature demonstration of
switching in multi-magnet networks interacting via spin currents. The other is the introduction of high anisotropy
magnetic materials 590 into relevant experiments which can improve energy-delay. Issues such as current density and
proper choice of channel materials also have to be carefully considered. The analog nature of ASL communication can be
efficiently coupled with median function 591 to develop an architecture called Functionality Enhanced ASL (FEASL) to
realize low-power, lower delay and lower area circuits. FEASL is especially suited for adder and multiplier circuits which
are an integral part of arithmetic logic units (ALU). Moreover, it should be mentioned that ASL could also provide a
natural implementation for biomimetic systems with architectures that are radically different from the standard von –
Neumann architecture.
4. EMERGING DEVICES FOR MORE-THAN-MOORE
This section covers emerging devices that are neither targeted for Boolean logic nor memory. The target application may
be either improved information processing (Emerging Research Architectures) or extensions to information processing to
include peripheral or non-core functions (More-than-Moore). Most of ITRS covers devices expected to be used for
Boolean logic in a target application comprising a microprocessor system. The ERD chapter also covers Emerging
Research Architectures and More-than-Moore, the latter being essentially an architecture comprising a microprocessor
core surrounded by analog devices for I/O. However, the microprocessor may also be augmented by other non-core
functions, like power harvesting. This chapter will describe how new devices could raise the performance of
microelectronic systems either through more functional diversity or greater performance of the core.
Non-memory uses of the Redox Random Access Memory (ReRAM) or memristors comprise the main new device class
in this edition. ITRS sees a possibility that fabs will add capability to produce these devices. Initially, the devices will be
as a replacement for Flash in memory sticks and solid state disk drives. ITRS is responding by enhanced coverage of
ReRAM in the PIDS and ERD memory sections. However, there is nothing about the devices that confines them only for
memory. In fact, the devices can become the basis of reconfigurable logic and neuromorphic architectures and thereby
raise information processing performance substantially. ReRAM is not a good acronym because the devices are not used

as memory, so we will use the term memristor in these applications. Requirements for memristors in these applications
will be described below.
This section will continue to cover emerging devices for RF applications in the context of low-power sensor nodes.
4.1 EMERGING DEVICES FOR SECURITY APPLICATIONS
32 4.1.1 Introduction
Like performance, power, and reliability, hardware security is becoming a critical design consideration. Hardware
security threats in the IC supply chain, include counterfeiting of semiconductor components, side-channel attacks,
invasive/semi-invasive reverse engineering, and IP piracy. A rapid growth in the “Internet of Things” (IoT) only
exacerbates problems. While hardware security enhancements and circuit protection methods can mitigate security
threats in protected components, they often incur a high cost with respect to performance, power and/or cost.
Advances in emerging, post-CMOS technologies may provide hardware security researchers with new opportunities to
change the passive role that CMOS technology currently plays in security applications. While many emerging
technologies aim to sustain Moore's Law-based performance scaling and/or to improve energy efficiency 592,593 , emerging
technologies also demonstrate unique features that could drastically simplify circuit structures for protection against
hardware security threats. Security applications could not only benefit from the non-traditional I-V characteristics of
some emerging devices, but also help shape research at the device level by raising security measures to the level of other
design metrics.
At present, most emerging technologies being studied in the context of hardware security applications are related to
designing physically unclonable functions (PUFs). Post-CMOS devices 594 , 595 , 596 have been suggested as a pathway to a
PUF design. While intriguing, these approaches (i) only cover a small part of the hardware security landscape, and (ii)
PUF designs often depend on device characteristics that a designer would like to eliminate when considering utility for
logic or memory. Given the many emerging devices being studied 592 and that few if any devices were proposed with
X X
hardware security as a “killer application,” this document reports initial efforts as to how the unique I-V characteristics of
emerging transistors that are not found in traditional MOSFETs could benefit hardware security applications.
33 4.1.2 Background - Devices

While a detailed discussion is beyond the scope of this document, below we introduce the I-V characteristics and the
devices that form the basis of this review.
Tunable Polarity: In many nanoscale FETs (45nm and below), the superposition of n-type and p-type carriers is
observable under normal bias conditions. The ambipolarity phenomenon exists in various materials such as silicon 597 ,
carbon nanotubes 598 and graphene 599 . By controlling ambipolarity, device polarity can be adjusted/tuned post-
deployment. Transistors with a configurable polarity – e.g., carbon nanotubes 600 , graphene 601 , silicon nanowires
(SiNWs) 602 , and transition metal dichalcogenides (TMDs) 603 – have already been experimentally demonstrated.
As more detailed examples, SiNW FETs have an ultra-thin body structure and lightly-doped channel which provides the
ability to change the carrier type in the channel by means of a gate. FET operation is enabled by the regulation of
Schottky barriers at the source/drain junctions. The control gate (CG) acts conventionally by turning the device on and off
via a gate voltage. The polarity gate (PG) acts on the side regions of the device, in proximity to the source/drain (S/D)
Schottky junctions, switching the device polarity dynamically between n- and p-type. The input and output voltage levels
are compatible, enabling directly-cascadable logic gates 604 .
Ambipolarity is an inherent property of TFETs due to the use of different doping types for drain and source if an n/i/p
doping profile is employed 605 . By properly biasing the n-doped and p-doped regions as well as the gate, a TFET can
function either as an n- or p-type device, and no polarity gate is needed. As the magnitude of ambipolar current can be
tuned (i.e., reduced) via doping or by increasing the drain extension length 605 one can envision fabricating devices that
X X
could be better suited for logic as well as security-related applications. Given that screening length in TMD devices scales
with their body thickness, one can achieve substantial tunneling currents.

Bell-Shaped I-Vs: Emerging transistor technologies may also exhibit bell-shaped I-V curves. Symmetric graphene FETs
(SymFETs) and ThinTFETs are representatives of this group. In a SymFET, tunneling occurs between two, 2-D materials
separated by a thin insulator. The IDS-VGS relationship exhibits a strong, negative differential resistance (NDR) region.
The I-V characteristics of the device are “bell-shaped,” and the device can remain off even at higher values of VDS. The
magnitude of the current peak and the position of the peak are tunable via the top gate VTG) and back gate (VBG) voltages
of the device 606 . Such behavior has been observed experimentally 607,608 . More specifically, VTG and VBG change the
carrier type/density of the drain and source graphene layers by electrostatic field, which can modulate IDS. ITFETs or
ThinTFETs may exhibit similar I-V characteristics 609 .
34 4.1.3 Hardware security based on tunable polarity

The ability to dynamically change the polarity of a transistor opens the door to define the functionality of a layout or a
netlist post fabrication. Though one may use field programmable gate arrays (FPGAs) to achieve the same goal, FPGAs
cannot compete with ASICs in terms of performance and power, and an FPGA's reliance on configuration bits being
stored in memory introduces another vulnerability. Security primitives to be discussed can serve as building blocks for IP
protection, IP piracy prevention, and to counter hardware Trojan attacks.
Polymorphic logic gates: Polymorphic logic circuits provide an effective way for logic encryption such that attackers
cannot easily identify circuit functionality even though the entire netlist/layout is available. However, polymorphic logic
gates have never been widely used in CMOS circuits mainly due to the difficulties in designing such circuits using CMOS
technology.
In 606 ,610 , SiNW FET based polymorphic gates to prevent IP piracy was introduced. If the control gate (CG) of a SiNW
X X
FET is connected to a normal input, while the polarity gate (PG) is treated as the polymorphic control input, through
different configurations on the polymorphic control inputs, we can easily change the circuit functionality without a
performance penalty. For example, a SiNW FET based NAND gate can be converted to a NOR gate, whereas a CMOS-
based NAND cannot be converted to a fully functioning NOR by switching power and ground.
TFET-based polymorphic logic circuits have also recently been developed 611 . By properly biasing the gate, the n-doped
region, and the p-doped region, a TFET device can function either as an n-type transistor or p-type transistor. If the n-
doped region of the two parallel TFETs is connected to VDD, and the p-doped region of the bottom TFET is connected to
GND, the circuit behaves like a NAND gate. If the n-doped region of the two parallel TFETs is connected to GND and
the p-doped region of the bottom TFET is connected to VDD, the circuit behaves as a NOR gate. By using two MUXes
(one at the top and the other at the bottom) to select between the two types of connections, the circuit then functions as a
polymorphic gate where the control to the MUXes forms a 1-bit key 611 .
X X
One can readily design polymorphic functional modules using the low-cost polymorphic logic gates built from either
SiNW FETs or TFETs – that only perform a desired computation if properly configured. If some key components (e.g.,
the datapath) in an ASIC is designed in this manner, the chip is thus encrypted such that a key, i.e., the correct circuit
configuration, is required to unlock the circuit functionality. Without the key, invalid users or attackers cannot use the
circuit Thus, IP cloning and IP piracy can be prevented with extremely low performance overhead. A 32-bit polymorphic
adder using SiNW FETs has been designed and simulated. Two pairs of configuration bits (with up to 32-bits in length)
are introduced and the adder can only perform addition functionality if the correct configuration bits are provided.
Camouflaging Layout: Split manufacturing and IC camouflaging are used to secure the CMOS fabrication process, albeit
with high overhead and decreased circuit reliability. With CMOS camouflaging layouts, both power and area would
increase significantly in order to achieve high levels of protection 612 . A CMOS camouflaging layout that can function
either as an XOR, NAND or NOR gate requires at least 12 transistors. Emerging technologies help reduce the area
overhead. Recent work 606 , 610 , has demonstrated that only 4 SiNW FETs with tunable polarity are required to build a
X X X X
camouflaging layout that can perform NAND, NOR, XOR or XNOR functionality. Again, the SiNW FET based
camouflaging layout has more functionality and requires less area than CMOS counterparts – and could offer higher
levels of protection to circuit designs.
Security Analysis: Logic obfuscation is subject to brute-force attacks. If there are N polymorphic gates incorporated in
the design, it would take 2N trials for an attacker to determine the exact functionality of the circuit. As the value of N
increases, the probability of successfully mounting a brute-force attack becomes extremely low. In a preliminary
implementation of 32-bit adder, the incorporated key size is 32 bit 611 . The probability that an attacker can retrieve the
X X
correct key becomes 1/232 (2.33x10-10). Obviously, polymorphic based logic obfuscation techniques are resistant to a

conventional brute-force attack. With respect to camouflaging layouts, given that our proposed SiNW based
camouflaging layout can perform four different functions, the probability that an attacker can retrieve the correct layout is
25%. Therefore, if N SiNW FET camouflaging layouts are incorporated in a design, the attacker has to compute up to 4N
times to resolve the correct layout design. Compared to polymorphic gates based logic obfuscation, camouflaging layout
embraces higher security level but with larger area overhead.
35 4.1.4 Hardware security leveraging atypical switching behaviors

Many post-CMOS transistors aim to achieve steeper subthreshold swing, which in turn enables lower operating voltage
and power. Many devices in this space also exhibit I-V characteristics that that are not representative of a conventional
MOSFET. An example of how to exploit said characteristics for designing hardware security primitives is discussed.
Side-channel analysis, such as fault injection, power and timing analysis, allows attackers to learn about internal circuit
signals without destroying the fabricated chips. Countermeasures have been proposed to balance the delay and power
consumption when performing encryption/decryption at either the algorithm or circuit levels 613 . These methods often
cause higher power consumption and longer computation time in order to balance the side-channel signals under different
conditions. Thus, an important goal is to prevent fault injection and to counter side-channel analysis by introducing low-
cost, on-chip voltage/current monitors and protectors. Graphene SymFETs, which have a voltage-controlled unique peak
current can be used to build low-cost, high-sensitivity circuit protectors through supply voltage monitoring.
Recent work has developed a SymFET-based power supply protector 606 , 610 . With only two SymFETs, the power supply
X X X X
protector can easily monitor the supply voltage to ensure that the supply voltage to the circuit-under-protection is within a
predefined range 610 . In the event of a fault injection, the decreased supply voltage will power down the circuit rather than
X X
injecting a single-bit fault, and can thus protect the circuit from fault injection attacks. If one uses Vout as the power
supply to a circuit under protection (e.g., an adder), due to the bell-shaped I-V characteristic of the SymFET, an
intentional lowering of VDD cuts off the power supply. Thus, the sum and carry-out of the full adder output ‘0’, and no
delay related faults are induced. A similar CMOS power supply protector would require op-amps for voltage comparison.
As a result of the voltage/current monitors developed thus far, voltage/current-based fault injections can be largely
prevented. By inserting the protectors in the critical components of a given circuit design, the power supply to these
components can be monitored and protected. (See 606 for more detail.) (SymFET-based Boolean logic is also possible 614 .)
X X
4.2 DEVICES WITH LEARNING CAPABILITIES
36 4.2.1 Devices That Learn Logic Configurations

The ITRS traditionally views computer performance as the product of device performance multiplied by a factor related
to computer architecture – but it is possible to raise computer performance in a different way. An information processing
function can be realized by the placement of gates and wires on a custom ASIC or by coding the function in software and
running it on a microprocessor. The ASIC implementation will be several orders of magnitude faster and more power
efficient because moving a bit from one gate or functional block to another via a wire is much more efficient than having
a microprocessor move the bit in software, incurring as overhead the movement of hundreds of bits of instruction, opcode,
cache access, etc. to interpret the machine’s instruction set for the software. However, customers demand the ability to
change a system’s function in a split second. While the function of a microprocessor can be changed just by loading
different software, changing the function of an ASIC requires redesign and refabrication of a chip that may take a year
and cost a million dollars. The direction under discussion would implement “programmable wire.” The vision is a chip
that could be rewired and thus realize the flexibility of a microprocessor and the efficiency of an ASIC at the same time.
The Field Programmable Gate Array (FPGA) achieved the flexibility objective of the last paragraph long ago 615 , but
memristor-class devices show the possibility meeting the efficiency objective as well 616 . As illustrated in figure ERD7 617,
618
, there are several approaches in the literature where memristors are used as essentially Single Pole Single Throw
(SPST) switches that connect some form of general wiring array into specific wiring interconnections. By altering the
pattern of switches, a series of gates in a base CMOS layer can be reconnected into an arbitrary configuration. This is
essentially the same architectural concept as an FPGA, but the traditional FPGA implements a non-volatile switch with a
sizeable CMOS circuit.

The efficiency of memristors in these types of reconfigurable architectures will depend on figures of merit in Table
ERD11. Note that Table ERD11 covers a device called both a ReRAM and memristor in the ITRS. If the device is used
for memory, it is called a ReRAM and covered in other sections of the ITRS. If the same device is used in reconfigurable
logic (and also for neurmorphic applications) it is called a memristor, where it will be subject to the more stringent
requirements in Table ERD11. ITRS considers memristors an “emerging” research device for this application because the
device technology is less mature when measured against the more stringent requirements of Table ERD11.
Table ERD 11: Figure-of-merit of three reconfigurable architectures
Reconfigurable (CMOL/FPNI-like): Artificial neural network:

Memristor Memristor
Array
interconnect
Crossbar Natural neural network

deformed to show equivalence:
Synapse
Equivalent logic diagram:
SPST Dendrite
switch Axo
n
Reconfigurable-memristor functional mapping. Artificial-natural neural network mapping.

Memristors fill the role of a SPST switch in a Memristors fill the role of synapses with
crossbar wiring network. The logic circuit can be row/column wires filling the role of dendrites
“rewired” by appropriate switch/memristor settings and axons.
Figure ERD7 Two variants of learning devices for configuration
The key issues for reconfigurable logic are described below:

 The low, on resistance requirement is due to the memristor switches being in series with the signal wires. This
means the low, on resistance of the memristor Ron must be on the order of the on resistance of a drive transistor
RTon otherwise the switches will lengthen transition times and reduce the throughput of the system.
 The high, off resistance of a memristor Roff must be high enough to avoid generating too much leakage current
and thus raising static power dissipation. For a CMOS gate, the ratio of dynamic to static power dissipation will
be approximately equal to RToff/RTon ~ 10,000, where RT is the resistance of the transistors. Say the circuits in
figure Table ERD11 have f ~ 20 (for fanout) memristors on each of the array wires. In this case, f-1 of the
memristors with resistance Roff will have the system power supply voltage across their leads. Thus, f  Roff
must be on the order of RToff otherwise the memristors will significantly exacerbate leakage current and power.
37 4.2.2 Devices That Learn by Examples

Brain-inspired, neural systems are capable of performing tasks close to the level of human intellect and there is strong
indication that these systems can be made more efficient using physical devices that support learning. Computers that
learn by examples have been successfully applied to activities that have previously been beyond the reach of computers,
such as the Watson computer playing Jeopardy 619 . To the extent a new type of computer can address formerly human-
only tasks, the proper cost comparison becomes computer cost versus the cost of a human being paid a salary, working in
an office, and so forth. The Jeopardy-playing computer demonstration shows that computer methods are known for
performing at least some formerly human-only tasks, but the Watson computer was actually a 2500-core microprocessor
cluster. If we assume the artificial intelligence community has correctly identified the artificial neural network as the

necessary computational primitive for this new type of computing, it would be important to find a way to build an
artificial neural network that is more efficient than a microprocessor cluster.
The motivating example of an artificial neural network is shown in figure ERD7, where a new nanodevice fills the role of
a synapse. Many mechanisms and devices have been proposed to implement the synapse, including software emulation,
memristors, and other devices. As stated at the beginning of this section, the memristor is covered by ITRS (in the form of
ReRAM for memory) and seems destined to be much more efficient than software emulation.
The basis of learning by example is illustrated in the example in figure ERD7. The example shows a device in the
architecture configuration of a neural synapse. Information flowing across the device when it is performing its function
causes a change in the non-volatile state of the device.
Table ERD11 includes rows for three variants of neural networks:
 There are projects in the literature that simulate artificial neural networks using software models for synapse
behavior. Some models are biologically inspired 620 whereas others are device inspired 621 . The authors have tried
to capture the common behavioral attributes of the device-inspired models. The memristor models are not
derived from real memristors but may form a goal for device designers.
 The authors have tried to capture what would appear to be a reasonable target for artificial synapses.
 We include the final row on hybrid neuromorphic systems to emphasize that many projects in the literature have
to accommodated the unavailability of acceptable devices by using methods such as multiple memristors per
synapse, offline learning and other methods that produce working systems but at reduced efficiency. See
reference 622 for an example.
4.3 EMERGING DEVICES FOR LOW-POWER SENSOR NODE

The More than Moore idea is to enhance the logic family of CMOS from strictly Boolean logic to additionally include a
family of analog RF devices. In this instance, the term “family” implies both manufacturing and use of the manufactured
device. For manufacturing, the objective would be to enhance fab lines so the new RF devices could either be fabricated
with CMOS using the as few additional materials or process steps as possible. An alternative would be separate
fabrication of RF components and subsequent integration into the same package. For usage, it implies that the RF
components would operate with compatible voltages and signals. In this attempt to address the wide field of “More-than-
Moore” emerging RF devices, this section is focused on a few devices and functional blocks.
38 4.3.1 Graphene RF Transistors

Owing to the potentially very high carrier velocity of graphene, RF transistors using this material possibly can reach very
high unity current gain cutoff frequency, fT: graphene RF transistors have been reported with higher fT and lower fMax than
Si transistor at the same gate length. A cutoff frequency of 300 GHz is reported using Co2Si-nanowire gate and an
exfoliated graphene. 623 A fT of 240 GHz was reported using wafer scale epitaxial graphene 624 and a fT of 200 GHz was
reported using a CVD-grown graphene layer 625
To obtain higher fT, the device configuration needs to be optimized. The source and drain of the graphene transistor are
usually defined by depositing a metal film, which can induce parasitic capacitances: in top-gate configuration, where
source, drain and gate are on the same side of graphene channel, gate-source or gate-drain capacitances can be large,
which results in a reduced fT. However, in back-gate configuration, where the gate is on the opposite side of the graphene
layer than the source and drain, the gate-source or gate-drain capacitances could be lower even for an overlapped situation
(Lgs<0). CVD graphene can be fabricated easily on the back-gate configuration; epitaxial graphene could not. Methods to
fabricate a local embedded back gate on a SiC wafer are, however, suggested, although high growth temperature could
make it difficult 626 . An inverted graphene integration process, where transistor gate/source/drain and passive circuit
components were pre-fabricated before the transfer of CVD graphene, has been demonstrated on 200mm CMOS
compatible process 627 . Graphene trasnsistors achieved fT and fmax of 17GHz and 15.2GHz, respectively.
Since the cutoff frequency is inversely proportional to the channel length, the limit of fT in graphene transistor has not
been fully assessed by the reported wafer scale devices. Using a nanowire gate instead of a patterned metal, fT was
estimated down to a 45 nm channel length based on transition time. High Fermi velocity of carriers in graphene, resulting

in high drift velocity (~ 4 x 107 cm/s) in a channel, makes 1THz fT achievable for a sub-70 nm channel length device 628 .
This is greater than sub-30 nm channel length of HEMT and Si RF transistors 629 .
The unity power gain frequency or maximum frequency of oscillation, fMax, which is around 10-50 GHz even for devices
with fT of 200 GHz, could be increased by improving the device structure and reducing the parasitics. This is a field
which is presently less investigated than the intrinsic properties of graphene.
39 4.3.2 Spin Torque Oscillators

Spin transfer torque in metallic spin-valves and magnetic tunnel junctions using nano-sized magnetic multilayer structures
can drive uniform precession of the free layer magnetization under external magnetic field conditions 630,631 . When
combined with the giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR) effect, this precession
produces voltage responses that make those magnetic multilayers high frequency spin torque oscillators. The oscillation
frequency in a spin torque oscillator can be tuned by adjusting the electric current or the external magnetic field. Due to
its high compactness, extremely wide tunability, and compatibility with standard CMOS process, spin torque oscillator
has the potential to be an agile RF oscillator 632,633
Currently, oscillation frequencies ranging from several hundred MHz to tens of GHz have been demonstrated depending
on the magnetic structures, magnetic field and input current levels 634 . The output power in spin torque oscillators based
on metallic spin valve structures is about several hundred pW and it was improved up to about tens of nW in MTJ based
spin torque oscillators 635,636 . Despite these experimental advancements in spin torque oscillators, there are several
challenges to be overcome for the practical application of spin torque oscillator. These challenges include 1) auto-
oscillation structures, 2) increase of output power, and 3) high spectral purity (low phase noise).
Auto-oscillation structures are required to eliminate the need for an external magnetic field that is used in most recent
experimental demonstrations. Spin torque oscillator structures with a perpendicular polarizer and a planar free layer 637 ,
vortex magnetization state in free layer 638 , and wavy angular dependence of spin torque 639 have been suggested.
For the spin torque oscillator to be useful, the output power of RF oscillation should be improved above a few microwatts.
Although achieving higher magnetoresistance (MR) ratios through high spin polarization of magnetic layers or large
precession angle of free layers could be a first approach for higher output power, phase locking of many weakly coupled
oscillators is further needed for a sufficient increase of the output power. Many theoretical predictions and experimental
demonstrations of synchronization of electrically connected spin torque oscillators have been reported so far 640,641,642 .
Among the remaining challenges, obtaining spectral purity that is compatible to the levels of existing current oscillator
devices may be the biggest obstacle for the spin torque oscillators to be applied in the telecommunication field. Issues in
the spin torque oscillation linewidth are reportedly coming from the lack of temporal coherence 643 and from the non-
linearity of the oscillation frequency 644,645 . The adoption of PLL circuits and synchronization of several spin torque
oscillators can be one of the solutions for the higher spectral purity.
40 4.3.3 NEMS Resonators

There is an increasing interest to miniaturize and integrate the off-chip RF components, especially the quartz crystal used
in the reference oscillator whose quality factor Q (>104-105) and temperature stability (better than 1 ppm/°C) are difficult
to achieve with integrated devices. The quality factors of integrated LC-tank circuits are limited by the poor quality factor
values of integrated inductors and capacitors (from 10’s to 100’s). As a consequence, the most promising solutions to
miniaturize reference oscillators with uncompromised quality factors 646 are related to the classes of vibrating devices.
Among the most promising of these vibrating structures are the capacitively transduced micro- and nano-electro-
mechanical (M/NEM) resonators. In recent years tremendous progress has been achieved in the frequency x quality factor
product, the main figure of merit for MEM/NEM resonators. The general trend of increasing their resonance frequency to
values exceeding the GHz domain pushed such resonators towards very small, very stiff and low mass NEM systems.
However, their ability to conserve a high-Q at low dimensions is questionable when the main energy dissipation
mechanisms are the gas friction, the clamping and surface losses 647 . Another important issue is how the (in)stabilities of
these resonators scale with dimensions as the effects of fluctuations in numbers of photons, phonons, electrons and
adsorbed molecules can significantly affect the noise characteristics 648

41 4.3.4 NEM resonators based on silicon nanowires, carbon nanotubes and graphene
At micrometer scale, recent successful demonstrations of very high frequency resonators are the extensional wine-glass
resonators with frequencies ranging from 400 MHz to 1.5 GHz (and Q > 3700) 649 and the dielectrically actuated and
piezoresistively sensed 4.41 GHz silicon bar resonator exploiting internal dielectric actuation 650 . Piezoresistive
sensing 651 of capacitively actuated resonator exceeding 4GHz with Q>8000 and using the 9th harmonic longitudinal
model was implemented.
Very high frequency (VHF) NEM resonators were described using platinum nanowires, resonating at frequencies higher
than 100MHz and with a quality factor of 8500 at 4K 652 . The same group later reported 653,654 VHF NEM resonators based
upon single-crystal Si nanowires. Carbon nanotubes attracted major interest for building NEM resonators, due to their
high stiffness (Young’s Elastic Modulus, E, near 1Tpa), low density, defect-free structure and ultra-small cross section.
Resonator responses have been 655 reported varying from 3 to 200MHz with voltage-tunable characteristics, in CNTs with
1-4nm in diameter, suspended over a trench. The NEM resonator with resonance frequencies up to ≈ 4 GHz were reported
with a similar CNT device loaded in an abacus style with inertial metal clamps, yielding very short effective beam
lengths 656,657 . One issue of such small vibrating SiNWs and CNTs is the early onset, at very low applied power, of non-
linearities characterized by frequency bistability arising from the effect of tension built-up in the wire at large vibration
amplitudes.
Recently, graphene material attracted further attention for its extremely high strength, stiffness, and thermal conductivity
along the basal plane. In Ref. 658 exfoliated graphene sheets are suspended to form two-dimensional NEM resonators with
resonance frequencies from 1MHz to 170MHz.
42 4.3.5 NEM resonators based on resonant gate or vibrating body transistors

The capacitively transduced signals of MEM resonators are very small and the impedance matching can be limiting. The
movable gate and body FET transistor structures can operate as M/NEM resonators, with the main difference that the
output is the drain current of the transistor, offering the possibility of building active resonators.
Resonant gate transistors were reported with out-of-plane AlSi resonant gate MOSFETs 659,660 and with in-plane resonant
silicon gate transistors 661 . Aggressively scaled versions of the in-plane resonant gate transistors have been reported 662
based on Silicon-On-Nothing technology to achieve sub-100nm gaps and 400nm-thick single crystal resonators with a
front-end process. The lateral MOS transistor could suffer from poor carrier mobility due to the roughness of the
vertically etched sidewalls and have shown very little gain, but can be integrated with advanced CMOS 663 to minimize
the influence of parasitic capacitances.
An alternative resonant transistor, called Vibrating-Body FET (VB-FET) has been proposed 664,665 ; the movable body
modulates both the inversion or accumulation charge in the lateral channels and the piezoreistance of the structure (carrier
mobility and mass). Silicon nanowires show an unusually large piezoreistance effect compared with bulk Si. An
outstanding gain of more than +30dB for the output signal was obtained in micrometer scale double-gate VB-FET when
the output is taken from the transistor drain. Moreover, the device motional resistance is reduced from 16k to below
100 which enables excellent conditions for 50 matching in RF applications.
Another active resonator has been proposed 666 by using the mechanical strain rather than an electric field to modulate the
conductivity of the silicon. This resonator can provide a gain higher than unity at 15MHz, similarly to the VB-FET.
43 4.3.6 RF Mixers
An RF mixer is an important building block of the RF front end and many emerging solutions seek attention 667
Resonant tunneling diodes were explored for decades. Owing to their negative differential resistance and fast response,
they had some potential in the RF domain, and subharmonic mixers were demonstrated 668,669 . The potential advantages of
such an approach are a wide range of operating temperature, frequencies ranging up to 10 THz, and a reduced noise figure
due to RTD shot noise suppression. While this field wasn’t very active in the recent years it could regain interest due to
the increased demand for THZ applications and the coming integration of III-V materials on Si.
For the same reason single electron transistors were considered with resonant frequencies in the range 1 – 10 GHz. A
SET-based mixer with fully tunable band selection from 0 to 300 MHz was demonstrated but at cryogenic
temperature 670,671 .

Recently the ambipolar I-V characteristic of the graphene transistor which mimics the response of full-wave rectifier has
been used to demonstrate a frequency-doubler circuit 672,673 . A double balanced RF mixer integrating four GFET has been
demonstrated on 200mm CMOS wafers, with significantly improved linearity over single-GFET mixers 674 .
Finally the nonlinear I-V characteristic of a carbon nanotube can be used to demodulate AM signal. However the
demonstrations were limited to <100 kHz due to the external bias circuitry and to <2 GHz due to intrinsic parasitics (chip
bond pads, etc.) 675,676 .
5. EMERGING RESEARCH ARCHITECTURES
5.1 Introduction
This chapter covers two areas: Storage Class Memories and Emerging Computing Architectures. Storage class memories
refers to large solid state memories intended to replace some or all of the traditional DRAM-disk hierarchy. Emerging
Computing Architectures refers to non-traditional computer architectures intended to replace or supplement traditional
architectures. Both sections include a review of the state of the art and a summary of open challenges.
5.2 STORAGE CLASS MEMORIES

5.2.1. INTRODUCTION
In traditional computing, SRAM is used as a series of caches, which DRAM tries to refill as fast as possible. The entire
system image is stored in a non-volatile medium, traditionally a hard drive, and is then swapped to and from memory as
needed. However, this situation has been changing rapidly. Application needs are both scaling in size and evolving in
scope, and thus are rapidly exhausting the capabilities of the traditional memory hierarchy.
By combining the reliability, fast access, and endurance of a solid-state memory together with the low-cost archival
capabilities and vast capacity of a magnetic hard disk drive, Storage Class Memory (SCM) offers several interesting
opportunities for creating new levels in the memory hierarchies that could help with these problems. SCM offers compact
yet robust non-volatile memory systems with greatly improved cost/performance ratios relative to other technologies. S-
class SCM represents ultra-fast long-term storage, similar to an SSD but with higher endurance, lower latencies, and byte-
addressable access. M-class represents dense and low-power nonvolatile memory at speeds close to DRAM.
In order to implement SCM, both the emerging memory technologies discussed in Section 2 as well as new interfaces and
architectures will be needed, in order to fully use the potential, and to compensate for the weaknesses of various new
memory technologies. In this section, we explore the Emerging Research Architecture implications and challenges
associated with Storage Class Memory.
5.2.2. CHALLENGES IN MEMORY SYSTEMS

Current memory systems range in size from Gigabytes (low-volume ASIC systems, FPGAs and mobile systems) through
Terabytes (multicore systems that manage execution of many threads for personal or departmental computing), to
Petabytes (for database, Big Data, cloud computing, and other data analytics applications), and up to Exabytes (next-
generation, exascale scientific computing). In all cases, speed (both in terms of latency of data reads and writes as well as
bandwidth), power consumption, and cost are absolutely critical. However, the importance of other system aspects can
vary across these different application spaces.
Table ERD12 presents a summary of memory needs by application space. The table is organized as a cross-matrix of
application drivers indexed against desired memory properties. It is not indexed by year but is meant to be read in the
context of computing in the 2015 – 2025 timeframe.

Historically, roughly one-third of the power in a large computer system is consumed in the memory sub-system 677 . Some
portion of this is refresh power, required by the volatile nature of DRAM. As a result, modern data servers consume
considerable power even when operating at low utilization rates. For example, Google 678 reports that servers are typically
operating at over 50% of their peak power consumption even at very low utilization rates. The requirement for rapid
transition to full operation precludes using a hibernate mode. As a result, a persistent memory that did not require constant
refresh would be valuable.
Many computer systems are not running at peak load continuously. Such systems (including mobile or data analytics)
become much more efficient if power can be turned off rapidly while maintaining persistent stored data, since power
usage can then become proportional to the computational load. This provides additional incentive for the nonvolatile
storage aspect of SCM.
Some applications such as data analytics and ASIC systems can benefit from having associative memories or content
addressability, while other applications might gain little. Mobile systems can become even more compact if many
different memory tiers can be combined on the same chip or package, including non-volatile M-class or even S-class
Storage Class Memory.
Total cost of ownership is influenced by cost-to-purchase, cost-to-maintain, and system lifetime. Current cost-to-purchase
trends are that Hard Disk Drives (HDD) cost roughly an order of magnitude less per bit than flash memory, which in turn
costs almost an order of magnitude less per bit than DRAM. However, cost-to-purchase is not the only consideration. It is
anticipated that S-class SCM will consume considerably less power than HDD (both directly and in terms of required
cooling), and will take up considerably less floorspace. By 2020, if the main storage system of a data center is still built
solely from HDD, the target performance of 8.4 G-SIO/s could consume as much as 93 MW and require 98,568 square
feet of floor space 679 . In contrast, the improved performance of emerging memories could supply this performance with
only 4 kW and 12 square feet. Given the cost of energy, this differential can easily shift the total cost advantage to
emerging memory, away from HDD, even if a cost per bit differential still exists.
These requirements have led to considerable early investigation into new memory architectures, exploiting emerging
memory devices, often in conjunction with DRAM and HDDs in novel architectures. These new Storage Class Memories
(SCM) are differentiated as whether they are intended to be close to the CPU (M-class), or to largely supplement the hard-
drives and SSDs (S-class).
The emergence of SCM leads to the need to resolve issues beyond the device level, including software organization, wear
leveling management, and error management. Because of the inherent speed in SCMs, software can easily limit the
system performance. All types of IO software – from the filesystem, through the operating system and up to applications
– will need to be redesigned in order to best leverage SCMs. The number of software interactions must be reduced and
disk-centric features will need to be removed. Inefficiencies buried deep within conventional software can account for
anywhere from 70% to 94% of the total IO latency 680 . It is likely to be valuable to give application software direct access
to the SCM interface, although this can then require additional considerations to protect the SCM device from malicious
software. However, this approach is not typically used in current operating systems that use some form of File Address
Table as an intermediate index mechanism.
Access patterns in data-intensive computing can vary substantially. While some companies continue to use relational
databases, others have switched to flat databases that must be separately indexed to create connections amongst entries. In
general, database accesses tend to be fairly atomic (as small as a few Bytes), and can be widely distributed across the
entire database. This is true for both reads and writes, and since the relative ratio of reads and writes varies widely by
application, the optimality of any one design can depend strongly on the particular workload.
A specific issue that arises with SCMs is wear leveling. While DRAMs and HDDs can support a large number of writes
to the same location without failure, most of the emerging non-volatile memory device technologies cannot. Thus there is
a need for low-overhead mechanisms to “spread” the writes around uniformly, generally referred to as “wear leveling”.
An important issue in any file system is that certain data (such as metadata) is written to quite frequently. It is important
to make sure that such storage locations are not subject to fast wearout, e.g. by using a more robust technology for such
portions of the file system.
Error management is a broader problem than just wear leveling. While DRAM has traditionally benefited from simple
methods such as ECC and EDCs, flash with its large page sizes and slow accesses can afford more sophisticated
algorithms such as LDPC. Unfortunately, SCM will need more error correction than DRAM but will need faster error
correction than flash, especially for M-class SCMs. This is an open area for research. Some possible options include

exploring codes that exploit specifics of error patterns, such as Tensor codes, and the use of in-situ scrub 681 , where
accumulated errors are periodically eliminated so that one or two bit error correction can remain sufficient.
Table ERD12. Anticipated Important Properties of Emerging Memories as driven by application need.
5.2.3. EMERGING MEMORY ARCHITECTURES FOR M-CLASS SCM

Storage Class Memory architectures that are intended to replace, merge with, or support DRAM, and be close to the CPU,
are referred to as M-type or Memory-type SCM (M-SCM). The required properties of this memory have many similarities
to DRAM, including its interfaces, architecture, endurance, and read and write speed. Since write endurance of an
emerging research memory is likely to be inferior to DRAM, considerable scope exists for architectural innovation. It will
necessary to choose how to integrate multiple memory technologies to optimize performance and power while
maximizing lifetime. In addition, advanced load leveling that preserves the word level interface and suitable error
correction will be needed.
The interface is likely to be a word-addressable bus, treating the entire memory system as one flat address space. Since
the cost of adapting to a new memory interfaces is sizeable, an interface standard that could support multiple generations
of M-SCM devices would be highly preferred. Many systems (such as in automobiles) might be deployed for a long time,
so any new standard should be backward-compatible. Such a standard should compatible to DRAM interfaces (though
with simpler control commands), and should reuse existing controllers and PHY (physical layers), as well as power
supplies, as much as possible. It should be power efficient, e.g. supporting small page sizes, and should support future
directions, such as 3D Master/slave configurations. The M-SCM device should indicate when writes have been completed
successfully. Finally, an M-SCM standard should support multiple data rates, such as a DDR-like speed for the DRAM
and a slower rate for the NVRAM 682 .
While wear-leveling in a block-based architecture requires significant overhead to track the number of writes to each
block, simple techniques such as “Start-Gap” Wear-Leveling are available for direct-byte-access memories such as PCM
(Phase Change Memory) 683 . In this technique, a pair of registers are used to identify the location of the start point and an
empty gap within a region of memory. After some threshold number of write accesses, the gap register is moved through
the region, with the start register incrementing each time the gap register passes through the entire region. Additional
considerations can be added to defend against detrimental attacks intended to intentionally wear out the memory.
With such techniques, even an M-class SCM that is markedly slower than DRAM can offer improved performance by
increasing available capacity and by reducing the occurrence of costly cache misses 684 . With proper caching, a carefully-
designed M-SCM system could potentially even match DRAM performance despite its lower device latency 685 . The
presence of a small DRAM cache helps keep the slower speed of the M-class SCM from affecting overall system
7
performance in many common workloads. Even with an endurance of 10 , system lifetime has been shown to be on the
order of 3 years. Techniques for reducing the write traffic back to the SCM device can help improve this by as much as a
factor of 3 under realistic workloads.
Direct replacement of DRAM with a slightly slower M-class SCM has also been considered, for the particular example of
STT-MRAM 686 . Since individual byte-level writes to STT-MRAM consume more power than in DRAM, a direct
replacement is not competitive in terms of energy or performance. However, by re-architecting the interaction between
the output buffer and the STT-MRAM, unnecessary writes back to the NVM can be eliminated, producing a sizeable
energy improvement at almost no loss in performance. However, the use of write buffers means that the device must be
able to complete all writes back to non-volatile memory in the event of power loss. Integrating PCM into the mobile
environment, together with a redesigned memory management controller, is predicted to deliver a six times improvement
in speed and also extends the memory lifetime six times 687 .
Caches are intended to ensure that frequently-needed data is located near to the processor, in nearby, low-latency
memory. In storage architectures, “hot” or frequently-accessed data is identified and then moved to faster tiers of storage.
However, as the number of tiers or caches increases, a significant amount of time and energy is being spent moving data.
An alternative approach is to completely rethink the hardware/software interface. By organizing the computational system
around the data, data is not brought to the processor but instead processing is performed in proximity to the stored data.
One such emerging data-centric chip architectures, termed “Nanostores,” 688 was predicted to offer 10-60x improvements
in energy efficiency 689 .

Given the slower than expected deployment of scaled emerging devices for M-class SCM, several projects have employed
large amounts of DRAM as a surrogate for and M-class SCM. Though Bresniker et.al. describe a computer enabled by a
large non-volatile “Universal memory” 690 , press reports indicate that early commercial machines will be built with large
amounts of DRAM. They point out that an NVM version allows “occasionally-on computing” but could have the down-
side that new types bugs might appear as OSs and programs effectively run indefinitely and can’t “re-crate their memory
state representations each time they start”. New applications and algorithms might emerge as a result of keeping data in
perpetuity, or at least for a long time. Like others, they point out the problems that arise as NVMs
Table ERD13 presents the likely desirable properties of M-class SCM.
Table ERD13. Likely desirable properties of M (Memory) type and S (Storage) type Storage Class Memories
5.2.4. EMERGING MEMORY ARCHITECTURES FOR S-CLASS SCM

S (Storage) type SCMs are intended to replace or supplement hard-disk drives as main storage, much like current Flash-
based SSDs, but with even more IOPs (I/O operations per second). Their main advantage will be speed, avoiding the seek
time penalty of main drives. However, to succeed, their total cost of ownership needs to approach that of HDDs. Research
issues include whether the SCM serves as a disk cache or is directly managed, how load leveling is implemented while
retaining a sufficiently fast and flexible interface, how error correction is implemented, and what is the optimal mix of
fast-yet-expensive and slow-yet-inexpensive storage technologies.
The effective performance of flash SSD, itself slower than S-SCM, has been strongly affected by interface performance.
The standard SATA (Serial Advanced Technology Attachment) interface, which is a commonly used interface for SSD,
was originally designed for HDD, and is not optimized for flash SSD 691 .
One possible introduction of these new memory devices to the market would be as hybrid solid-state discs, where the new
memory technology complements the traditional flash memory to boost the SSD performance. Experimental
implementations of FeRAM/flash 692 and PCRAM/flash 693 have been explored. It was shown that the PCRAM/Flash hybrid
improves SSD operations by decreasing the energy consumption and increasing the lifetime of flash memory.
Additional open questions for S-SCM include storage management, interface and architectural integration, such as
whether such a system should be treated like a fast disk drive, or as a managed extension of main memory. To date, disk-
like systems built using non-volatile memories have had disk-like interfaces, with fixed-sized blocks and a translation
layer used to obtain block addresses. However, since the file system also performs a table lookup, some portion of SCM
performance is sacrificed. In addition, non-NAND-flash SCMs have randomly accessible bits and do not need to be
organized as fixed-size blocks 694 .
While preserving this two table structure means that no changes to the operating system are required to use, or to switch
between, new S-SCM technologies, the full advantages of such fast storage devices cannot be realized. There are two
alternative approaches to eliminate one of these lookup tables. In the Direct Access mode, the translation table is
removed, so that the operating system must then understand how to address the SCM devices. However, any change in
how table entries are calculated (such as improvements in garbage collection or wear-leveling) would then require
changes in the operating system.
In contrast, in an Object-Based access model, the file system is organized as a series of (key, value) objects. While this
requires a one-time change to operating systems, all specific details of the SCM could be implemented at a low level. This
model leads to greater efficiency in terms of both speed and effective “file” density, and also offers the potential for
enhanced reliability.
Another issue for SCM-based systems will be addressing the asymmetry between read and write in devices such as PCM
or other emerging non-volatile memories 695 . Such asymmetry can affect the ordering and atomicity of writes, and needs
to be taken into consideration in system or algorithm design 696 . Atomicity is critical for operations such as database
transactions properties, so that either all of a series of related database operations occur, or none of them occur.
Longer write latencies, in technologies such as PCM, can be compensated by techniques such as data comparison
writes 697 , partial writes 698 , or specialized algorithms/structures that trade writes for reads20699 700 . (These last set of
techniques can also help reduce endurance problems.)Write ordering and atomicity problems can be finessed by hardware
primitives. These can either be existing hardware primitives – cache modes (e.g., write-back, write-combining), memory

barriers, cache line flush 701 702 703 – or newly-proposed hardware primitives, such as atomic 8-byte writes and epoch
barriers 704 70520 .
Even first-generation PCM chips, although implemented without a DRAM cache, compare favorably with state-of-the-art
SSDs implemented with NAND Flash, particularly for small (<2KB) writes and for reads of all sizes 706 . The CPU
overhead per input-output operation is also greatly reduced. Another observation for even first-generation PCM chips is
that while the average read latency is similar to NAND Flash, the worst-case latency outliers for NAND Flash can be
many orders of magnitude slower than the worst-case PCM access. This is particularly important considering that such S-
class SCM systems will typically be used to increase system performance by improving the delivery of urgently-needed
“hot” data.
Another new software consideration for both S- and M-class SCM is the increased importance of avoiding memory
corruption, either through memory leaks, pointer errors, or other issues related to memory allocation and deallocation 707 .
Since part of the memory system is now non-volatile, such issues are now pervasive and may be difficult to detect and
remove without affecting stored user data.
General libraries and programming interfaces – such as NV-heaps 708 , Mnemosyne 709 ,NVMalloc 710 ,and recovery and
durable structures 711 – have been proposed to expose SCM as a persistent heap and thus ease its adoption. Schemes for
filesystem support have been developed to transparently utilizes as byte-addressable persistent storage, including Intel’s
PMFS 712 ,BPFS, FRASH 713 , ConquestFS 714 , and SCMFS 715 .
Table ERD13 presents the likely desirable properties of S-class SCM.
5.3 EMERGING COMPUTING ARCHITECTURES
5.3.1 INTRODUCTION
Emerging devices are creating opportunities for new computing machines, including machines with non-conventional
architectures. At the same time, designers are developing emerging architectural concepts, such as neuro-inspired
architectures that incorporate conventional computing devices. This sub-chapter includes a survey of a number of these
technologies, together with a summary of open challenges.
Figure ERD8 presents a chart that summarizes and categorizes computing architectures, both conventional and
unconventional. The chart is organized along multiple dimensions. Horizontally, the chart is first organized with
“Program-Centric” architectures on the left and “Data-Centric” architectures on the right. “Program centric” refers to
processors wherein the detailed design, including every step of the program flow, is dictated by the designer. Program-
centric processors are further split into conventional stored program Von Neuman machines and non-Von Neuman
processors that are not driven from a stored software program. “Data-centric” refers to processors wherein some of the
details of the final “design” are driven by the data that is passed through the system during a training step, either by the
system manufacturer at the factory, by a systems integrator before shipping to customers, or even by customers in the
field. For example, the weights in a neural network are learned for a recognition task by showing the network many data-
examples. The final horizontal dimension is the split of each column into CMOS and non-CMOS device enabled
categories.
Vertically, the table is divided by a dashed red line between “deterministic” and “non-deterministic” computing.
“Deterministic” computing refers to fixed-precision (whether floating or fixed point) and low bit-error-rate compute
models. “Non-deterministic” computing refers to computing that does not rely on these paradigms, and the compute
solution has some sort of probabilistic nature to it. A vertical distinction that is not specifically marked are that the top
band in the deterministic row largely use logic devices while the lower entries in the band largely use emerging memory
devices as crossbars. The grey boxes imply a neural inspired architecture.
In the next few sections, emerging program-centric and data-centric architectures are each surveyed in turn, followed by a
discussion of crossbar trends. Table ERD14 summarizes some categories of non-CMOS emerging architectures.
Table ERD14. Categories of non-CMOS emerging architectures

Figure ERD8. Categories of computing architectures.
5.3.2 Emerging Program-centric Architectures
Program-centric architecture are largely designed and programmed in the conventional way – all design is human
directed, and processors are programmed using a programming language. As a result, the performance and components of
the system are known before any data is presented to the system. At a circuit level, most SCM candidates (see above
sections) are configured as one transistor, one “resistive memory device” (1T1R) cells. Using a high on-off ratio
transistor as an access device simplifies the overall design but at the expense of area. A long-standing goal has been to
create a memory array that consists of memory devices only (1R), i.e. a passive crossbar, or that only needs a two
terminal diode (or switch) as an access device (1AD1R or 1S1R). The latter needs unipolar device operation.
Outstanding challenges towards this goal has been (1) controlling the “sneak current path” so that the sum of the currents
in the “off” devices in an array do not become comparable to the “on” current which we are trying to detect, and (2) the
need for the access device to deliver sufficient write current with little power wasted on unselected devices. Together
with high device variability, these issues limit the achievable size of a buildable array. Hamdioui et al. 716 summarizes
these issues and presents some potential circuit level solutions. Narayanan et.al. 717 explores the limits for arrays with a
specific type of access device. They explore arrays in the 1 Mb range and show that array size is mainly limited by write
power.
Ternary Content Addressable Memories (TCAM) enable lookup via data value, rather than address, and are very useful in
many applications. However, each cell requires 14 transistors or more, limiting the density and power consumption.
There have been numerous simulation and physical demonstrations of smaller TCAM cells enabled by MTJs or RRAMs,
and these typically require 6 CMOS transistors or less (and 2 resistive devices). For example, Li et.al. Demonstrate a 2T-
2R 1Mb TCAM based on CMOS and PCM 718 .
On the processor side, the concept of Non-Volatile (NV) computing relies on using non-volatile memories within the state
registers inside the CPU. This enables the processor to be quickly placed into, and taken out of a full sleep mode, thus
saving power overall despite the extra power required for the NV write. For example, Liu et.al. 719 demonstrate using NV
flip-flops and NV SRAM to achieve a 170 ns restore time.

“Next switch” refers to using an emerging logic device to replace a CMOS switch in what would otherwise largely be a
conventional design. Examples include all-spin logic, and employing TFETs for low voltage circuitry. Since MTJs have
a high write current, compared with a CMOS FET, their use in program-centric computers is probably limited to enabling
fast all-sleep modes. In contrast, all-spin devices have potential for low power computation but the level of device
maturity is very low, and benchmarking results to date indicate poor potential for all spintronic and ferroelectric devices
to have a better energy-delay product than CMOS 720 .
One “next switch” for which there is a lot of current interest is to use Josephson Junctions to build superconducting
circuits operating at very low temperatures. Devices and circuits have been demonstrated. Even though the devices need
to be cooled to 4 K, there is potential for a better energy-delay product than CMOS due to the expectation of very high
speed operation 721 . One approach is to build relatively “conventional” logic using Josephson junctions modulating
single-flux-quantum (SFQ) voltage pulses. A very different approach is to build a flux qubit that operates below 0.1 K
and supports the superposition of two quantum states. An algorithm referred to as “quantum annealing” can be used to
solve discrete optimization problems during which the qubits settle to one state.
Several new concepts are under active exploration for program-centric, non-Von Neuman processors, i.e. digital circuits
generally designed for a fixed one or small set of applications. “Active interconnect” refers to using switchable low-
resistance devices to enable switchable interconnect. For example the “complementary atom switch” has potential to
replace the switchboxes in FPGAs for a substantial gain in power/performance 722 .
This has also been considerable interest in replacing the Look Up Tables (LUTs) in FPGAs with LUTs enabled by NV
memory crossbars. For example, Kumar et.al. 723 present a circuit for a RRAM based crossbar that reduces the sneak path
current and half write problems, and predict an improvement in read energy delay product in the range of 103 to 104 J.
Logic-in-memory refers to the idea of attaching logic directly to the columns of an SRAM or DRAM, and has been
proposed or employed multiple times to speed-up memory bound operations. Of course, replacing the SRAM or DRAM
with a fast low power NV RAM, such as STT or RRAM gives potential for reducing power, delay and area.
When multiple oscillators are loosely coupled, they tend towards the lowest energy synchronized state. This can be used
for associative computing tasks, e.g. image recognition. Several projects are underway today in which such systems are
being built using CMOS and emerging-device-enabled oscillators, e.g. coupled spin networks. For example, Fan et.al. 724
describe one approach using spin torque oscillators.
Non-deterministic computing refers to computing paradigms in which different behaviors can be obtained on different
runs. Examples include approximate computing, statistical computing, and quantum computing.
Approximate computing refers to the idea that you can size the precision (number of bits) of intermediate stages of the
computation and achieve a sufficiently precise result. This reduced precision can be used to save energy. This concept
can be quite useful in areas such as DSP, image processing, recognition and data mining. Just don’t use it for finance!
Current challenges are in hardware and software support to enable programmable approximation without user-driven
optimization of the required precision. Approximate computing can also be used to manage lack of precision due to lack
of reliability. See 725 for an example of recent work in this area. That work addresses still open issues as to how to
represent probability reasoning to the designer and how to build an end-to-end compiler chain.
Statistical computing is a broad field covering the intersection of computing and statistics. The area of interest in the
context of this chapter at the hardware layer is computing in the presence of errors, for example using an estimator to
correct an output based on error statistics 726 . This in turn enables the use of emerging devices with poor yield or low bit-
error-rates while enabling high density and low-power operation. A key challenge today is satisfying the need to have
nanofunction models that encapsulate the statistical behavior needed to enable statistical information processing. A
further need is to formulate the abstractions and supporting tools that permit software to be written that is agnostic to the
specific statistics of the underlying hardware. A potentially broader agenda is how to tie probabilistic behavior to
probabilistic programming, which are being used in machine learning techniques.
One quantum computing paradigm – quantum annealing – was discussed above. A more general technique is quantum
superposition – for example if one has a pair of qubits, the quantum superposition can be in any one of four states. By
manipulating this state through a set of quantum logic gates (e.g., by performing a quantum algorithm), a system of n
qubits will decompose into one of 2n states, however with only a certain known probability that the answer will be
correct. Vizotta 727 presents a review of the state of the art. Open challenges include maintaining coherence at scale and
I/O between the outside world and qubits that must be carefully isolated from their surrounding environment. Numerous
algorithms have been mapped onto quantum computers and prototype programming languages developed.

5.3.3 Emerging Data Centric Architectures
These are architectures that derive at least part of their “design” or “program” from the data they are processing. In
effect, either the final performance or the makeup of the configuration that delivers a particular performance is not
specified until data has been passed through the system. Such systems can be further divided into two types, systems that
are trained off-line, and systems trained on-line. In the former, the weights and settings are trained on a separate
computer on which a (usually) labeled training data set is run. In the latter, both training and recognition are done on the
same hardware, though sometimes the training might consist of updating weights and settings initially trained off-line.
Artificial Neural Networks (ANN) have been under active investigation as a computation paradigm since the 1940s.
Such systems consist of an interconnected network of multiple layers. Each node produces an output
f(x) = K i wigi(x)
where gi(x) are the inputs, wi are the weights, and K is an activation function, which can be linear, binary or non-linear. A
continuously differentiable activation function permits gradient-based optimization methods to be used in training. The
use of a nonlinear activation function allows multi-level systems to scale computing capability significantly as the number
of layers in the network increases. In a spiking neural network, the output only changes (“fires”) when the evaluated
function reaches a specific value.
A recent CMOS implementation of a spiking neural network is the IBM True North chip 728 . True North is programmed
via the “Corelet Programming Environment” which includes a compositional language and development library.
There is considerable interest in building ANNs with programmable resistive memories, including RRAM, PCM and
spin-based. Building ANNs with crossbar arrays is of particular interest, using the programmable memory elements to
store synaptic weights. With such, there is significant potential for power reduction and improvements in area efficiency.
However, one challenge is that the NVM nonlinearity and asymmetry “prevents the back-propagation algorithm from
locating optimum values during programming.” 729 .
Conventional logic can also be implemented using NVM crossbar arrays, by training the network with the complete truth
table. This has been demonstrated (in simulation) on Ohmic Weave 730 .
Micron has built a CMOS “automata processor” designed to accelerate regular expression evaluation, for use with
complex unstructured data streams 731 .
Recently, Deep Convolutional Networks (such as AlexNet) have arisen as algorithms that can achieve a high recognition
success rate, once intensively trained off-line. Other successful ANN algorithms being pursued by the Machine Learning
community include Long Short Term Memory. For example, deep learning is a feedforward ANN employing multiple
layers of hidden neurons, and nonlinear activation functions. CMOS accelerators have been built for a number of these
algorithms, e.g. Chen 732 . A key challenge is achieving high throughput in the presence of finite memory bandwidth.
The right-most column of Figure ERD8 refers to implementations of algorithms that can do in-situ training.
Some of these are variants of algorithms that can be trained off-line, for example using back-propagation to modify
previously trained network weights. Currently, there is significant research into how to incorporate online modifiability
into a number of machine learning algorithms. These normally operate in a supervised learning mode, i.e. the training
data is clearly labelled.
Of particular interest are applying algorithms that take their inspiration about how the brain learns, and can learn even
with unlabeled data (unsupervised learning). One approach is to implement spike timing dependent plasticity (STDP) on
a spiking neural network. In this biologically inspired approach, a neuron’s weight is increased if the input spike tends to
occur just before the output spike (causal), and decreased if not (acausal). Of particular research interest is how to
implement STDP in an NVM crossbar array.
Recently other algorithms have emerged that are inspired by higher level models implementing assumptions of how the
brain works at the cognition level. Examples include Hierarchical Temporal Memory (HTM) 733 and Cogent
Confabulation. 734 In Cogent Confabulation, the neurons are excited by a sum of Bayesian probabilities. Hebbian
learning is employed. HTM is not inspired directly by ANN, but instead by neuroscientific observations about the
neocortex. It is a sparse algorithm in which spatial and temporal sequences matter. In HTM, learning phases run between
recognition or inference phases.

The general idea of analog computing predates digital computing. In traditional analog computing, analog multipliers etc.
are built to perform calculations. Of recent interest has been the idea of using analog memories within an analog
computing paradigm. This permits a programmable analog system. One approach is to use floating gates as analog
memories in a field programmable analog array, and apply them to classification problems, e.g. 735 .
An area that has been little explored in the context of new devices is probabilistic learning, .e.g. in-situ training and
classification in a Bayesian network. Such systems require representation of probability distributions within the system.
5.4 CROSSBAR PROGRESS
One relatively common theme is the construction of crossbar arrays, typically arrays that use a two-terminal access device
instead of a transistor. Applications include FPGA LUTS, neuromorphic arrays, Storage-Class Memory, and TCAMs.
Table ERD15 summarizes a selection of reported measured results for implemented crossbars.
Banno et.al. 736 describes a chip with an 8x16 crossbar switch. Each switch is built using two RRAM-based varistors,
each with their own control line. Their motivating application was programmable logic devices. Prezioiso et.al. 737
describe a 10x8 crosspoint built using bilayer metal-oxide memristors. Their motivating application are classifiers using
deep learning neural networks. Luo et.al. 738 describe a threshold selector MIEC switch built with HfO2 RRAM device.
They demonstrate the device in a 32x32 array. Yu et.al. 739 describe a 64x64 1T1R pseudo-crossbar with RRAM devices
and integrate and fire neuron read CMOS circuits. Burr et.al. 740 describe a 3-layer perceptron network, with 164,885
synapses built using PCM. They demonstrate the capability of the network using the MNIST dataset. Jo et.al. 741
describe a 4 Mb RRAM array addressed using a new select device.
Table ERD15. A selection of reported measured results for implemented crossbars

6. EMERGING MEMORY AND LOGIC DEVICES ASSESSMENT
6.1 INTRODUCTION
The purpose of this section is to assess emerging research technology entries considered in this chapter benchmarked
against current memory or CMOS technologies. Two methods are used to perform this assessment. In the “Quantitative
Logic Device Benchmarking”, each emerging logic device is evaluated by its operation in conventional Boolean Logic
circuits, e.g., a unity gain inverter, a 2-input NAND gate, and a 32-bit shift register. Metrics evaluated include speed, areal
footprint, power dissipation, etc. Each parameter is compared with the performance projected for high performance and
low power 15nm CMOS applications. The second method, referred to as “Survey-Based Benchmarking”, was conducted
in the 2014 ERD Emerging Memory and Logic Device Assessment Workshops (Albuquerque, NM). The survey collects
voting on emerging technologies evaluated in the workshops in the categories of the “most promising” and the “most
need of resources” to assess the potential of these technology entries perceived by ERD experts.
Up to the 2013 ERD Chapter, a survey-based critical review was conducted based on eight criteria to compare emerging
devices against their CMOS benchmark. Spider chart has been used to visualize the perceived potential of these
technology entries. However, limited number of survey results sometimes raises questions of the accuracy of this survey.
Therefore, a different voting-based survey was used in this version to replace the previous approach.
An important issue regarding emerging charge-based nanoelectronic switch elements is related to the fundamental limits
to the scaling of these new devices, and how they compare with CMOS technology at its projected end of scaling. An
analysis 742 concludes that the fundamental limit of scaling an electronic charge-based switch is only a factor of 3× smaller
than the physical gate length of a silicon MOSFET in 2024. Furthermore, the density of these switches is limited by
maximum allowable power dissipation of approximately 100W/cm2, and not by their size. The conclusion of this work is
that MOSFET technology scaled to its practical limit in terms of size and power density will asymptotically reach the
theoretical limits of scaling for charge-based devices.
Most of the proposed beyond-CMOS replacement devices are very different from their CMOS counterparts, and often
pass computational state variables (or tokens) other than charge. Alternative state variables include collective or single
spins, excitons, plasmons, photons, magnetic domains, qubits, and even material domains (e.g., ferromagnetic). With the
multiplicity of programs characterizing the physics of proposed new structures, it is necessary to find ways to benchmark
the technologies effectively. This requires a combination of existing benchmarks used for CMOS and new benchmarks
which take into account the idiosyncrasies of the new device behavior. Even more challenging is to extend this process to
consider new circuits and architectures beyond the Boolean architecture used by CMOS today, which may enable these
devices to complete transactions more effectively.
6.1.1 Architectural requirements for a competitive logic device

The circuit designer and architect depend on the logic switch to exhibit specific desired characteristics in order to insure
successful realization of a wide range of applications. These characteristics 743 , which have since been supplemented in the
literature, include:
 Inversion and flexibility (can form an infinite number of logic functions)
 Isolation (output does not affect input)
 Logic gain (output may drive more than one following gate and provides a high Ion/Ioff ratio)
 Logical completeness (the device is capable of realizing any arbitrary logic function)
 Self restoring / stable (signal quality restored in each gate)
 Low cost manufacturability (acceptable process tolerance)
 Reliability (aging, wear-out, radiation immunity)
 Performance (transaction throughput improvement)
 “Span of control” is an important means of connecting device performance and area to communication performance,
relating time to space. The metric measures how other devices may be contacted within a characteristic delay of the

switch, and is dependent on not only switch delay but also switch area, as well as communication speed 744 .
Successful architectures also need effective fan-out.
Devices with intrinsic properties supporting the above features will be adopted more readily by the industry. Moreover,
devices which enable architectures that address emerging concerns such as computational efficiency, complexity
management, self-organized reliability and serviceability, and intrinsic cyber-security 745 are particularly valuable.
6.2 QUANTITATIVE LOGIC DEVICE BENCHMARKING

The first method for benchmarking emerging information processing devices is based on their quantitative evaluation in
conventional circuits. The Nanoelectronics Research Initiative (http://nri.src.org) has been benchmarking several diverse
beyond-CMOS technologies, trying to balance the need for quantitative metrics to assess a new device concept’s potential
with the need to allow device research to progress in new directions which might not lend themselves to existing metrics.
Several of the more promising NRI devices have been described in detail in the Logic and Emerging Information
Processing Device Section, and the intermediate results on the benchmarking efforts were outlined in a 2010 IEEE
Proceedings article 746 . The benchmark results were updated again based on refined device data in 2011 747 . Some results
of this benchmark study were included in 2013 ERD chapter. Another independent benchmark was conducted by Intel
researchers pursuing uniform methodology for benchmark on the same set of NRI device using similar reference circuits
and parameters 748,749 . Earlier results of this study were included in 2013 ERD chapter and more results results are
discussed in this version.
While all these efforts are still very much a work in progress – and no concrete decisions have been made on which
devices should be chosen or eliminated as candidates for significantly extending or augmenting the roadmap as CMOS
scaling slows – this section summarizes some of the data and insights gained from these studies. Further benchmark may
alter some of the conclusions here and the outlook on some of these devices, but the overall message on the challenge of
finding a beyond CMOS device which can compete well across the full spectrum of benchmarks of interest remains.
6.2.1 Quantitative Results

Preliminary analyses sponsored by SRC/NRI and the Intel study surveyed the potential logic opportunities afforded by
major emerging switches using a variety of information tokens and communication transport mechanisms. Specifically,
the projected effectiveness of these devices used in a number of logic gate configurations was evaluated, and normalized
to CMOS at the 15nm generation as captured by the ITRS. The initial work has focused on “standard” Boolean logic
architecture, since the CMOS equivalent is readily available for comparison. It should be noted that the majority of
devices are evaluated via simulations, since many of them have not yet been built, so it should be considered only a
“snapshot in time” of the potential of any given device. Data on all of them are still evolving.
(a) (b)
Figure ERD9 Median delay, energy, and area of proposed devices in NRI benchmark (normalized to ITRS 15-nm CMOS), based on
principal investigators’ data. (a) 2011 benchmark results 747 ; (b) 2010 benchmark results 746 .
X X X X

At a high level, the data from these studies corroborates qualitative insights from earlier works, suggesting that many new
logic switch structures are superior to CMOS in energy and area, but inferior to CMOS in delay, as shown in the plot of
median data for the device (Figure ERD9). This is perhaps not surprising; the primary goal for nanoelectronics and NRI is
to find a lower power device 750 since power density is a primary concern for future CMOS scaling. The power-speed
tradeoffs commonly observed in CMOS is also extended into the emerging devices. The difference between panel (a) and
panel (b) shows that the benchmarking results were evolving from 2010 to 2011, due to more refined device data input
from NRI researchers in 2011. It is also important to understand the impact of transport delay for the different information
tokens these devices employ. Communication with many non-charge tokens can be significantly slower than moving
charge, although this may be balanced in some cases with lower energy for transport. The combination of the new balance
between switch speed, switch area, and interconnect speed can lead to advantages in the span of control for a given
technology. For some of the technologies (e.g., nanomagnetic logic), there is no strong distinction between the switch
and the interconnect, indicating the need for novel architecture to exploit unique attributes of these technologies.
Figure ERD10 lists the devices benchmarked in the Intel study 749 . Simplified 32-bit arithmetic logic unit (ALU) was built
X X
from these devices to evaluate their performance. The energy-delay plot in Figure ERD11(a) reveals disadvantages of
spin-based devices in speed, while no obvious energy advantage is demonstrated. Figure ERD11(b) shows power-
constrained throughput of these ALUs. It should be pointed out that the evaluations from the NRI benchmark and the Intel
study do not always agree with each other on the same types of devices, due to different device assumptions on device
parameters, interpretations of physical mechanisms, and logic gate designs.
Figure ERD10 List of devices considered in Intel benchmark with their computational variables and classification 749 .
X X

Figure ERD11 (a) Energy vs. delay plot of 32bit ALU built from benchmarked devices; (b) power vs. throughput of 32bit ALU built
from these devices, reflecting power-constrained (< 10 W/cm2) throughput 749 .
X X
At the architecture level, the ability to speculate on how these devices will perform is still in its infancy. While the
ultimate goal is to compare at a very high level – e.g., how many MIPS can be produced for 100mW in 1 mm2? – the
current work must extrapolate from only very primitive gate structures. One initial attempt to start this process has been
to look at the relative “logical effort” 751 for these technologies, a figure of merit that ties fundamental technology to a
resulting logic transaction. Several of the devices appear to offer advantage over CMOS in logical effort, particular for
more complex functions, which increases the urgency of doing more joint device – architecture co-design for these
emerging technologies.
6.2.2 Observations
A number of common themes have emerged from these benchmark studies and in the observations made during recent
studies of beyond-CMOS replacement switches 752,753 . A few noteworthy concepts:
1) The low voltage energy-delay tradeoff conundrum will continue to be a challenge for all devices. Getting to low
voltage must remain a priority for achieving low power, but new approaches to getting throughput with ‘slow’
devices must be developed.
2) Most of the architectures that have been considered to date in the context of new devices utilize binary logic to
implement von Neumann computing structures. In this area, CMOS implementations are difficult to supplant
because they are very competitive across the spectrum of energy, delay and area – not surprising since these
architectures have evolved over several decades to exploit the properties and limitations of CMOS most
effectively. Novel electron-based devices – which can include devices that take advantage of collective and non-
equilibrium effects – appear to be the best candidates as a drop-in replacement for CMOS for binary logic
applications.
3) As the behavior of other emerging research devices becomes better understood, work on novel architectures that
leverage these features will be increasingly important. A device that may not be competitive at doing a simple
NAND function may have advantages in doing a complex adder or multiplier instead. Understanding the right
building blocks for each device to maximize throughput of the system will be critical. This may be best
accomplished by thinking about the high-level metric a system or core is designed to achieve (e.g., computation,
pattern recognition, FFT, etc.) and finding the best match between the device and circuit for maximizing this
metric.
4) Increasing functional integration and on-chip switch count will continue to grow. To that end, in any logic
architectural alternative, both flexible rich logic circuit libraries and reconfigurability will be required for new
switch implementations.
5) Patterning, precision layer deposition, material purity, dopant placement, and alignment precision critical to
CMOS will continue to be important in the realization of architectures using these new switches.

6) Assessment of novel architectures using new switches must also include the transport mechanism for the
information tokens. Fundamental relationships connecting information generation with information
communication spatially and temporally will dictate CMOS’ successor.
Based on the current data and observations, it is clear that CMOS will remain the primary basis for IC chips for the
coming decade. While it is unlikely that any of the current emerging devices could entirely replace CMOS, several do
seem to offer advantages, such as ultra-low power or nonvolatility, which could be utilized to augment CMOS or to
enable better performance in specific application spaces. One potential area for entry is that of special purpose cores or
accelerators that could off-load specific computations from the primary general purpose processor and provide overall
improvement in system performance. This is particularly attractive given the move to multi-core chips: while most are
homogeneous today, if scaling slows in delivering the historically expected performance improvements in future
generations, heterogeneous multi-core chips may be a more attractive option. These would include specific, custom-
designed cores dedicated to accelerate high-value functions, such as accelerators already widely-used today in CMOS
(e.g. Encryption/Decryption, Compression/Decompression, Floating Point Units, Digital Signal Processors, etc.), as well
as potentially new, higher-level functions (e.g. voice recognition). While integrating dissimilar technologies and materials
is a big challenge, advances in packaging and 3D integration may make this more feasible over time, but the performance
improvement would need to be large to balance this effort.
As a general rule, an accelerator is considered as an adjunct to the core processors if replacing its software
implementation improves overall core processor throughput by approximately ten percent; an accelerator using a non-
CMOS technology would likely need to offer an order of magnitude performance improvement relative to its CMOS
implementation to be considered worthwhile. That is a high bar, but there may be instances where the unique
characteristics of emerging devices, combined with a complementary architecture, could be used to advantage in
implementing a particular function. At the same time, the changing landscape of electronics (moving from uniform,
general purpose computing devices to a spectrum of devices with varying purposes, power constraints, and environments
spanning servers in data centers to smart phones to embedded sensors) and the changing landscape of workloads and
processing needs (Big Data, unstructured information, real-time computing, 3D rich graphics) are increasing the need for
new computing solutions. One of the primary goals then for future beyond-CMOS work should be to focus on specific
emerging functions and optimize between the device and architecture to achieve solutions that can break through the
current power/performance limits.
6.3 SURVEY-BASED BENCHMARKING OF BEYOND CMOS MEMORY & LOGIC

TECHNOLOGIES
6.3.1 Emerging Device Assessment in 2014 ERD Workshops

In August 2014, ERD organized an “Emerging Memory Device Assessment Workshop” and an “Emerging Logic Device
Assessment Workshop”, where nice memory devices and fourteen logic devices were evaluated. Each device was
evaluated by a proponent who focuses on the advantages of the device and a friendly critic who addresses challenges of
the device. Each device was extensively discussed by participating experts. A survey was also conducted in the
workshops for the experts to vote on the “most promising” devices and devices “needing more resources”. Figure ERD12
shows the relative number of vote received by emerging memory devices in these two categories, ranked from high to low
in the “most promising” category (read color bars). Figure ERD 13 is the relevant volte of emerging logic devices.
In the “most promising” memory device category, the vote clearly accumulated to a few well-known memory devices:
STTRAM, ReRAM (including CBRAM and oxide-based ReRAM), and PCM, ranked from high to low. Some memory
devices received few vote, due to lack of progress. Results in this category reflect concensus among experts based on
factual R&D status of these devices. The “need more resources” category reflects perceived value of these devices in the
view of the experts who have diversified background and interest. The results also reflect experts’ consideration of R&D
resource allocation based on existing investment (or lack of investment) for each device. For example, with heavy R&D
investment on STTRAM that is considered most promising, it is not surprising that it ranks low in the need of resource.
The strong interest in emerging FeFET memory is closely linked to the discovery of ferroelectricity in doped HfOx.
Carbon-based memory is also recommended as a top choice for R&D resource, owing to general interest in carbon
materials and devices based on various forms of carbon materials.

Figure ERD12 Survey of emerging memory devices in 2014 ERD Emerging Memory Workshop (Albuquerque, NM).
Similar trend and difference in the “most promising” and “need of resources” categories are also observed in emerging
logic devices in Figure ERD13. “Carbon nanomaterial device” (mainly carbon nanotube FET), tunnel FET, and nanowire
FET were ranked as one of the most promising emerging logic devices. Notice that they are all charge-based devices, but
involve novel materials, structures, and mechanisms. “Piezotronic transistors”, “negative-capacitance FET”, and “2D
channel FET” were considered top choices for enhanced research investment.
Figure ERD13 Survey of emerging logic devices in 2014 ERD Emerging Logic Workshop (Albuquerque, NM).
6.3.2 ERD Survey Criteria, Methodology, and results

The second method for benchmarking emerging memory and information processing devices is based on a survey of the
Emerging Research Devices Working Group. Some emerging nanoscale devices discussed in this chapter are charge-
based structures proposed to extend CMOS to the end of the current roadmap. Other emerging devices offer new
computational state variables and will likely require new fabrication technologies. A set of relevance or evaluation
criteria, defined below, are used to parameterize the extent to which proposed “CMOS Extension” and “Beyond CMOS”
technologies are applicable to memory or information processing applications. The relevance criteria are: 1) Scalability,
2) Speed, 3) Energy Efficiency, 4) Gain (Logic) or ON/OFF Ratio (Memory), 5) Operational Reliability, 6) Operational
Temperature, 7) CMOS Technological Compatibility, and 8) CMOS Architectural Compatibility. Detailed description of
each criterion can be found in 2013 ERD chapter.

Each CMOS extension and beyond-CMOS emerging research nanoscale memory and logic device technology is
evaluated against each Relevance Criterion according to a single factor. For logic, this factor relates to the projected
potential performance of a nanoscale device technology, assuming its successful development to maturity, compared to
that for silicon CMOS scaled to the end of the Roadmap. For memory, this factor relates the projected potential
performance of each nanoscale memory device technology, assuming its successful development to maturity, compared
to that for ultimately scaled current silicon memory technology which the new memory would displace. Performance
potential for each criterion is assigned a value from 1–3, with “3” substantially exceeding ultimately-scaled CMOS, and
“1” substantially inferior to CMOS or, again, a comparable existing memory technology. These numbers are more
precisely defined in that charts below. This evaluation is determined by a survey of the ERD Working Group members
composed of individuals representing a broad range of technical backgrounds and expertise. Details of the assessment
values are also included in 2013 ERD chapter.
Although this survey-based critical review has been conducted in ERD for several versions and has been widely cited in
literatures, the decreasing number of votes of some less popular devices has raised concerns about the accuracy of some
of the results. Therefore, this version used the experts’ vote in 2014 workshops as the qualitative assessment. Figures
ERD14 and ERD15 summarize the critical review conducted in 2013 for emerging memory devices and emerging logic
devices, respectively. Devices in the same category are compared in the same spider chart, while 2013 ERD chapter
provided spider charts comparing evolving assessment of each device from 2009 to 2013. Notice that the technology
entries in these figures are based on the 2013 ERD chapter, while some of them have been removed in this version (e.g.,
molecular memory, atomic switch, etc.) and several new additions in this version are not included (e.g., novel STTRAM,
piezotronic transistors, etc.)
Figure ERD14 Comparison of emerging memory devices based on 2013 critical review.
(a) CMOS extension devices (b) Charge-based byond-CMOS devices

Figure ERD15 Comparison of emerging logic

devices based on 2013 critical review: (a)
CMOS extension devices; (b) Charge-based
beyond-CMOS devices; (c) Non-charge-based
beyond-CMOS devices.
(c) Non-charge-based beyond-CMOS devices
Since “3” represents the best result and “1” the worst in the spider chart, devices with larger circle area represent more
promising devices. In Figure ERD15 for emerging logic devices, the perceived potential of “beyond-CMOS devices” is
generally poorer than “CMOS-extension devices”. Within “beyond-CMOS devices”, “non-charge-based devices” area
also also perceived slightly less promising than “charge-based devices”. The general trend is consistent with the
quantitative assessment in section 6.2. Multiple factors contribute to this result, including the strength of CMOS as a
platform technology, the challenges of beyond-CMOS devices in materials, fabrication, and even mechanisms, the lack of
memory and interconnect solutions for beyond-CMOS devices, etc.
7. PROCESSING
7.1 INTRODUCTION
In considering the many disparate new approaches proposed to provide order of magnitude scaling of information
processing beyond that attainable with ultimately scaled CMOS, the Emerging Research Devices Working Group
proposes the following comprehensive set of guiding principles. We believe these “Guiding Principles” provide a useful
structure for directing research on any “Beyond CMOS” information processing technology to dramatically enhance
scaling of functional density and performance while simultaneously reducing the energy dissipated per functional
operation. Further this new technology would need to be realizable using a highly manufacturable fabrication process.
7.2 GRAND CHALLENGES

7.2.1 COMPUTATIONAL STATE VARIABLE(S) OTHER THAN SOLELY ELECTRON CHARGE
These include spin, phase, multipole orientation, mechanical position, polarity, orbital symmetry, magnetic flux quanta,
molecular configuration, and other quantum states. The estimated performance comparison of alternative state variable
devices to ultimately scaled CMOS should be made as early in a program as possible to down-select and identify key
trade-offs.
7.2.2 NON-THERMAL EQUILIBRIUM SYSTEMS
These are systems that are out of equilibrium with the ambient thermal environment for some period of their operation,
thereby reducing the perturbations of stored information energy in the system caused by thermal interactions with the
environment. The purpose is to allow lower energy computational processing while maintaining information integrity.
7.2.3 NOVEL ENERGY TRANSFER INTERACTIONS
These interactions would provide the interconnect function between communicating information processing elements.
Energy transfer mechanisms for device interconnection could be based on short range interactions, including, for

example, quantum exchange and double exchange interactions, electron hopping, Förster coupling (dipole–dipole
coupling), tunneling and coherent phonons.
7.2.4 NANOSCALE THERMAL MANAGEMENT
This could be accomplished by manipulating lattice phonons for constructive energy transport and heat removal.
7.2.5 SUB-LITHOGRAPHIC MANUFACTURING PROCESS
One example of this principle is directed self-assembly of complex structures composed of nanoscale building blocks.
These self-assembly approaches should address non-regular, hierarchically organized structures, be tied to specific device
ideas, and be consistent with high volume manufacturing processes.
7.2.6 ALTERNATIVE ARCHITECTURES
In this case, architecture is the functional arrangement on a single chip of interconnected devices that includes embedded
computational components. These architectures could utilize, for special purposes, novel devices other than CMOS to
perform unique functions.

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INTERNATIONAL

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015 i

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

Table ERD 1 Transition Table for Emerging Research Devices

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

EMERGING RESEARCH DEVICES

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

1.2 DIFFICULT CHALLENGES

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

Table ERD2 Emerging Research Devices Difficult Challenges

2 1.2.2 Device Technologies

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

0 1.3 NANO-INFORMATION PROCESSING TAXONOMY

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

A Taxonomy for Nano Information Processing Technologies

Multicore Architecture Morphic

Von Neumann Analog Quantum

Device Spintronics Quantum

Material Carbon Strongly correlated mat’ls

Silicon Ge & III-V mat’ls Nanostructured mat’ls

State Variable Phase Spin orientation

Electric charge Molecular state Strongly correlated

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

2. EMERGING MEMORY DEVICES

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

2.1 MEMORY TAXONOMY

Figure ERD3 Taxonomy of emerging memory devices

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

2.2 EMERGING MEMORY DEVICES

4 2.2.1 Redox Memory

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

45 2.2.1.2 Metal Oxide-Bipolar Filamentary ReRAM

to mitigate the electroforming process and obtain electroforming-free devices. 27 X X

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

use of a single program voltage polarity greatly simplifies the circuitry.

assisted switching to lower the switching current.

47 2.2.1.4 Metal Oxide-Bipolar Non-Filamentary ReRAM

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

49 2.2.2.1 Ferroelectric FET

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

6 2.2.3 Carbon Based Memory

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

switching voltage will be less than 0.01 V.

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

switch 1x nm cells, an effect of 3x larger will be required.

2.3 MEMORY SELECT DEVICE

THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2015

Memory Selector Devices

Transistor Diodes Volatile switch Nonlinear devices

Planar Si diodes Threshold Tunneling-based

Metal/oxide Schottky Complementary

Figure ERD4. Taxonomy of memory select devices

9 2.3.1 Vertical transistors

10 2.3.2 Diode selector devices