H-Bridge Gate Driver IC: Freescale Semiconductor, Inc

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Freescale Semiconductor, Inc.

MOTOROLA Document order number: MC33883/D


SEMICONDUCTOR TECHNICAL DATA Rev 7.0, 02/2005

33883
H-Bridge Gate Driver IC
The 33883 is an H-bridge gate driver (also known as a full-bridge predriver)
IC with integrated charge pump and independent high- and low-side gate
driver channels. The gate driver channels are independently controlled by four
separate input terminals, thus allowing the device to be optionally configured
H-BRIDGE GATE DRIVER IC
as two independent high-side gate drivers and two independent low-side gate
drivers. The low-side channels are referenced to ground. The high-side
channels are floating.
The gate driver outputs can source and sink up to 1.0 A peak current
pulses, permitting large gate-charge MOSFETs to be driven and/or high Pulse
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Width Modulation (PWM) frequencies to be utilized. A linear regulator is


incorporated, providing a 15 V typical gate supply to the low-side gate drivers.

Features
• VCC Operating Voltage Range from 5.5 V up to 55 V
• VCC2 Operating Voltage Range from 5.5 V up to 28 V
DW SUFFIX
• CMOS/LSTTL Compatible I/O 98ASB42343B
• 1.0 A Peak Gate Driver Current 20-TERMINAL SOICW
• Built-In High-Side Charge Pump
• Undervoltage Lockout (UVLO) ORDERING INFORMATION
• Overvoltage Lockout (OVLO)
Temperature
• Global Enable with <10 µA Sleep Mode Device
Range (TA)
Package
• Supports PWM up to 100 kHz
MC33883DW/R2 -40°C to 125°C 20 SOICW

33883 Simplified
SimplifiedApplication
Application Diagram
Diagram

VBAT VBOOST

33883
VCC CP_OUT
VCC2 LR_OUT
G_EN

C1 GATE_HS1
C2 SRC_HS1
DC
MCU GATE_LS1 Motor
GATE_HS2

IN_HS1 SRC_HS2
IN_LS1 GATE_LS2
IN_HS2
IN_LS2 GND

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CCP

C1 C2
VCC2
VCC, VCC2 VCC
Undervoltage/ VCC2
Overvoltage VCC C1
5.5 V– 28 V
Detection VCC
VDD Charge
EN C2
Pump VCC
CP_OUT
GND VPOS
5.5 V –
G_EN CCP_OUT 55 V
GND2 VCC2 VDD

VCC2 CP_OUT
+5.0 V
EN Linear
CLR_OUT
Reg LR_OUT
GND +14.5 V
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GND_A LR_OUT
GND2 HIGH- AND LOW-SIDE
CONTROL WITH CHARGE PUMP

CP_OUT
BRG_EN VCC
Control
IN_HS1 VDD /VPOS Pulse IN Output OUT
and GATE_HS1
Generator Driver
TSD1 Logic Level Shift
SRC_HS1
TSD1
HIGH-SIDE CHANNEL
Thermal Shutdown
BRG_EN
Control
LR_OUT
IN_LS1 and
Logic
TSD1 IN Output OUT
VDD /VCC Pulse GATE_LS1
Generator Driver
Level Shift

LOW-SIDE CHANNEL GND1

VCC
CP_OUT
BRG_EN
Control
IN Output OUT
IN_HS2 and VDD /VPOS Pulse GATE_HS2
Generator Driver
Logic Level Shift
TSD2
SRC_HS2
HIGH-SIDE CHANNEL TSD2
Thermal Shutdown
BRG_EN
Control LR_OUT
IN_LS2 and
TSD2 Logic
IN Output OUT
VDD /VCC Pulse GATE_LS2
Generator Driver
Level Shift

LOW-SIDE CHANNEL GND2

GND1 GND2 GND_A

Figure 1. 33883 Simplified Internal Block Diagram

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VCC 1 20 G_EN
C2 2 19 SRC_HS2
CP_OUT 3 18 GATE_HS2
SRC_HS1 4 17 IN_HS2
GATE_HS1 5 16 IN_LS2
IN_HS1 6 15 GATE_LS2
IN_LS1 7 14 GND2
GATE_LS1 8 13 C1
GND1 9 12 GND_A
LR_OUT 10 11 VCC2

TERMINAL FUNCTION DESCRIPTION


Terminal Terminal Name Formal Name Definition
1 VCC Supply Voltage 1 Device power supply 1.
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2 C2 Charge Pump Capacitor External capacitor for internal charge pump.

3 CP_OUT Charge Pump Out External reservoir capacitor for internal charge pump.
4 SRC_HS1 Source 1 Output High Side Source of high-side 1 MOSFET
5 GATE_HS1 Gate 1 Output High Side Gate of high-side 1 MOSFET.
6 IN_HS1 Input High Side 1 Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1
HIGH).
7 IN_LS1 Input Low Side 1 Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1
HIGH).
8 GATE_LS1 Gate 1 Output Low Side Gate of low-side 1 MOSFET.
9 GND1 Ground 1 Device ground 1.
10 LR_OUT Linear Regulator Output Output of internal linear regulator.
11 VCC2 Supply Voltage 2 Device power supply 2.

12 GND_A Analog Ground Device analog ground.


13 C1 Charge Pump Capacitor External capacitor for internal charge pump.
14 GND2 Ground 2 Device ground 2.
15 GATE_LS2 Gate 2 Output Low Side Gate of low-side 2 MOSFET.
16 IN_LS2 Input Low Side 2 Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2
HIGH).
17 IN_HS2 Input High Side 2 Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2
HIGH).
18 GATE_HS2 Gate 2 Output High Side Gate of high-side 2 MOSFET.

19 SRC_HS2 Source 2 Output High Side Source of high-side 2 MOSFET.


20 G_EN Global Enable Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation,
G_EN logic LOW = Sleep Mode).

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating Symbol Value Unit

Supply Voltage 1 VCC -0.3 to 65 V

Supply Voltage 2 (Note 1) VCC2 -0.3 to 35 V

Linear Regulator Output Voltage VLR_OUT -0.3 to 18 V

High-Side Floating Supply Absolute Voltage VCP_OUT -0.3 to 65 V

High-Side Floating Source Voltage VSRC_HS -2.0 to 65 V

High-Side Source Current from CP_OUT in Switch ON State IS 250 mA

High-Side Gate Voltage VGATE_HS -0.3 to 65 V

VGATE_HS - VSRC_HS -0.3 to 20 V


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High-Side Gate Source Voltage (Note 2)

High-Side Floating Supply Gate Voltage VCP_OUT - VGATE_HS -0.3 to 65 V

Low-Side Gate Voltage VGATE_LS -0.3 to 17 V

Wake-Up Voltage VG_EN -0.3 to 35 V

Logic Input Voltage VIN -0.3 to 10 V

Charge Pump Capacitor Voltage VC1 -0.3 to VLR_OUT V

Charge Pump Capacitor Voltage VC2 -0.3 to 65 V

ESD Voltage V
Human Body Model on All Pins (VCC and VCC2 as Two Power
Supplies) (Note 3) VESD1 ±1500
Machine Model (Note 4) VESD2 ±130

Power Dissipation and Thermal Characteristics


Maximum Power Dissipation @ 25°C PD 1.25 W
Thermal Resistance (Junction to Ambient) RθJA 100 °C/W
Operating Junction Temperature TJ -40 to 150 °C
Storage Temperature TSTG -65 to 150 °C

Terminal Soldering Temperature (Note 5) TSOLDER 240 °C

Notes
1. VCC2 can sustain load dump pulse of 40 V, 400 ms, 2.0 Ω.
2. In case of high current (SRC_HS>100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed
as shown in Figure 12.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω).
4. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
5. Terminal soldering temperature limit is for 10 second maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.

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STATIC ELECTRICAL CHARACTERISTICS


Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values
for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

OPERATING CONDITIONS
Supply Voltage 1 for Output High-Side Driver and Charge Pump VCC 5.5 – 55 V

Supply Voltage 2 for Linear Regulation VCC2 5.5 – 28 V

High-Side Floating Supply Absolute Voltage VCP_OUT VCC+4 – VCC +11 V


but < 65

LOGIC
Logic 1 Input Voltage (IN_LS and IN_HS) VIH 2.0 – 10 V
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Logic 0 Input Voltage (IN_LS and IN_HS) VIL – – 0.8 V

Logic 1 Input Current IIN+ µA


VIN = 5.0 V 200 – 1000

Wake-Up Input Voltage (G_EN) VG_EN 4.5 5.0 VCC2 V

Wake-Up Input Current (G_EN) IG_EN µA


VG_EN = 14 V – 200 500

Wake-Up Input Current (G_EN) IG_EN2 mA


VG_EN = 28 V – – 1.5

LINEAR REGULATOR
Linear Regulator VLR_OUT V
VLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to 20 mA 12.5 – 16.5
VLR_OUT @ ILOAD = 20 mA VCC2 -1.5 – –

VLR_OUT @ ILOAD = 20 mA, VCC2 = 5.5 V, VCC = 5.5 V 4.0 – –

CHARGE PUMP
Charge Pump Output Voltage, Reference to VCC VCP_OUT V

VCC = 12 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 7.5 – –

VCC = 12 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF 7.0 – –

VCC2 = VCC = 5.5 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 2.3 – –

VCC2 = VCC = 5.5 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF 1.8 – –

VCC = 55 V, ILOAD = 0 mA, CCP_OUT = 1.0 µF 7.5 – –


7.0 – –
VCC = 55 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 µF

Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see IC1 A
Figure 11, page 14) -2.0 – 2.0

Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see VC1min V
Figure 11, page 14) -1.5 – –

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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STATIC ELECTRICAL CHARACTERISTICS (continued)


Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values
for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

SUPPLY VOLTAGE
Quiescent VCC Supply Current IVCCsleep µA

VG_EN = 0 V and VCC = 55 V – – 10


– – 10
VG_EN = 0 V and VCC = 12 V

Operating VCC Supply Current (Note 6) IVCCop mA


VCC = 55 V and VCC2 = 28 V – 2.2 –
– 0.7 –
VCC = 12 V and VCC2 = 12 V
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Additional Operating VCC Supply Current for Each Logic Input Terminal Active IVCClog mA
VCC = 55 V and VCC2 = 28 V (Note 7) – – 5.0

Quiescent VCC2 Supply Current IVCC2sleep µA


VG_EN = 0 V and VCC = 12 V – – 5.0
– – 5.0
VG_EN = 0 V and VCC = 28 V

Operating VCC2 Supply Current (Note 6) IVCC2op mA


VCC = 55 V and VCC2 = 28 V – – 12
– – 9.0
VCC = 12 V and VCC2 = 12 V

Additional Operating VCC2 Supply Current for Each Logic Input Terminal IVCC2log mA
Active
VCC = 55 V and VCC2 = 28 V (Note 7) – – 5.0

Undervoltage Shutdown VCC UV 4.0 5.0 5.5 V

Undervoltage Shutdown VCC2 (Note 8) UV2 4.0 5.0 5.5 V

Overvoltage Shutdown VCC OV 57 61 65 V

Overvoltage Shutdown VCC2 OV2 29.5 31 35 V

OUTPUT
Output Sink Resistance (Turned Off) RDS Ω
Idischarge LSS = 50 mA , VSRC_HS = 0 V (Note 8) – – 22

Output Source Resistance (Turned On) RDS Ω


Icharge HSS = 50 mA, VCP_OUT = 20 V (Note 8) – – 22

Charge Current of the External High-Side MOSFET Through GATE_HSn Icharge HSS mA
Terminal (Note 9) – 100 200

Maximum Voltage (VGATE_HS - VSRC_HS) Vmax V

INH = Logic 1, ISmax = 5.0 mA – – 18

Notes
6. Logic input terminal inactive (high impedance).
7. High-frequency PWM-ing (» 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain
within the package power handling rating.
8. The device may exhibit predictable behavior between 4.0 V and 5.5 V.
9. See Figure 3, page 10, for a description of charge current.

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DYNAMIC ELECTRICAL CHARACTERISTICS


Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values
for TA = 25°C and min/max values for TA = -40°C to 125°C unless otherwise noted.
Characteristic Symbol Min Typ Max Unit

TIMING CHARACTERISTICS
Propagation Delay High Side and Low Side tpd ns
CLOAD = 5.0 nF, Between 50% Input to 50% Output (Note 10) (see Figure 2) – 200 300

Turn-On Rise Time tr ns


CLOAD = 5.0 nF, 10% to 90% (Note 10), (Note 11) (see Figure 2) – 80 180

Turn-Off Fall Time tf ns


CLOAD = 5.0 nF, 10% to 90% (Note 10), (Note 11) (see Figure 2) – 80 180
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Notes
10. CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.
11. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time).

50% 50%
IN_HS
or IN_LS t pd t pd

GATE_HS
or GATE_LS 50% 50%
tf tr

10% 90% 90% 10%

Figure 2. Timing Characteristics

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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33883 is an H-bridge gate driver (or full-bridge predriver) charge MOSFETs and supports high PWM frequency. In sleep
with integrated charge pump and independent high- and low- mode its supply current is very low.
side driver channels. It has the capability to drive large gate-

FUNCTIONAL TERMINAL DESCRIPTION

Supply Voltage Terminals (VCC and VCC2) Gate High- and Low-Side Terminals (GATE_HSn and
GATE_LSn)
The VCC and VCC2 terminals are the power supply inputs to
the device. VCC is used for the output high-side drivers and the The GATE_HSn and GATE_LSn terminals are the gates of
charge pump. VCC2 is used for the linear regulation. They can the external high- and low-side MOSFETs. The external high-
and low-side MOSFETs are controlled using the IN_HSn and
be connected together or independent with different voltage
IN_LSn inputs.
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values. The device can operate with VCC up to 55 V and VCC2


up to 28 V.
G_EN Terminal
The VCC and VCC2 terminals have undervoltage (UV) and
The G_EN terminal is used to place the device in a sleep
overvoltage (OV) shutdown. If one of the supply voltage drops
mode. When the G_EN terminal voltage is a logic LOW state,
below the undervoltage threshold or rises above the
the device is in sleep mode. The device is enabled and fully
overvoltage threshold, the gate outputs are switched LOW in
operational when the G_EN terminal voltage is logic HIGH,
order to switch off the external MOSFETs. When the supply
typically 5.0 V.
returns to a level that is above the UV threshold or below the OV
threshold, the device resumes normal operation according to
the established condition of the input terminals. Charge Pump Out Terminal (CP_OUT)
The CP_OUT terminal is used to connect an external
Input High- and Low-Side Terminals (IN_HSn and reservoir capacitor for the charge pump.
IN_LSn)
The IN_HSn and IN_LSn terminals are input control Charge Pump Capacitor Terminals (C1 and C2)
terminals used to control the gate outputs. These terminals are The C1 and C2 terminals are used to connect an external
5.0 V CMOS-compatible inputs with hysteresis. IN_HSn and capacitor for the charge pump.
IN_LSn independently control GATE_HSn and GATE_LSn,
respectively.
Linear Regulator Output Terminal (LR_OUT)
During wake-up, the logic is supplied from the G_EN
The LR_OUT terminal is the output of the internal regulator.
terminal. There is no internal circuit to prevent the external high-
It is used to connect an external capacitor.
side and low-side MOSFETs from conducting at the same time.

Ground Terminals (GNDn and GND_A)


Source Output High-Side Terminals (SRC_HSn)
These terminals are the ground terminals of the device. They
The SRC_HSn terminals are the sources of the external
should be connected together with a very low impedance
high-side MOSFETs. The external high-side MOSFETs are
connection.
controlled using the IN_HSn inputs.

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Table 1. Functional Truth Table

Conditions G_EN IN_HSn IN_LSn Gate_HSn Gate_LSn Comments

Sleep 0 x x 0 0 Device is in Sleep mode. The gates are at low state.

Normal 1 1 1 1 1 Normal mode. The gates are controlled independently.

Normal 1 0 0 0 0 Normal mode. The gates are controlled independently.

Undervoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low
state. Once the fault is removed, the 33883 recovers its
normal mode.

Overvoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low
state. Once the fault is removed, the 33883 recovers its
normal mode.

Overtemperature 1 1 x 0 x The device is currently in fault mode. The high-side gate is


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on High-Side Gate Driver at low state. Once the fault is removed, the 33883 recovers
its normal mode.

Overtemperature 1 x 1 x 0 The device is currently in fault mode. The low-side gate is


on Low-Side Gate Driver at low state. Once the fault is removed, the 33883 recovers
its normal mode.

x = Don’t care.

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DEVICE DESCRIPTION

Driver Characteristics The different voltages and current of the high-side gate driver
are illustrated in Figure 4. The output driver sources a peak
Figure 3 represents the external circuit of the high-side gate current of up to 1.0 A for 200 ns to turn on the gate. After
driver. In the schematic, HSS represents the switch that is used 200 ns, 100 mA is continuously provided to maintain the gate
to charge the external high-side MOSFET through the charged. The output driver sinks a high current to turn off the
GATE_HS terminal. LSS represents the switch that is used to gate. This current can be up to 1.0 A peak for a 100 nF load.
discharge the external high-side MOSFET through the
GATE_HS terminal. A 180KΩ internal typical passive discharge
resistance and a 18 V typical protection zener are in parallel IN_HS1
with LSS. The same schematic can be applied to the external
low-side MOSFET driver simply by replacing terminal CP_OUT 0
with terminal LR_OUT, terminal GATE_HS with terminal
GATE_LS, and terminal SRC_HS with GND. HSSpulse_IN
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0
CP_OUT
HSS DC_IN
HSS
0
IGATE_HS
Icharge HSS GATE_HS1
HSSDC_IN LSS_IN

Idischarge LSS

Icharge HSS
180 1.0 A Peak
IN_HS1
LSS kΩ 100 mA Typical
HSSpulse_IN
18V 0
LSS_IN Idischarge LSS
1.0 A Peak
SRC_HS1

Figure 3. High-Side Gate Driver Functional Schematic IGATE_HS


1.0 A Peak
100 mA Typical
0

-1.0 A Peak

Note GATE_HS is loaded with a 100 nF capacitor in the


chronograms. A smaller load will give lower peak and DC charge or
discharge currents.

Figure 4. High-Side Gate Driver Chronograms

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APPLICATION REQUIREMENTS

Turn-On Turn-Off
For turn-on, the current required to charge the gate source The peak current for turn-off can be obtained in the same
capacitor Ciss in the specified time can be calculated as follows: way as for turn-on, with the exception that peak current for fall
time, tf, is substituted for tr:
I P = Q g /t r = 80 nC/80 ns ≈ 1.0 A
I P = Qg /t f = 80 nC/80 ns ≈ 1.0 A
Where Q g is power MOSFET gate charge and t r is peak current
for rise time. In addition to the dynamic current required to turn off or on
the MOSFET, various application-related switching scenarios
must be considered. These scenarios are presented in
Figure 5. In order to withstand high dV/dt spikes, a low resistive
path between gate and source is implemented during the OFF-
state.
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Flyback spike charges low- Flyback spike pulls down Flyback spike charges low- Flyback spike pulls down
side gate via Crss charge high-side source VGS. side gate via Crss charge high-side source VGS.
current Irss up to 2.0 A. Delays turn-off of high- current Irss up to 2.0 A. Causes increased uncon-
Causes increased uncon- side MOSFET. Delays turn-off of low-side trolled turn-on of high-side
trolled turn-on of low-side MOSFET. MOSFET.
MOSFET.

VBAT VBAT VBAT VBAT


Crss Crss Crss Crss
OFF OFF
VGATE
-VDRN
GATE_HS GATE_HS GATE_HS GATE_HS
ILOAD ILOAD ILOAD ILOAD
L1 L1 Ciss L1 Ciss L1
Ciss Ciss
Crss Crss Crss Crss
Irss
VGATE

GATE_LS GATE_LS GATE_LS GATE_LS


OFF OFF
Ciss Ciss Ciss Ciss

Driver Requirement: Driver Requirement: Driver Requirement: Driver Requirement:


Low Resistive Gate- Low Resistive Gate- High Peak Sink Current Low Resistive Gate-
Source Path During Source Path During Capability Source Path During
OFF-State OFF-State. High Peak OFF-State
Sink Current Capability

Figure 5. OFF-State Driver Requirement

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Low-Drop Linear Regulator External Capacitors Choice


The low-drop linear regulator is supplied by VCC2. If VCC2 External capacitors on the charge pump and on the linear
exceeds 15.0 V, the output is limited to 14.5 V (typical). regulator are necessary to supply high peak current absorbed
during switching.
The low-drop linear regulator provides the 5.0 V for the logic
section of the driver, the Vgs_ls buffered at LR_OUT, and the Figure 7 represents a simplified circuitry of the high-side gate
+14.5 V for the charge pump, which generates the CP_OUT driver. Transistors Tosc1 and Tosc2 are the oscillator-switching
The low-drop linear regulator provides 4.0 mA average current MOSFETs. When Tosc1 is on, the oscillator is at low level.
per driver stage. When Tosc2 is on, the oscillator is at high level. The capacitor
CCP_OUT provides peak current to the high-side MOSFET
In case of the full bridge, that means approximately 16 mA — through HSS during turn-on (3).
8.0 mA for the high side and 8.0 mA for the low side.
VLR_OUT
VLR-OUT
Note: The average current required to switch a gate with a
CP_out
CP_OUT
frequency of 100 kHz is: Tosc2
Tosc2
ICP = Qg * f PWM = 80 nC * 100 kHz = 8.0 mA Ccp
CCP D1
D1 C
Ccp_out
CP_OUT
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In a full-bridge application only one high side and one low side
switches on or off at the same time. C1
C1 C2
C2
D2
D2
Tosc1
Tosc1
Charge Pump
The charge pump generates the high-side driver supply
VVcc
CC
voltage (CP_OUT), buffered at CCP_OUT. Figure 6 shows the
charge pump basic circuit without load.

T1
HSS
(3)
VCP_OUT
CP_OUT
(2) D1
D1 GATE_HS
HS
GATE_HS MOSFET
V
VLR_OUT
LR_OUT High-Side
Ccp
CCP MOSFET
LSS Rg
Rg
T2
Osc.
OSC. A
C2 CCcp_out
CP_OUT
C1
SRC_HS
SRC_HS
D2
D2
(1)
Vbat
V LS
CC Low-Side
MOSFET
MOSFET
Figure 6. Charge Pump Basic Circuit
When the oscillator is in low state [(1) in Figure 6], CCP is pins
Terminals
charged through D2 until its voltage reaches VCC - VD2. When
the oscillator is in high state (2), CCP is discharged though D1 Figure 7. High-Side Gate Driver
in CCP_OUT, and final voltage of the charge pump, VCP_OUT, is
Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator is
about 330 kHz.

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CCP CCP_OUT
CCP choice depends on power MOSFET characteristics and Figure 9 depicts the simplified CCP_OUT current and voltage
the working switching frequency. Figure 8 contains two waveforms. fPWM is the working switching frequency.
diagrams that depict the influence of CCP value on VCP_OUT
average voltage level. The diagrams represent two different Oscillator
Oscillator High Side
High Side Turn On
in high
in High turn on
frequencies for two power MOSFETs, MTP60N06HD and VCP_OUT
V Cp_out Oscillator
State Oscillator
state
in low
Low
MPT36N06V. in
State
state
∆V
∆ VCcp
CP_OUT
_ out

rage V Cp_out
Average
VCP_OUT

21
20 kHz
20KhZ
20.5 100
100 kHz
KhZ
ICP_OUT
I ffPWM
(V)

Cp_out f=330kHz
f = 330 kHz
20 PWM
CP_OUT (v)
VVcp_out

19.5
Freescale Semiconductor, Inc...

19

18.5

18 Peak
5 25 45 65 85 Peak Current
Current

C
Ccp (nF)
CP(nF)
Figure 9. Simplified CCP_OUT Current and Voltage
MTP60N06HD (Qg=50nC) Waveforms
MTP60N06HD (Qg = 50 nC)
MTP60N06HD (Qg = 50 nC) As shown above, at high-side MOSFET turn-on VCP_OUT
voltage decreases. This decrease can be calculated according
21.5 to the CCP_OUT value as follows:
20 kHz

21 100 kHz Qg
∆VCP_OUT =
CCP_OUT
20.5
(V)(V)

Where Qg is power MOSFET gate charge.


VCP_OUT

20
Vcp_out

19.5 CLR_OUT
19 CLR_OUT provides peak current needed by the low-side
MOSFET turn-on. VLR_OUT decrease is as follows:
18.5
5 25 45 65 85
Qg
CCcp (nF)
CP (nF) ∆VLR_OUT =
CLR_OUT
MTP36N06V (Qg = 40 nC)

Figure 8. VCP_OUT Versus CCP Typical Values of Capacitors


The smaller the CCP value is, the smaller the VCP_OUT value In most working cases the following typical values are
is. Moreover, for the same CCP value, when the switching recommended for a well-performing charge pump:
frequency increases, the average VCP_OUT level decreases. For CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF
most of the applications, a typical value of 33 nF is
recommended. These values give a typical 100 mV voltage ripple on VCP_OUT
and VLR_OUT with Qg = 50 nC.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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Protection Load Dump and Reverse Battery


VCC and VCC2 can sustain load a dump pulse of 40 V and
Gate Protection
double battery of 24 V. Protection against reverse polarity is
The low-side driver is supplied from the built-in low-drop ensured by the external power MOSFET with the free-wheeling
regulator. The high-side driver is supplied from the internal diodes forming a conducting pass from ground to VCC.
charge pump buffered at CP_OUT. Additional protection is not provided within the circuit. To protect
the circuit an external diode can be put on the battery line. It is
The low-side gate is protected by the internal linear
not recommended putting the diode on the ground line.
regulator, which ensures that VGATE_LS does not exceed the
maximum VGS. Especially when working with the charge pump,
Temperature Protection
the voltage at CP_OUT can be up to 65 V. The high-side gate
is clamped internally in order to avoid a VGS exceeding 18 V. There is temperature shutdown protection per each half-
bridge. Temperature shutdown protects the circuitry against
Gate protection does not include a flyback voltage clamp that temperature damage by switching off the output drivers. Its
protects the driver and the external MOSFET from a flyback typical value is 175°C with an hysteresis of 15°C.
voltage that can occur when driving inductive load. This flyback
voltage can reach high negative voltage values and needs to be
Freescale Semiconductor, Inc...

dV/dt at VCC
clamped externally, as shown in Figure 10.
VCC voltage must be higher than (SRC_HS voltage minus a
LR_OUT CP_OUT diode drop voltage) to avoid perturbation of the high-side driver.
M1 VCC In some applications a large dV/dt at terminal C2 owing to
IN OUT sudden changes at VCC can cause large peak currents flowing
Output GATE_HS
through terminal C1, as shown in Figure 11.
Driver VGS < 14 V
Under All For positive transitions at terminal C2, the absolute value of
SRC_HS
Conditions the minimum peak current, I C1min, is specified at 2.0 A for a
L1 Inductive
t C1min duration of 600 ns.
Dcl
Flyback Voltage For negative transitions at terminal C2, the maximum peak
M2 Clamp current, IC1max, is specified at 2.0 A for a t C1max duration of
IN OUT
Output GATE_LS 600 ns. Current sourced by terminal C1 during a large dV/dt will
Driver result in a negative voltage at terminal C1 (Figure 11). The
minimum peak voltage VC1min is specified at -1.5 V for a
duration of t C1max = 600 ns. A series resistor with the charge
pump capacitor (Ccp) capacitor can be added in order to limit
the surge current.
Figure 10. Gate Protection and Flyback Voltage Clamp

VCC

IC1max t C1min

I (C1+C2)
0A

t C1 max I C1min

V(LR_OUT)

V(C1)
0V

VC1min

Figure 11. Limits of C1 Current and Voltage with Large Values of dV/dt

33883 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA


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In the case of rapidly changing VCC voltages, the large dV/dt dV/dt at VCC2
may result in perturbations of the high-side driver, thereby
When the external high-side MOSFET is on, in case of rapid
forcing the driver into an OFF state. The addition of capacitors
negative change of VCC2 the voltage (VGATE_HS - VSRC_HS) can
C3 and C4, as shown in Figure 12, reduces the dV/dt of the
source line, consequently reducing driver perturbation. Typical be higher than the specified 18 V. In this case a resistance in
values for R3/R4 and C3/C4 are 10 Ω and 10 nF, respectively. the SRC line is necessary to limit the current to 5.0 mA max. It
will protect the internal zener placed between GATE_HS and
SRC terminals.
In case of high current (SRC_HS>100 mA) and high voltage
(>20 V) between GATE_HSX and SRC_HS an external zener
of 18 V is needed as shown in Figure 12.

VBAT VBOOST

33883
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VCC
CCP_OUT
VCC2 VCC CP_OUT
470 nF M1 M3
VCC2 LR_OUT R1 R2
G_EN CLR_OUT
G_EN
470 nF 50 Ω 50 Ω
CCP C1
C1 GATE_HS1 R4
18 V R3
33 nF C2
C2 SRC_HS1 10 Ω C4
MCU 10 Ω C3
GATE_LS1 10 nF 10 nF DC
IN_HS1
IN_HS1
GATE_HS2 Motor
IN_LS1 18 V
IN_LS1 SRC_HS2
IN_HS2
IN_HS2 GATE_LS2
M2 50 Ω M4
IN_LS2
IN_LS2 GND
50 Ω

Figure 12. Application Schematic with External Protection Circuit

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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PACKAGE DIMENSIONS

DW SUFFIX
20-TERMINAL SOICW
PLASTIC PACKAGE
98ASB42343B
ISSUE H

0.25 M B
2.65
10.55 A 2.35 0.25
10X 0.10
PIN'S 10.05 0.49
NUMBER 20X
0.35 6
1 20 0.25 M T A B

18X
PIN 1 INDEX
1.27
Freescale Semiconductor, Inc...

NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER
12.95
4 12.65
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT
A A THE PLANE WHERE THE BOTTOM OF THE
LEADS EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE
MOLD FLASH, PROTRUSION OR GATE
BURRS. MOLD FLASH, PROTRUSION OR
10 11 GATE BURRS SHALL NOT EXCEED
0.15mm PER SIDE. THIS DIMENSION IS
SEATING
T PLANE
DETERMINED AT THE PLANE WHERE THE
7.6 BOTTOM OF THE LEADS EXIT THE
B 20X
7.4 PLASTIC BODY.
0.1 T 5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
5 INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25mm PER SIDE.
THIS DIMENSION IS DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE
0.75 X45 LEADS EXIT THE PLASTIC BODY.
0.25 6. THIS DIMENSION DOES NOT INCLUDE
0.32 DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT
0.23 CAUSE THE LEAD WIDTH TO EXCEED
0.62mm.

1.0
0.4 7
0
SECTION A-A

33883 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA


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NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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NOTES
Freescale Semiconductor, Inc...

33883 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA


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NOTES
Freescale Semiconductor, Inc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33883


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MC33883/D
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