Expt. No.

2 Verilog Dataflow modeling

Exercise Problems

Exercise No. 2.1 Write a dataflow Verilog code to realize the given logic function in POS form
and verify the design by simulation.
F = (A̅+B ̅ + C). (A
̅+B̅+C ̅ ).(A + B + C). (A + B + C ̅)
Solution:
Verilog Code:

`timescale 1ns / 1ps

module POS(
input A,B,C,
output F
);
wire Abar,Bbar,Cbar;
assign Abar=~A;
assign Bbar=~B;
assign Cbar=~C;
assign F=((Abar|Bbar|C)&(Abar|Bbar|Cbar)&(A|B|C)&(A|B|Cbar));
endmodule

Simulation Results:
Input: A = 0, B = 0, C = 0
Output: F = 0

Exercise No. 2.2 Write dataflow Verilog code for following digital building blocks and verify
the design by simulation: [i] full adder [ii] full subtractor [iii] three variable majority function
[iv] three input exnor function [v] two bit equality detector.

Solution:

[i] Full adder

Verilog Code:
 module fulladder(
input a,b,c,
output sum,carry );
wire x;
assign x = ( a & ~b) | ( ~a & b );
assign sum = ( x & ~c) | ( ~x & c);
assign carry = a&b | b&c | c&a;
endmodule

Simulation Results:
Input: abc = 011
Output: sum = 0, carry = 1

[ii] Full Subtractor

Verilog Code:

module fullsubtractor(
input a,b,c,
output diff,borrow,
inout x
);
assign x = ( a & ~b) | ( ~a & b );
assign diff = ( x & ~c) | ( ~x & c);
assign borrow = ~a&b | ~b&c | ~c&a;
endmodule
Simulation Results:

Input: abc = 111

 Output: diff = 1, borrow = 1

[iii] Three variable majority function

Verilog Code:

module majorityfunction(
input a,b,c,
output m );
assign m = a&c | b&c;
endmodule

Simulation Result:
Input: abc = 001
Output: m = 0
[iv] Equality detector

Verilog Code:

module equalitydetector(
input a,b,
output c
);
assign c = ( ~a & ~b) | ( a & b );
endmodule

Simulation Result:
Input: ab = 00
Output: c = 1

Exercise No. 2.3 Write a dataflow Verilog code for 8- to-3 encoder with enable input and verify
the design by simulation
Verilog Code:

module encoder8to3(
output [2:0] A,
input [7:0] D,
input E
);
wire Ebar;

assign Ebar=~E;
assign A[2]=(D[4]|D[5]|D[6]|D[7])&Ebar;
assign A[1]=(D[2]|D[3]|D[6]|D[7])&Ebar;
assign A[0]=(D[1]|D[3]|D[5]|D[7])&Ebar;
endmodule

Simulation Result:

Input: D [7:0] = 0000 10002

Output: A [2:0] = 0112

Exercise No. 2.4 Write a dataflow Verilog code for 8- to-3 priority encoder and verify the design
by simulation
Verilog Code:
module PriorityEncoder_8_to_3(input [0:7] D, output [2:0] Y)
assign Y[1] = D[2] | D[3]|D[6]|D[7];
assign Y[2] = D[4] | D[5] | D[6] |D[7];
assign Y[0] = D[1] | D[3] | D[5] | D[7];
endmodule

Simulation Result:

Input: D[0:7] = 11110000

Output: Y[2:0] = 011
Exercise No. 2.5 Write a dataflow Verilog code for 4 bit gray- to-binary code converter and
verify the design by simulation.
Verilog Code:
`timescale 1ns / 1ps
module graytobinary(
output B1,B2,B3,B4,
input G1,G2,G3,G4
);
assign B4=G4;
assign B3=G4^G3;
assign B2=G3^G4^G2;
assign B1=G3^G4^G2^G1;
endmodule

Simulation Result:
Input: G[4:1] = 00002
Output: B[4:1] = 00002
Exercise No. 2.6 Write a dataflow Verilog code for 8421 to 2421 code converter and verify the
design by simulation.
Verilog Code:
module code8421to2421(
input a,b,c,d,
output p,q,r,s
);
assign p = a&~b&~c;
assign q = ~a&b | a&~b&~c;
assign r= ~a&c | a&~b&~c;
assign s= ~a&d | ~b&~c&d;
endmodule

Simulation Result:

Input: abcd = 1000

Output: pqrs = 1110

Exercise No. 2.7 Write a dataflow Verilog code for 1 bit magnitude comparator and verify the
design by simulation.

Verilog Code:

module MAG_COMP_1BIT(
input A,B,
input G,E,L
);
wire Abar,Bbar;
assign Abar=~A;
assign Bbar=~B;
assign G=A & Bbar;
assign E=A^~B;
assign L=Abar & B;
endmodule

Simulation Result:

Input: A = 1, B = 1

Output: G = 0, E = 1, L = 0
Exercise No. 2.8 Write a dataflow Verilog code for N bit magnitude comparator and verify the
design by simulation.

Verilog Code:

module nbitcom( a,b, cgt, clt, ceq );

parameter N = 4; // default size
input [N-1:0] a, b;
output cgt, clt, ceq;
assign cgt = (a > b);
assign clt = (a < b);
assign ceq = (a == b);
endmodule

Simulation Result:

Input: a[3:0] = 0010, b[3:0] = 1100

Output: cgt = 0, clt = 1, ceq = 0

Exercise No. 2.9 Write a dataflow Verilog code for 4 bit adder and verify the design by
simulation.

Verilog Code:

`timescale 1ns / 1ps

module adder4bit(
output [3:0] sum,
output c_out,
input [3:0] a,b,
input c_in
);
assign{c_out,sum} = a+b+c_in;
endmodule

Simulation Result:

Input: a[3:0] = 00112, b[3:0] = 10012, c_in = 12

Output : c_out = 02, sum[3:0] = 11012

 Expt. No. 3 Verilog Sequential Modeling Examples
Exercise Problems
Exercise No. 3.1 Write the sequential Verilog code for N bit full adder (assume N = 4 and use
for-loop statement)
Verilog Code:

Simulation Result:

Exercise No. 3.2 Write the sequential Verilog code for synchronous mod 5 counter.
Verilog Code:

module counter_mod5 ( clk ,reset ,dout );

output [2:0] dout ;
reg [2:0] dout ;
inputclk ;wire clk ;input reset ;wire reset ;
initialdout = 0;
always @ (posedge (clk))
begin
if (reset) dout<= 0;
else if (dout<4)
dout<= dout + 1;
else dout<= 0;
end
endmodule

Simulation Result:

Exercise No. 3.3 Write a sequential Verilog code for 4 bit priority encoder.
Verilog Code:
Simulation Result:

Exercise No. 3.4 Write the sequential Verilog code for Master-slave JK flip-flop (assume delay
of master and slave as 2ns and 1ns respectively)
Verilog code:

Module jkffmasterslave(Q,Qn,C,J,K,Resetn);
output Q;
output Qn;
 input C,J,K,Resetn;
wire mq;
wire mqn;
wire cn;
wire j1,k1,j2,k2;
assign j2=!Resetn? 0 : J1;
assign K2=!Resetn ? 1 : K1;
and(J1,J,Qn);
and(K1,K,Q);
not(Cn,C);
srlatchmaster(mq,mqn,c,J2,K2);
srlatchslave(q,qn,cn,mq,mqn);
endmodule

Simulation Result:

Exercise No. 3.5 Write sequential Verilog code for 4 bit universal shift register
Verilog Code:
Simulation Result:

Exercise No. 3.6 Write sequential Verilog code to model ACTEL ACT 1 Logic Module (Use
initial statement).
Verilog Code:

module act1(a,b,c,d,e,f,x,y,dout);
output dout;
input a,b,c,d,e,f,x,y;
wire p,q,r;
initial
begin
p = (a&(~c)|(b&(c));
q = (d&(~f)|(e&(f));
r = x|y;
dout = (p&(~r)|(b&(r));
endmodule

Simulation Result:
 Expt. No. 4 Verilog structural modeling

Exercise Problems
Exercise No. 4.1 Write structural Verilog code for mod-10 ripple counter and verify the design
by simulation

Exercise No. 4.2(a) Write structural Verilog code for 4 bit SIPO/ PISO shift register and verify
the design by simulation

Verilog Code:

`timescale 1ns / 1ps

module sipo ( din ,clk ,reset ,dout );
output [0:3] dout;
input din ;
input clk ;
input reset ;

d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(dout[0]));

d_flip_flop u1 (.din(dout[0]),
.clk(clk),
.reset(reset),
.dout(dout[1]));

d_flip_flop u2 (.din(dout[1]),
.clk(clk),
.reset(reset),
.dout(dout[2]));

d_flip_flop u3 (.din(dout[2]),
.clk(clk),
.reset(reset),
.dout(dout[3]));

endmodule

// -------------- D flip flop design - -----------------------

module d_flip_flop ( din ,clk ,reset ,dout );
 output dout ;
reg dout;
input din ;
input clk ;
input reset ;

always @ (posedge clk)

begin
if (reset)
dout <= 1;
else
dout <= din;
end
endmodule

Simulation Result:

Input :

Output:

Exercise No. 4.2(b) Write structural Verilog code for 4 bit PISO shift register and verify the
design by simulation

Verilog Code:

`timescale 1ns / 1ps

module sipo ( din ,clk ,reset ,dout,shift_load );
output dout;
input [0:3]din;
input clk;
input reset;
input shift_load;
wire [0:12]s;
d_flip_flop u0 (.din(din[0]),
.clk(clk),
.reset(reset),
.dout(s[2]));
d_flip_flop u1 (.din(s[10]),
.clk(clk),
.reset(reset),
.dout(s[3]));

d_flip_flop u2 (.din(s[11]),
.clk(clk),
.reset(reset),
.dout(s[4]));

d_flip_flop u3 (.din(s[12]),
.clk(clk),
.reset(reset),
.dout(dout));

not n1(s[0],shift_load);

and a1(s[1],shift_load,s[2]),
a2(s[5],din[1],s[0]),
a3(s[6],s[3],shift_load),
a4(s[7],s[0],din[2]),
a5(s[8],s[4],shift_load),
a6(s[9],s[0],din[3]);

or or1(s[10],s[1],s[5]),
or2(s[11],s[6],s[7]),
or3(s[12],s[8],s[9]);

endmodule
// -------------- D flip flop design - -----------------------
module d_flip_flop ( din ,clk ,reset ,dout );
output dout ;
reg dout;

input din ;
input clk ;
input reset ;
initial
begin

dout=0;

end
always @ (posedge clk)
begin
 if (reset)
dout <= 1;
else
dout <= din;
end

endmodule

Simulation Result:

Input :

Output:

Exercise No. 4.3 Write structural Verilog code for 4 bit carry look ahead adder and verify the
design by simulation
Verilog Code:

Simulation Result:

Input :

Output:

Exercise No. 4.4 Write structural Verilog code for 4 bit carry save multiplier and verify the
design by simulation.
Verilog Code:

`timescale 1ns / 1ps

module CSA(
input X,Y,Z,
output sum, carry
);
assign sum=X^Y^Z;
assign carry=((X&Y)|(Z&(X^Y)));
endmodule
 module CS_mul(
input [0:3] A,
input [0:3] B,
output [7:0] s
);
wire [1:17] W;
wire [1:16] p;
and a1(p[1],A[0],B[0]),
a2(p[2],A[1],B[0]),
a3(p[3],A[2],B[0]),
a4(p[4],A[3],B[0]),
a5(p[5],A[0],B[1]),
a6(p[6],A[1],B[1]),
a7(p[7],A[2],B[1]),
a8(p[8],A[3],B[1]),
a9(p[9],A[0],B[2]),
a10(p[10],A[1],B[2]),
a11(p[11],A[2],B[2]),
a12(p[12],A[3],B[2]),
a13(p[13],A[0],B[3]),
a14(p[14],A[1],B[3]),
a15(p[15],A[2],B[3]),
a16(p[16],A[3],B[3]);

assign s[0]=p[1];

CSA C1(p[5],p[2],0,s[1],W[1]),
C2(p[6],p[3],W[1],W[2],W[3]),
C3(p[7],p[4],W[3],W[4],W[7]),
C4(p[8],p[11],W[7],W[10],W[12]),
C5(p[12],p[15],W[12],W[15],W[16]),
C6(W[2],p[9],0,s[2],W[5]),
C7(W[4],p[10],W[5],W[6],W[8]),
C8(p[14],W[10],W[8],W[11],W[13]),
C9(p[13],W[6],0,s[3],W[9]),
C10(W[11],W[9],0,s[4],W[14]),
C11(W[13],W[15],W[14],s[5],W[17]),
C12(p[16],W[17],W[16],s[6],s[7]);
endmodule

Simulation Result:

Input:

Output:
Exercise No. 4.5 Write structural Verilog code for 4- bit binary-to-gray code converter and
verify the design by simulation.
Verilog Code:

Simulation Result:

Input:

Output:

Expt. No. 5 Verilog Switch Level and Mixed-mode Modeling Examples

Exercise Problems

Exercise No. 5.1 Write a switch level Verilog code for the following combinational logic using
both gate based and TG based approach
Y = (AB + CD)’
Verilog Code:

Simulation Result:

Exercise No. 5.2 Write switch level Verilog code for a 3 input CMOS NAND gate with test
benches

Verilog Code:

Simulation Result:

Exercise No. 5.3 Write a Verilog code for ALU using mixed style of modelling. Model the
addition operation using carry-look ahead adders. The operation code for selection is given
below

Operation Code Operation

00 Addition
 01 Multiplication
10 Integer Division
11 No operation
Verilog Code:

Simulation Result:

Expt. No. 6 Verilog examples using task and functions, user defined primitive

Exercise Problems

Exercise No. 6.1 Write a Verilog code of 4 to 1 multiplexer as UDP and verify the design
description by simulation.
Solution:
Verilog Code:

//4:1 multiplexer as a UDP

primitive udp_mux4 (out, s1, s0, d0, d1, d2, d3);
input s1, s0, d0, d1, d2, d3;
output out;
table //define state table
//inputs are in the same order as the input list
// s1 s0 d0 d1 d2 d3 : out comment is for readability
0 0 1 ? ? ? : 1; //? is "don't care"
0 0 0 ? ? ? : 0;
0 1 ? 1 ? ? : 1;
0 1 ? 0 ? ? : 0;
1 0 ? ? 1 ? : 1;
1 0 ? ? 0 ? : 0;
1 1 ? ? ? 1 : 1;
1 1 ? ? ? 0 : 0;
? ? 0 0 0 0 : 0;
? ? 1 1 1 1 : 1;
endtable
endprimitive

module udp_mux4_tb;
reg s1, s0, d0, d1, d2, d3;
wire out;
initial
begin
//set the input lines to known values
 d0 = 1; d1 = 0; d2 = 1; d3 = 0;
//display the input values
#10 $display ("d0=%b, d1=%b, d2=%b, d3=%b \n",
d0, d1, d2, d3); // \n is new line
//continued on next page

//select d0 = 1
s1 = 0; s0 = 0;
#10 $display ("s1=%b, s0=%b, output=%b \n",
s1, s0, out);
//select d1 = 0
s1 = 0; s0 = 1;
#10 $display ("s1=%b, s0=%b, output=%b \n",
s1, s0, out);
//select d2 = 1
s1 = 1; s0 = 0;
#10 $display ("s1=%b, s0=%b, output=%b \n",
s1, s0, out);
//select d3 = 0
s1 = 1; s0 = 1;
#10 $display ("s1=%b, s0=%b, output=%b \n",
s1, s0, out);
#10 $stop;
end
//instantiate the module into the test bench.
//if instantiating only the primitive with no module,
//then instantiation must be done using positional notation
udp_mux4 inst1 (out, s1, s0, d0, d1, d2, d3);
endmodule

Simulation Result:

Input: d3 = 0, d2 = 1, d1 = 0, do = 1, s1 = 1, s0 = 0

Output: out = 1

Exercise No. 6.2 Write a Verilog code for 4-bit binary to Gray code converter using two-input
xor gate UDP and verify the design by simulation.
Solution:
Verilog Code:
//UDP for a 2-input exclusive-OR
primitive udp_xor2 (z1, x1, x2);
input x1, x2;
output z1;
//define state table
table
//inputs are in the same order as the input list
// x1 x2 : z1; comment is for readability
0 0 : 0;
0 1 : 1;
1 0 : 1;
1 1 : 0;
endtable
endprimitive

//binary-to-Gray code converter using a UDP

module bin_to_gray_udp (b3, b2, b1, b0, g3, g2, g1, g0);
input b3, b2, b1, b0;
output g3, g2, g1, g0;
//instantiate the udps
buf (g3, b3);
udp_xor2 (g2, b3, b2);
udp_xor2 (g1, b2, b1);
udp_xor2 (g0, b1, b0);
endmodule

Simulation Result:

Input: b[3:0] = 01112

Output: g[3:0] = 01002

Exercise No. 6.3 Write a Verilog code to define and call the function that evaluates the two-
input ex-or expression and verify the code by simulation.
Solution:

Verilog Code:

module Func_exm (a1, b1, d1);

input a1, b1;
output d1;
reg d1;
always @ (a1, b1)
begin
/*The following statement calls the function exp
and stores the output in d1.*/
d1 = exp (a1, b1);
end
function exp ;
input a, b;
begin
exp = a ^ b;
end
endfunction
endmodule

Simulation Result:

Input: a1 = 0, b1 = 0

Output: d1= 0

Exercise No. 6.4 Write a Verilog code for half-adder using task and then describe the behaviour
of full-adder from two half-adders.
Solution:

Verilog Code:

module fadd( x, y, cin, sum,cout);

input x, y, cin;
output sum, cout;
reg sum1, c1,c2, cout, sum;
 always@(x, y, cin)
begin
haddr (sum1,c1,y,cin);
haddr (sum,c2,sum1,x);
cout= c1|c2;
end
task haddr; // this task describes the half adder
output sh, ch;
input ah,bh;
begin
sh= ah^bh;
ch= ah & bh;
end
endtask
endmodule

Simulation Result:

Input: x = 1, y = 0, cin = 1

Output: sum = 0, cout = 1

Exercise No. 6.5 Write a Verilog code for the positive-edge-triggered D flip-flop with active low
reset as UDP.
Solution:
Verilog code:
primitive udp_dff_edge1 (q, d, clk, rst_n);
input d, clk, rst_n;
output q;
reg q; //q is internal storage
//initialize q to 0
initial
q = 0;
//define state table
table
//inputs are in the same order as the input list
// d clk rst_n : q : q+; q+ is the next state
0 (01) 1 : ? : 0; //(01) is rising edge
1 (01) 1 : ? : 1; //rst_n = 1 means no rst
1 (0x) 1 : 1 : 1; //(0x) is no change
0 (0x) 1 : 0 : 0;
? (?0) 1 : ? : -; //ignore negative edge
//reset case when rst_n is 0 and clk has any transition
? (??) 0 : ? : 0; //rst_n = 0 means reset
//reset case when rst_n is 0. d & clk can be anything, q+=0
? ? 0 : ? : 0;
//reset case when 0 --> 1 transition on rst_n. Hold q+ state
? ? (01) : ? : -;
//non-reset case when d has any trans, but clk has no trans
(??) ? 1 : ? : -; //clk = ?, means no edge
endtable
endprimitive

`timescale 1 ns / 1 ps

//test bench for the positive-edge-triggered D flip-flop

module udp_dff_edge1_tb;
reg d, clk, rst_n;
wire q;
//display variables
initial
$monitor ("rst_n=%b, d=%b, clk=%b, q=%b",
rst_n, d, clk, q);
//apply input vectors
initial
begin
#0 rst_n=1'b0; d=1'b0; clk=1'b0;
#10 rst_n=1'b1; d=1'b1; #2 clk=1'b1;
#10 rst_n=1'b1; d=1'b1; #2 clk=1'b0;
#10 rst_n=1'b1; d=1'b0; #2 clk=1'b1;
#10 rst_n=1'b1; d=1'b1; #2 clk=1'b0;
#10 rst_n=1'b1; d=1'b1; #2 clk=1'b1;
#10 rst_n=1'b1; d=1'b0; #2 clk=1'b0;
#10 $stop;
end
//instantiation must be done by position, not by name
udp_dff_edge1 inst1 (q, d, clk, rst_n);
endmodule

Simulation Results
 Input: rst_n = 12 ; d = 1; clk = ↑ (0 to 1 transition) ;

Output: q = 1

Expt. No. 7 Verilog examples using task and functions, user defined primitive

Exercise No. 7.1 Synthesize and implement the sequential Verilog model of 4 bit up down
counter [make use of control and reset inputs] using XILINX SPARTAN 3 chip and display the
decimal equivalent output using seven segment display. Use clock division principle.

Solution :
Verilog code:
module updown_sevenseg(up_down,display,control,reset,clk,counter);
input up_down,clk,reset;
output [3:0] counter;
output [7:0] display;
output [3:0] control;
reg [3:0] control;
reg [7:0] display;
reg [3:0] counter;
integer temp;
reg clkdiv;
initial
begin
temp=0;
counter=4'b0000;
clkdiv=1'b0;
end
always@(posedge clk)
begin
temp=temp+1;
if (temp==2000000)
begin
clkdiv=~clkdiv;
temp=0;
end
end
always@(posedge clkdiv)
begin
if(reset)
counter=4'b0000;
else if(up_down==1'b1)
counter=counter+1;
else if(up_down==1'b0)
counter=counter-1;
control=4'b0111;
case (counter)
4'd0:display=8'b11111100;
4'd1:display=8'b01100000;
4'd2:display=8'b11011010;
4'd3:display=8'b11110010;
4'd4:display=8'b01100110;
4'd5:display=8'b10110110;
4'd6:display=8'b10111110;
4'd7:display=8'b11100000;
4'd8:display=8'b11111110;
4'd9:display=8'b11110110;
4'd10:display=8'b11111010;
4'd11:display=8'b00111110;
4'd12:display=8'b10011100;
4'd13:display=8'b01111010;
4'd14:display=8'b10011110;
4'd15:display=8'b10001110;
endcase
end
endmodule

#PACE: Start of PACE I/O Pin Assignments

NET "clk" LOC = "P52" ;
NET "control<0>" LOC = "P23" ;
NET "control<1>" LOC = "P24" ;
NET "control<2>" LOC = "P26" ;
NET "control<3>" LOC = "P27" ;
NET "display<0>" LOC = "P21" ;
NET "display<1>" LOC = "P18" ;
NET "display<2>" LOC = "P17" ;
NET "display<3>" LOC = "P15" ;
NET "display<4>" LOC = "P14" ;
NET "display<5>" LOC = "P13" ;
NET "display<6>" LOC = "P12" ;
NET "display<7>" LOC = "P1" ;
NET "reset" LOC = "P84" ;
NET "up_down" LOC = "P85" ;
Exercise No. 7.2 Write a Verilog code to generate the ramp waveform and display it on the
oscilloscope using XILINX SPARTAN 3 FPGA and DAC interfacing board.

Solution:
Verilog code:
module squarewave(clk,reset,dacout);
input clk,reset;
output [7:0] dacout;
reg [7:0] dacout;
integer count,temp1;
reg temp2;
reg clkms;
initial
begin
count=0;
clkms=1'b0;
dacout=8'd0;
temp1=0;
temp2=1'b0;
end

always @(posedge clk)

begin
count=count+1;
if (count==16)
begin
count=0;
clkms=~clkms;
end
end
always @(posedge clkms)
begin
if(reset)
dacout=8'd0;
else
begin
temp1=temp1+1;
if (temp1==128)
begin
temp2=~temp2;
temp1=32'd0;
end
end
case (temp2)
3'd0:dacout=8'd0;
3'd1:dacout=8'd255;
 endcase
end
endmodule

Procedure:

[i] Connect DIP switch to FRC2

[ii] Connect DAC IN to FRC5
[iii]Connect DAC OUT to Oscilloscope probe
[iv] Put RESET DIP switch in OFF position

#PACE: Start of PACE I/O Pin Assignments

NET "clk" LOC = "p52" ;
NET "dacout<0>" LOC = "p1" ;
NET "dacout<1>" LOC = "p12" ;
NET "dacout<2>" LOC = "p13" ;
NET "dacout<3>" LOC = "p14" ;
NET "dacout<4>" LOC = "p15" ;
NET "dacout<5>" LOC = "p17" ;
NET "dacout<6>" LOC = "p18" ;
NET "dacout<7>" LOC = "p21" ;
NET "reset" LOC = "p84" ;

Output waveform

Ramp output waveform (displayed on CRO)

Exercise No. 7.3 Interface the stepper motor with XILINX SPARTAN 3 board and run a
Verilog code to control stepper motor operations like clockwise/ anticlockwise rotation, step size
control, variation of speed (slow/ medium and high)

Verilog code:

module motor(clk, anticlk, slow, med, high,stepout );

input clk, anticlk, slow, med, high;
output reg [3:0]stepout;
reg [20:0] divider;//=20'b000000000000000000000;
reg clk1;
reg [1:0] count;

always @(posedge clk )

begin
divider=divider+1;
if (slow)
clk1=divider[20];
else if (med)
clk1=divider[18];
else if (high)
clk1=divider[15];
else
clk1=0;

end

always @(posedge clk1)

begin
if (anticlk)
begin
count= count-1;
end
else
count = count +1;
end

always @(count)
begin
case (count)
2'b00 : stepout=4'b1100 ;
2'b01 : stepout=4'b0110 ;
2'b10 : stepout=4'b0011 ;
2'b11 : stepout=4'b1001 ;
endcase
end
endmodule

#PACE: Start of PACE I/O Pin Assignments

NET "anticlk" LOC = "P74" ;
NET "clk" LOC = "P52" ;
NET "high" LOC = "P83" ;
NET "med" LOC = "P80" ;
NET "slow" LOC = "p82" ;
NET "stepout<0>" LOC = "P141" ;
NET "stepout<1>" LOC = "P2" ;
 NET "stepout<2>" LOC = "P4" ;
NET "stepout<3>" LOC = "P5" ;

Procedure:

[i] Make the connection between FRC1 of the FPGA board with the Dip switch of
INTERFACING board. If anti-clk Dip switch is ON, direction will be anticlockwise
otherwise direction will be clockwise.

[ii] Make the connection between FRC9 of the FPGA board with the STEPPER MOTOR
INPUT of INTERFACING board. Connect STEPPER MOTOR OUTPUT TO STEPPER
MOTOR.

[iii] Connect the downloading cable and power supply to the FPGA board.

[iv] Then open the Xilinx iMPACT software and select the respective BIT file and click
program.

[v] Apply inputs to DIP SWITCHES i.e. HIGH, MED and LOW and observe the output in the
stepper motor.

Expt. No. 9 Verilog examples using CADENCE

Exercise No. 9.1 Write a Verilog code and test bench to model and simulate 4 bit ripple counter.

Solution :
Verilog code:
module ripple_counter (clock, toggle, reset, count);
input clock, toggle, reset;
output [3:0] count;
reg [3:0] count;
wire c0, c1, c2;
assign c0 = count[0], c1 = count[1], c2 = count[2];

always @ (posedge reset or posedge clock)

if (reset == 1'b1) count[0] <= 1'b0;
else if (toggle == 1'b1) count[0] <= ~count[0];

always @ (posedge reset or negedge c0)

if (reset == 1'b1) count[1] <= 1'b0;
else if (toggle == 1'b1) count[1] <= ~count[1];

always @ (posedge reset or negedge c1)

if (reset == 1'b1) count[2] <= 1'b0;
 else if (toggle == 1'b1) count[2] <= ~count[2];
always @ (posedge reset or negedge c2)
if (reset == 1'b1) count[3] <= 1'b0;
else if (toggle == 1'b1) count[3] <= ~count[3];
endmodule
module ripple_counter_t ;// Testbench for ripple counter
reg clock,toggle,reset;
wire [3:0] count ;
ripple_counter r1 (clock,toggle,reset,count);
initial
clock = 1'b0;
always
#5 clock = ~clock;
initial
begin
reset = 1'b0;toggle = 1'b0;
#10 reset = 1'b1; toggle = 1'b1;
#10 reset = 1'b0;
#190 reset = 1'b1;
#20 reset = 1'b0;
#100 reset = 1'b1;
#40 reset = 1'b0;
#250 $finish; //stopped time 620 ns
end
initial
$monitor ($time, " output q = %d", count);
endmodule

Simulation Results:

Input: reset = 0, toggle = 1

Output: count [3:0] = 0000 - - 0001 - - 0010 - - 0011 --

Fig. 1. Simulated output of 4 bit ripple counter.

Exercise No. 9.2 Write a Verilog code for 4 bit ripple carry adder using structural modelling.
Also write a test bench to simulate the code.
Solution :
Verilog code:
module fulladd (cin,x,y,s,cout);

input cin,x,y;
output s,cout;
assign s = x^y^cin;
assign cout =( x & y) | (x & cin) |( y & cin);

endmodule
//Instantiation of above module
module adder4 ( carryin,x,y,sum,carryout);
input carryin;
input [3:0] x,y;
output [3:0] sum;
output carryout;
fulladd stage0 (carryin,x[0],y[0],sum[0],c1);
fulladd stage1 (c1,x[1],y[1],sum[1],c2);
fulladd stage2 (c2,x[2],y[2],sum[2],c3);
fulladd stage3 (c3,x[3],y[3],sum[3],carryout);
endmodule

//Test bench for adder

module adder4_t ;
reg [3:0] x,y;
reg carryin;
wire [3:0] sum;
wire carryout;
adder4 a1 ( carryin,x,y,sum,carryout);
initial
begin
$monitor($time,"SUM=%d",sum);
x = 4'b0000; y= 4'b0000;carryin = 1'b0;
#20 x =4'b1111; y = 4'b1010;
#40 x =4'b1011; y =4'b0110;
#40 x =4'b1111; y=4'b1111;
#50 $finish;
end
endmodule

Simulation Results:
Input: x[3:0] = 11112, y[3:0] = 10102
Output: carryout = 12 , sum[3:0] = 10012
 At console window, t = 0, 20, 60, 100 Sum is 0, 9, 1, 14. Stopped time is 150 ns.
Fig. 2. Waveform and console output of 4 bit ripple carry adder.

Exercise No. 9.3 Write a Verilog code and test bench to model and simulate following:
[i] D flip-flop [ii] T flip-flop

Solution :
Verilog code:
[i] D flip-flop

module d_ff(q,clk,n_rst,din);
output q;
input clk,din,n_rst;
reg q;
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
q <= 1'b0;
else
q <= din;
end
endmodule
module d_ff_test;
reg clk, din, n_rst;
wire q;
d_ff df1 (q, clk, n_rst, din);
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
din = 1'b0;
n_rst = 1'b1;
#20 n_rst = 1'b0;
#10 din = 1'b1;
 #20 n_rst = 1'b1;
#20 din = 1'b0;
#10 ;
end
always
#5 $display ($time," clk=%b din=%b q=%b", clk, din, q);
initial
#100 $finish;
endmodule

Simulation Results:

Fig. 3 (i). Simulated output of D flip-flop.

[ii] T flip-flop

module t_ff(q,qbar,clk,tin,rst);
output q,qbar;
input clk,tin,rst;
reg tq;
always @(posedge clk or negedge rst)
begin
if(!rst)
tq <= 1'b0;
else
begin
if (tin)
tq <= ~tq;
end
end
assign q = tq;
assign qbar = ~q;
endmodule

module t_ff_test;
reg clk,tin,rst;
wire q,qbar;
t_ff t1(q,qbar,clk,tin,rst);
initial
 clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
rst = 1'b0; tin = 1'b0;
#30 rst = 1'b1;
#10 tin = 1'b1;
#205 tin = 1'b0;
#300 tin = 1'b1;
#175 tin = 1'b0;
#280 rst = 1'b0;
#20 rst = 1'b1;
#280 tin = 1'b1;
#10 ;
end
initial
#2000 $finish;
Endmodule

Simulation Results:

Fig. 3(ii) Simulated output of T flip-flop.

Exercise No. 9.4 Write a Verilog code and test bench to model and simulate a CMOS inverter
using PMOS and NMOS switches.

Solution :
Verilog code:
module inverter
(out,in);
// Declarations of I/O, power and ground lines
output out;
input in;
supply1 pwr;
supply0 gnd;
// Instantiate pmos and nmos switches
pmos (out,pwr,in);
nmos (out,gnd,in);
 endmodule
// Testbench for Inverter Module
module inv_test;
wire out ;
reg in ;
// Instantiate inverter Module
inverter i1
(out,in) ;
// Display
task display ;
begin
$display
(
"time=%0d" , $time , " ns"
, " Input=" , in
, " Output=", out
);
end
endtask
// Apply Stimulus
initial
begin
in = 1'b0 ; #10 ; display ;
in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
in = 1'bz ; #10 ; display ;
end
endmodule

Simulation Results:

Input: z = 1

Output: x = 0

Fig. 4. Simulated output of CMOS inverter

Exercise-9.5: Write a Verilog code for a buffer using switch level modelling. Also write a test
bench to simulate the code.

Solution:

Verilog Code:

module inverter (Y,A);

// Declarations of I/O , Power and Ground Lines
output Y;
input A;
supply1 pwr;
supply0 gnd;
// Instantiate pmos and nmos switches
pmos (Y,pwr,A);
nmos (Y,gnd,A);
endmodule
// Define our own Buffer
module buffer
(out,in);
// Declarations of I/O Lines
output out;
input in;
// Wire Declaration
wire a;
// Instantiate Inverter module
inverter i1 (a,in);
inverter i2 (out,a);
endmodule

// Testbench for Buffer Module

module buf_test;
wire out ;
reg in ;
// Instantiate Buffer Module
buffer b1(out,in) ;
// Display
task display ;
begin
$display
(
"time=%0d" , $time , " ns"
, " Input=" , in
, " Output=", out
);
end
endtask
 // Apply Stimulus
initial
begin
in = 1'b0 ; #10 ; display ;
in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
in = 1'bz ; #10 ; display ;
end
endmodule

Simulation Results:

Fig. 5. Simulated output of buffer.