The Eighth International Conference on Electronic Measurement and Instruments ICEMI’2007

Verification of AMBA Bus Model Using SystemVerilog

Han Ke1 Deng Zhongliang1 Shu Qiong2
(1. School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China; 2. School of
Electronic and Information Engineering, Beihang University, Beijing 100083, China)

Abstract: A verification environment to verify an ARM-based hardware concepts such as cycles, tri-state values,
SoC (System-on-Chip) by using SystemVerilog is presented in wires, just like Verilog hardware languages. So
this paper. The new verification constructs can be easily reused SystemVerilog can be used to simulate the HDL
for the objected-oriented feature of SystemVerilog. The paper design and verify them by high level test case.
also introduced how to design the AMBA (Advanced In this paper, how to put up the simulation
Microprocessors Bus Architecture) verification IP (Intellectual environment using SystemVerilog is introduced. The
Property) by SystemVerilog, which include AHB (Advanced simulation environment using by SystemVerilog is
High Performance Bus) Master and AHB Monitor. The efficient and high-performance. The paper discusses
verification IP can be reused to verify any AMBA protocol the usage experience to verify an SoC by the AMBA
based SoC. To reduce the time spending in the verification, a verification IP and the AHB monitor.
reference model designing method is also discussed in the During verify the SoC, a great deal of visual
paper. simulation waveform inspection is required. To
Keywords: SoC, AMBA, SystemVerilog, Reference model, generate the waveform will be time-consuming. The
Verification IP paper presents SoC bus transaction verification IP
1 Introduction written by SystemVerilog, which are called reference
model to compare the behavior of the DUT. The IP
The tremendous progress of VLSI technology can be integrated into SystemVerilog simulation
enables the integration of more than several million environment. By using the reference model, we can
transistors in a single chip to make a SoC greatly reduce the waveform inspection time.
(System-on-Chip). This has made verification the
most critical bottleneck in the chip design flow.
2 SystemVerilog Verification
Roughly 70 to 80 percent of the design cycle is spent Environment
in functional verification. However, the test program
The main purpose of the verification environment
need to provide more automation to maximize the
is to generate stimulus, apply stimulus to the DUT
functional coverage from each test case and reduce the
(design under test), and check results to verify that the
time needed to create a test case[1-3]. So there is a
function is correct. Then test cases may be modified or
tradeoff between the sophistication of the verification
added referring to the coverage reports. By using
program and the time spent developing it.
SystemVerilog we can easily do these works.
SystemVerilog is a special hardware verification
2.1 Introduction of the Verification Environment
language to be used in function verification. It
provides the high-level data structures available in Figure 1 shows the contracture of the
object-oriented languages, such as C++. These data SystemVerilog verification environment. The
structures enable a higher level of abstraction and environments include the DUT written by Verilog
modeling of complex data types. The SystemVerilog HDL, SystemVerilog test bench which include
also provides constructs necessary for modeling SystemVerilog interface, simulation top module, and
test program. In the SystemVerilog test bench, the
generator can be used to create constrained random
test vectors. These test vectors are sent to the driver,
1-4244-1135-1/07/$25.00 ©2007 IEEE.
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and then the driver can stimulate the DUT. The

System Verilog Testbench
monitor generates verification reports on states,
Coverage
transactions and model messages. Also the result can
be checked by the checker and added to the coverage Generator Checker

reports. These test bench components are all designed Channel Channel

by SystemVerilog. The object-oriented feature of Driver Monitor

SystemVerilog can greatly enhance the reusability of

test bench components. Modport Modport
As is divided in the Figure 1, there are three parts of Interface

the verification environment. The first is the DUT, DUT

which is the design top of the SoC to be verified. The
second is the test program (SystemVerilog Test bench), Fig. 1 SystemVerilog Verification Environment
which include the main test tasks. The interface part
(Interface) is the interface to be used to joining the The DUT we designed is shown in the Fig. 2. It is
DUT and the test program. All the parts are instanced an AMBA based SoC that include the AHB bus and
in the test-top. The verification environment will also the APB bus. Two AHB masters and four AHB slaves
be reused, without modifications, by as many test are integrated into the SoC. AHB masters are
cases as possible to minimize the amount of codes ARM7TDMI and DMA. AHB slaves are ROM,
required to verify the DUT. SRAM and APB BUS.

ARM 7TDMI
Reference
DMA Generator (Replace by
Model
VIP Master)

Master Master
Arbiter AHB AHB
/Decoder Monitor
Slave Slave Slave Slave

Peripheral Bridge ROM SRAM Flash

APB

Fig. 2 Contracture of the DUT

higher layers of the verification environment, such as
2.2 Use of the Verification IP the generator, stimulate the DUT. The connection
To verify the DUT in the SystemVerilog between the driver and the generator requires a
environment, we replace the ARM7TDMI by a VIP channel instance. SystemVerilog gives a template
(Verification IP) Master, which is designed by class, vmm_channnel[5], which can be specialized
SystemVerilog. It is a class to be reused in the based on the data or transaction descriptor it will
verification. The VIP Master serves as a driver carry.
including trans-actor, and stimulates the DUT. To The physical level interface is used to connect the
observe the behavior of the VIP master and the DUT. By SystemVerilog we use the modport
response of the DUT, An AHB Monitor IP is used definition to use the physical level interface. The
which can monitor the AHB protocol [4]. The Monitor interface between the DUT and the test program
IP is also designed by SystemVerilog as a class. which include the VIP Master and the Monitor is
The VIP Master and the Monitor IP have the defined in Fig. 3. The definition includes a list of all
physical level interface and the transaction level the pins, a list of clocking signals, two clocking blocks
interface. The transaction level interface lets the of related clocked signals and two modports defining.
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The ARM7TDMI master ports are wired by the VIP Generate configuration Wait for end
env.gen_cfg() env.wait_for_end()
master. The ports used by the monitor are wired
directly from the AHB bus. Build environment Stop environment
env.build() env.stop()
interface test _ahb_if(input hclk);
logic hresetn; Reset the DUT Sweep DUT and reports
logic [`AHB_DATA_WIDTH-1:0] hrdata; env.reset_dut() env.cleanup()
ĂĂ
//interface only used for the monitor
logic [`AHB_ADDR_WIDTH -1:0] haddr; Configure DUT Report pass/fail
logic hsel; env.cfg_dut env.report()
logic [`AHB_DATA_WIDTH-1:0] hwdata;
logic hgrant;
Start environment
logic hwrite; End Test
env.start()
ĂĂ
//interface only used for the VIP Master
logic [`AHB_ADDR_WIDTH -1:0] arm 1_haddr; Fig. 4 Executing Flow in the Verification
logic [`AHB_DATA_WIDTH-1:0] arm1_hwdata;
logic [`AHB_DATA_WIDTH-1:0] arm1_hrdata;
logic arm1_hgrant;
logic arm1_hwrite;
2.3 VIP Master Behavior Analysis
ĂĂ
clocking monitor_cb @(posedge HClk);
//default input #1skew output #0;
The VIP Master has two operating modes:
input hresetn; protocol-related and buffer access. Protocol related
input hrdata;
input haddr; features generate bus cycles and transfer responses to
input hesl;
input hwdata; slave response types. Buffer access features allow us
ĂĂ
endclocking
to create burst transfers in advance and reuse the burst
clocking master_cb @(posedge HClk); information. So it can give the DUT proper test to
default input#1 output #1;
input hresetn verify DUT’s protocol feature. VIP Master is not as
output arm1_haddr;
output arm1_hwata;
same as the ARM model. In the design, we use the
input arm1_hrata; ARM7TDMI core. The ARM7TDMI core uses a
output arm1_hwrite;
ĂĂ pipeline to increase the speed of the flow of
endclocking
modport Master(clocking master_cb); instructions to the processor. This allows several
modport Monitor(clocking monitor_cb);
endinterface
operations to take place simultaneously. A three stage
pipeline is used so instructions are executed in three
stages: fetch, decode and execute, as shown in fig
Fig. 3 Modport Define in the Test bench 5.While the instruction to be decoded by ARM may be
not necessary to verify.
During the simulation, the generator will transfer
test vectors by the channel to the VIP Master. Then the
master will drive the slaves. The reference model is
used to dynamically predict the response of the VIP
Master and compare with the data from the real slave.
The AHB monitor checks the bus protocol such as
which master requesting the bus and getting granted.
It also checks other AHB protocol such as the burst
type, the transfer size, and address increment size. Fig. 5 ARM7TDMI Simulation Waves
The executing flow of the SystemVerilog
simulation environment is shown in Fig.4. The first
step is to generate the configuration and connect
environment components, such as VIP master, monitor
and reference model. After reset the DUT, the
configuration will be downloaded into the DUT. Then
the VIP master, monitor, generator and reference
model will start and test begin. When the test is over,
logs will be generated and the designer can check the
reports. Fig. 6 VIP Master Simulation Waves

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The VIP Master will not simulate the same behavior. (2) Decode address; if an address is in the range of
As shown in fig 6, the VIP Master need not fetch the the Flash memory map, then the Flash reference
next command when executing an instruction, because model begin working.
all the commands have been decoder when the test (3) Read operation, the address will be stored, and
vectors were designed. The VIP Master can verify if the data store in the address will be output to
the DUT behavior confirm to the AHB protocol and compare with the response of the DUT.
execute the necessary commands. So it can be faster (4) Write operation, the address will be stored and
to verify the function feature of the DUT than the the write data will be store in.
ARM. (5) Page erase, all the page unit address will be
calculate out and the memory will be filled with
3 Design of the Reference model 16’hFFFF.
(6) Mass erase, all the memory will be filled in 16’
Rreference model that we designed is used to hFFFF.
dynamically predict the response of the DUT. As The reference model includes initiate part,
shown in fig. 1 and fig. 2, the stimulus applied to the memory address decoding part, operation checking
DUT is concurrently provided to the reference model. part, and address/data store part. The initiate part
The reference model performs all the operations on can get all the memory initiate state by the VIP master.
the stimulus to produce the form of the final response The SRAM must be written before READ operation.
and then inserts it in a data structure. Response from So which the reference model needs to do is to store
the reference model is forward to be the same as the the write address and the write data. When read
DUT’s . address is given, the reference model should give the
The reference model is also a class which includes data if the address has been written data in. Else, the
local variables and methods. It has the transaction reference model should simulate the error information
level interface. So it can get the VIP Master’s stimulus like the SRAM.
Then a report will be generating when the
by the channel to share the data contracture of the VIP
simulation is end. In the report we can debug the DUT
Master. Then the stimulus will be stored in the design. As shown in table 1, if the DUT responses
reference model and expect response will be given to difference from the reference model, it will be
verify the DUT. The comparison of the observed lightened in the report.
response with the reference model’s is performed at Table 1 Report For the Verification

the transaction level, not at the cycle-by-cycle level.

The reference model first waits for a transaction to
be generated and then waits for the monitor to notify
that this transaction occurred. In order to determine
the transaction correctness, the following rules are
applied: Each generated WRITEING transactions are
stored to a register file; each generated READING
transactions get their data field filled from the register
file, so to provide an expected result. Each transaction
is then compared on a first-come first-serve basis. Table 1 shows the results of the verification by using
In the SoC shown by the Fig.2, we want to verify reference model. The fail case is TC04-2, TC05-1,
the SRAM AHB controller and Flash AHB controller. TC06-1. These test cases are mass erase. The logs will
So the reference model should record the SRAM and give more specific reports about the error.
Flash memory behaviour.
To use the Flash, the operation contains READ, 4 Conclusions
WRITE, PAGE ERASE and MASS ERASE. The flash
memory may be initiated, so we can read the memory In this paper, we use SystemVerilog to put up a
before we write the memory. verification environment of the ARM-based SoC. The
(1) Initiate the reference model by checking all the environment can be reused easily for different design.
memory initiate state. Using VIP Master and the AHB Monitor can check the

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DUT’s protocol quickly. The reference model can be

considered as verification IP, and it can replace
time-consuming visual inspection for bus transaction
sequence verification. But using reference model
depends heavily on their availability. In this paper we
design a reference model that can be used to verify
SRAM and Flash controller. To verify other different
DUT we need to design different reference model.
How to enhance the flexible of the reference model to
verify different module needs to be discussed.
References

[1]C.Rowen. Reducing SoC simulation and development

time .Computer, 2002, 18:32-45.
[2]Rajsuman,Rajsuman. System-on-a-Chip: design and test,
Santa Clara: Advantest America R&D Center, 2000:5-27
[3]Faisal I.Haque, Khizar A.Khan, The Art of Verification with
Vera, California: 2001: 2-15
[4]ARM Ltd. AMBA Specification Rev.2.0, May
1999.http://www.arm.com
[5]Janick Bergeron, Eduard Cerny, Alan Hunter, et al.,
Verification Methodology Manual for SystemVerilog,
Synopsys Inc., 2006: 407-417
Author Biographies

Han Ke, male, born in 1980, is currently working toward the

PhD degree in the School of Electronic Engineering, Beijing
University of Posts and Telecommunications, and the major
subject is SoC technique and design of the testability(DFT) .
Deng Zhong-liang, male, born in 1965, Professor, is the dean
of in the School of Electronic Engineering, Beijing University
of Posts and Telecommunications. Currently, his research
emphasis focuses on the SoC and MEMS design
Shu Qiong, female, born in 1981, has received the MS Degree
in Electronic Engineering at the Beihang University. She is
now working on the design and verification method of SoC.

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