Exam Distributed Systems: Part 2 - Prof. R. Wattenhofer
Exam Distributed Systems: Part 2 - Prof. R. Wattenhofer
Sigg
Distributed Systems HS 09
Exam
Distributed Systems
5 February 2010, 9:00am – 12:00pm
Part 2: .................
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
8 b) (4 Points) Given a lock free consensus algorithm and two processes with different input. The root
of the execution tree...
true false
2 2 ... might be univalent.
2 2 ... must be bivalent.
2 2 ... can be critical.
2 2 ... must be critical.
8 c) (3 Points) If RMW-register x can be constructed from y and x has consensus number c...
true false
2 2 ... then y has consensus number c.
2 2 ... then y has consensus number at least c.
2 2 ... then y is non-trivial.
8 d) (4 Points) The Anderson Queue Lock (ALock)...
true false
2 2 ... is a linked list.
2 2 ... uses fetch-and-inc.
2 2 ... does not scale well.
2 2 ... is not ideal for NUMA.
8 e) (4 Points) Zyzzyva...
true false
2 2 ... optimistically executes an operation and checks replies for inconsistencies.
2 2 ... is able to handle up to f < n/3 Byzantine failures.
2 2 ... is completely decentralized and does not require a lead server.
2 2 ... outperforms PBFT (according to the numbers presented in the lectures)
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
8 f) (4 Points) Theory and practice: given a database that is replicated among n servers...
true false
2 2 It is not possible to use any algorithm based on synchronous rounds in a system
with asynchronous communication.
2 2 Assuming only crash failures, 2PC is a good choice to handle coordinated
progress.
2 2 The system may stall forever if Paxos is used for synchronization.
2 2 PBFT guarantees that all correct servers have the same content in their
databases.
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
9 a) (3 points) Old hardware often supports only RMW register like fetch-and-inc or
fetch-and-swap. Newer hardware supports rather compare-and-swap. Why?
A new hardware contains a new type of RMW-registers, so called “double RMW registers” (dRMW).
If some RMW register executes a function f (x) atomically, then its dRMW counterpart executes two
functions [f1 (x), f2 (y)] atomically on two registers. The pseudo-code below describes a generic dRMW.
1 class GenericDoubleRMW{
2 /**
3 * Atomically executes "f1" and "f2" for the registers "r1" and "r2".
4 * This method works with any two registers. The method returns the
5 * values that were stored in "r1" and "r2" before "f1" and "f2"
6 * were executed.
7 */
8 ValuePair execute( Register r1, Register r2, Function f1, Function f2 ){
9 atomic{
10 int previous1 = r1.get();
11 int previous2 = r2.get();
12 r1.set( f1.eval( previous1 ) );
13 r2.set( f2.eval( previous2 ) );
14 return new ValuePair( previous1, previous2 );
15 }
16 }
17 }
9 b) (6 points) The double-fetch-and-add register: A process can use any function of the form
fa (x) = x + a to call the dRMW. Prove your answer.
Example: calling GenericDoubleRMW.execute( x, y, f3 , f8 ) would atomically
increase the value of register x by 3 and of y by 8.
9 c) (12 points) The double-fetch-and-set register: A process can use any function of the form
fs (x) = s to call the dRMW. Sketch a proof.
Example: calling GenericDoubleRMW.execute( x, y, f4 , f7 ) would atomically
set the value of register x to 4 and of y to 7.
Hint: show that a consensus number c is between a lower and an upper bound blower ≤ c ≤ bupper . You
get full points if you show that blower = bupper , partial results give points as well.
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
10 c) (3 points) Give a concrete example where PBFT would fail without the prepare phase.
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
11 a) (10 points) List and explain (one sentence each) five synchronization patterns. Describe a different
use case for each pattern.
Study the source code that is attached to this question. It is a linked list offering a method to insert
and to remove items. The list is ordered and does not allow an item to be twice in the list.
11 c) (8 points) The current implementation has flaws and there are (at least) two scenarios where the
list gets corrupted if modified concurrently by two threads. Describe two of these scenarios, what
are the effects?
11 d) (6 points) How could the scenarios you found in b) be repaired without changing the synchroniza-
tion pattern? Write down ideas (50% of the points) and implement them (50% of the points). You
may use pseudo-code or real code.
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Prof. R. Wattenhofer, B. Sigg
Distributed Systems HS 09
1 class LinkedList{
2 // the head of the list, it can never be removed
3 Node head = new Node();
4
5 class Node{
6 int value;
7 Node next;
8 /* Only one thread can ’acquire’ the lock at a a time.
9 * Threads need to ’release’ the lock to free it. */
10 Lock lock = new Lock();
11 }
12
13 // insert ’x’, but only if not already in this list
14 void insert( int x ){
15 Node node = findPredecessor( x );
16 if( node.next == null || node.next.value != x ){
17 Node insert = new Node();
18 insert.value = x;
19 insert.next = node.next;
20 node.next = insert;
21 }
22 node.lock.release();
23 }
24
25 // remove ’x’ from this list
26 void remove( int x ){
27 Node node = findPredecessor( x );
28 Node next = node.next;
29 if( (next != null) && (next.value == x) ){
30 node.next = next.next;
31 }
32 node.lock.release();
33 }
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