Date: Page No:

Experiment No:

Design of Basic Current Mirror

Aim: Design and analysis of Simple current mirror with the given specifications of Iin=100uA,
Iout=Iin & Vmin=0.46v in 180nm technology.

Tool: Cadence ICFB.

Description: A current mirror is a circuit designed to copy a current through one active device
by controlling the current in another active device of a circuit, keeping the output current
constant regardless of loading. The current being 'copied' can be, and sometimes is, a varying
signal current. Conceptually, an ideal current mirror is simply an ideal current amplifier. The
current mirror is used to provide bias currents and active loads to circuits.

Design: we are using the following design parameters

Kn = μn.Cox=170µA/V2 given by technology, Vdd = 1.8V & L= 180nm

Vmin = Vgs-Vth = 0.46v

=> 100μA=(170μ(W/0.18)(0.46)2 )/2

=> W= 1μm.

Schematic:
Date: Page No:
Experiment No:

Layout:

Extracted Layout with parasitic RC:

Date: Page No:
Experiment No:

Test Bench:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
3 nets
3 terminals
2 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
3 nets
3 terminals
2 nmos

Terminal correspondence points

N1 N3 Iin
N2 N2 Iout
N0 N0 gnd!

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match.

Date: Page No:
Experiment No:

Simulation Waveforms:

Schematic:

Extracted:
Date: Page No:
Experiment No:

Observations:

 By Replacing all nmos’s with pmos’s then the CM action will not be affected.

 By increasing the overdrive voltage the Drain current will be increased.

 Overdrive voltage is reduced by decreasing the Gate to Source voltage (Vgs).

 By increasing the value of W1 to 2W2, the o/p will not follow the input it will become
half of the input current.

 The output resistance is 144Kohms.

 The o/p voltage swing is Vmin to (Vdd-Vmin) , i.e., 0.46v to 1.34v,where Vmin=Vgs-Vt.

 The current Mirror is not acting like a true current mirror we can make it a true current
copier by cascoding one more stage.

 The current mirror/current copying is mainly dependent on Widths of the two transistors.

 The nmos’s are replaced with pmos’s for high output impedances.

 The gain is effected when nmos transistors are replaced with pmos transistors because
μp<μn.

 The o/p resistance/Impedance is affected when nmos are replaced with pmos because
mobility of holes/electrons is inversely proportional to Rds.

Conclusion: Designed and analyzed the Simple current mirror with the given specifications of
Iin=100uA, Iout=Iin & Vmin=0.46v in 180nm technology.
Date: Page No:
Experiment No:

Design of Cascode Current Mirror

Aim: Design and analysis of Cascode Current mirror with the given specifications of Iin=40uA,
& Iout=Iin in 180nm technology.

Tool: Cadence ICFB.

Description: In previous sections we considered the subject of current sources and sinks where
the objective was to implement the ideal I-V characteristics at that place we prefer dc voltage
source was used to bias the implementation of sources and sinks. Mirror also similar to sink it
uses the matched principle this is looking like a mirror that is called current mirror.

One of the advantage over mos mirror compare to BJT mirror is here there is no early
effects. Here the output resistance is increased compared to simple current mirror. Cascode is
cascade of common source and common gate stage. Here transistors M3 and M4 keep the values
of Vds1 and Vds2 nearly equal, effectively removing the influence of the channel modulation
effect. The mismatch effects are neglected the current gain of the mos cascade mirror is given as

Iout /Iin = (W2/L2) / (W1/L1)

Output resistance of cascode mirror is

Rout= rds2 + r ds4+ rds2 rds4 gm4 (1 + gmb4/gm4)

After proper approximations rout = gm ro2 where ro =1/» Iout.

It provides the current reflection from a given current source.

It reduces the use of the number of current sources in the circuit.

Design: we are using the following design parameters

Kn = 170µA/V2 given by technology, Vdd = 1.8V & L=180nm

Vmin = Vdsat + (Vt + Vdsat)

= 2Vdsat + vt

Vmin= 0.76v= {0.14 + (0.48+0.14)}

(W/L)2=(W/L)4=2*Id/(Kn*(vgs2-vth2)2)

 W/L= (2*40)/(170*0.46*0.46)
 W=L*(80/35.97)
 W=400nm.
Date: Page No:
Experiment No:

Schematic:

Layout:
Date: Page No:
Experiment No:

Extracted Layout with parasitic RC:

Test Bench:
Date: Page No:
Experiment No:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
5 nets
3 terminals
4 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
5 nets
3 terminals
4 nmos

Terminal correspondence points

N1 N2 Iin
N4 N5 Iout
N2 N0 gnd!

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match logically but have mismatched parameters.

Simulation Waveforms:

Schematic:
Date: Page No:
Experiment No:

Extracted:

Observations:

 If the overdrive voltage of the two base transistors is increased the output voltage swing
will decrease.
 The voltage swing of the circuit is Vmin to (Vdd-Vmin) i.e., 0.76v to 1.04v, where
Vmin=Vt+2Vdsat.
 A method to improve the voltage swing is by using separate Iref (Iin) for both MN2 &
MN3 in the above diagram or using a self biased cascode, so that Vmin will become 2Vdsat.
 This current mirror truly acts as a current copier.
 The output resistance of the current mirror is172.37Kohms. A method to improve the
output resistance is choosing a Wilson current mirror.
 The effect of channel length modulation on the current copier is by considering
Iout/Iin= (1+ λvds2)/ (1+ λvds1)
In that we assumes λ value same for both transistors, but the differences in drain to
source voltages in the transistor can cause a deviation from the ideal unity current gain.

Conclusion: Designed and analyzed the Cascode current mirror with the given specifications
of Iin=40uA & Iout=Iin in 180nm technology.
Date: Page No:
Experiment No:

Design of Wilson Current Mirror

Aim: Design and analysis of Wilson Current mirror with the given specifications of Iin=40uA,
Iout=30uA & Vmin=0.76v in 180nm technology.

Tool: Cadence ICFB.

Description:

The salient features of the Wilson current mirror are:

1. Vmin represents a large portion of the Vout.
2. Curves (Id vs. Vds) are much flatter than the simple MOS current mirror indicating an
increase in the output resistance value.
3. Linearity of the circuit is not good for higher values of currents. This nonlinearity is due to the
fact that Vds=Vds1-Vds2 is large for current levels. So the ratio of currents is given by

Iout/Iin= (1+ λvds2)/ (1+ λvds1)

As Vds2<Vds1, so Iout<Iin due to channel length modulation.

To remove this nonlinearity, a fourth drain gate connected device is connected in series with M1,
between drain of M1 and gate of M3.
4. Vmin of the Wilson mirror is given by Vmin= VGS+VDS sat
5. The output resistance of the circuit is given by
Rout ≈ gm* Ro2/2

Design:

We are using the following design parameters

Iin = 40µA, Iout = 30µA, Vmin = 0.76V

The minimum output voltage Vout = 0.76V is assumed to be distributed for transistors M2 and
M3 as Vds2=0.62v and Vds3=0.14v

 (W/L)i=2*Id/(Kn*(vgs-vth)2)
 (W/L)=4.32µm/0.18µm
Date: Page No:
Experiment No:

Schematic:

Layout:
Date: Page No:
Experiment No:

Extracted Layout with parasitic RC:

Test Bench:
Date: Page No:
Experiment No:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
5 nets
3 terminals
4 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
5 nets
3 terminals
4 nmos

Terminal correspondence points

N1 N4 Iin
N4 N3 Iout
N2 N0 gnd!

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match logically but have mismatched parameters.

Simulation Waveforms:
Schematic:
Date: Page No:
Experiment No:

Extracted:

Observations:

 The voltage swing of the circuit is Vmin to (Vdd-Vmin) i.e., 0.76v to 1.04v, where
Vmin= Vgs+Vdsat.

 The output resistance is 2.892Mohms.

 The problem associated with the circuit is having different Vds values for the transistors
that cause short channel effect on Ids. To make the linearity in Ids & Vds curve include
one more transistor in series with M1, between drain of M1 and gate of M3.

 The performance comparison of Wilson current mirror and cascode current mirror with
respective to
Voltage swing is less for Wilson Current mirror,
Output resistance is more for Wilson current mirror,
Current mirroring is good in Cascode current mirror.

Conclusion: Designed and analyzed the Wilson current mirror with the given specifications of
Iin=40uA, Iout=30uA & Vmin =0.76v in 180nm technology.
Date: Page No:
Experiment No:

Design of Widlar Current Mirror

Aim: Design and analysis of Widlar Current mirror with the given specifications of Iin=50uA,
Iout=Iin & Vmin=0.76v in 180nm technology.

Tool: Cadence ICFB.

Description:

In Many cases the mirrored currents are not unity ,the circuit will become less accurate
due to decrease in relative accuracy of large ratios caused by unequal mirror currents can be
avoided by using a resistor in series with the source of lower current transistor .

This mirror is called wilder current mirror and can have large current differences with
identical transistor areas.

Writing KVL equation in the loop comprising M1, M2 transistors

We have Vgs1-Vgs2=Id*R

Designed the Current mirror by considering R=600Ohms & W=430nm.

Schematic:
Date: Page No:
Experiment No:

Layout:

Extracted Layout with parasitic RC:

Date: Page No:
Experiment No:

Test Bench:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
4 nets
3 terminals
1 nplusres
2 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
4 nets
3 terminals
1 nplusres
2 nmos

Terminal correspondence points

N1 N1 Iin
N3 N4 Iout
N0 N0 gnd!

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match logically but have mismatched parameters.

Date: Page No:
Experiment No:

Simulation Waveforms:

Schematic:

Extracted:

Conclusion: Designed and analyzed the Widlar current mirror with the given specifications of
Iin=50uA, Iout=Iin & Vmin =0.76v in 180nm technology.
Date: Page No:
Experiment No:

Design of Basic Current Sink

Aim: Design and analysis of Basic Current Sink with the given specifications of I=100uA,
Vmin=0.5v in 180nm technology.

Tool: Cadence ICFB.

Description:

An ideal current source is a two terminal element whose current is constant for any
voltage across the source. Most current source application require one of their terminals to be
common with the most positive or the most negative d.c voltage in the circuit. In current sink one
of the terminals (negative terminal) is connected to most negative d.c voltage. The two major
aspects by which a current source /sink is characterized are Vmin and Ro.

Id =1/(lambda * Id)

Vmin=Vgs- VTH

Design:

 From given value of Vmin specifications we get the value of Vgs

 Using the value of Vgs we can calculate the value of (W/L).
 Using Id calculate the value of Ro

VMIN =Vsat =0.5V

Vgs - Vth = 0.5V

Vgs = Vgg

Vgs = Vsat + Vth = 0.5+0.48 = 0.98v

Id =100 µA

Id = Kn/2* (W/L) *(Vgs-Vth) 2

W/L = 2*Id/Kn(Vgs-Vth) 2

W/L = 4.705

L = 0.18um, W=0.847um

Ro=1/(lambda * Id)=1/(.06*100u)=166Kohms.
Date: Page No:
Experiment No:

Schematic:

Layout:
Date: Page No:
Experiment No:

Extracted Layout with parasitic RC:

Test Bench:
Date: Page No:
Experiment No:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
3 nets
3 terminals
1 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
3 nets
3 terminals
1 nmos

Terminal correspondence points

N0 N0 gnd!
N2 N1 vin
N1 N3 vout

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match logically but have mismatched parameters.

Simulation Waveforms:

Schematic:
Date: Page No:
Experiment No:

Extracted:

Observation:

Theoretical values:

Vmin=0.5v

Ro=166Kohms

Id=100uA.

Practical values:

Ro=65.8Kohms

Vmin=0.542v

Id=168.4uA.

The exact current at Vmin is less than the saturation value. To increase this value to saturation
designed for, we have to increase the (W/L) ratio of the transistor or increase the offset gate to
source voltage.

Conclusion: Designed and analyzed the Basic current sink with the given specifications of
Iin=100uA & Vmin =0.5v in 180nm technology.
Date: Page No:
Experiment No:

Design of Cascode Current Sink

Aim: Design and analysis of Cascode Current Sink with the given specifications of Io=50uA,
Vmin=1.5v in 180nm technology.

Tool: Cadence ICFB.

Description: In most current source/sink realizations, the I-V characteristics of ideal current
source are only approximated over a limited range of the voltage V. Also the current is rarely
bidirectional. The resulting I-V characteristics of a practical current source/sink there is a
minimum voltage Vmin, below which the current source/sink will not be good approximation to
Io. Further even in the region where the current source/sink is a reasonably good approximation
to Io, the actual source/sink deviates by a resistance Ro, which represents the parallel resistance
of the current source/sink and ideally is infinite.

Thus, the two major aspects by which a current source/sink is characterized are Vmin and
Ro. In case of basic current sink the Ro is small. By cascoding current sink the output resistance
Ro is increased but at the same time minimum voltage Vmin is also increases

Design:

Vmin = 0.7v, Id = 100uA, Vt1 = 0.48v, Let us assume Vmin1 = 0.3v, Vmin2 = 0.4v

Vmin1 = Vgg1 – Vt1

=> Vgg1 = Vmin1 + Vt1 => Vgg1 = 0.78v

Vmin2 = Vgg2 – Vt2 - Vs2

=> Vgg2 = Vmin2 + Vt1 + Vs2 => Vgg2 = 0.88v

Id = Kn/2* (W/L)1 *(Vmin1) 2

(W/L)1 = 2*Id/Kn(Vmin1) 2 = 2*100*10-6/(170*10-6*(0.3)2)

W1=2.35um, L1=0.18um

Id = Kn/2* (W/L)2 *(Vmin2) 2

(W/L)2 = 2*Id/Kn(Vmin2) 2 = 2*100*10-6/(170*10-6*(0.4)2)

W2=1.323um, L2=0.18um
Date: Page No:
Experiment No:

Schematic:

Layout:
Date: Page No:
Experiment No:

Extracted Layout with parasitic RC:

Test Bench:
Date: Page No:
Experiment No:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
5 nets
4 terminals
2 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
5 nets
4 terminals
2 nmos

Terminal correspondence points

N1 N0 gnd!
N0 N5 vin1
N4 N2 vin2
N3 N3 vout

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
pmos nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match logically but have mismatched parameters.

Simulation Waveforms:
Schematic:
Date: Page No:
Experiment No:

Extracted:

Observation:

From Practical

Vmin=0.702V

Rout=154.12Kohms

Io=87.76µA.

When compared to basic current sink output resistance Rout is increased but at the same
time VMIN value also increases. From theoretical and practical values are deviations occur due
to channel length modulation

Conclusion: Designed and analyzed the Cascode current sink with the given specifications of
Iin=50uA & Vmin =1.5v in 180nm technology.
Date: Page No:
Experiment No:

Design of Active Load CMOS Inverter Amplifier

Aim: Design and analysis of Active Load CMOS Inverter Amplifier with the given
specifications, maximizing the gain in 180nm technology.

Tool: Cadence ICFB.

Description: A low-gain inverting stage is desired that has highly predictable small and large
signal characteristics. One configuration that meets this need is the active PMOS load inverter
(simply uses the term”active load inverter”).This type of inverting amplifier has limited output
voltage range and low gain.

Large-signal swing limitations of the active-resistor load inverter is

Date: Page No:
Experiment No:

Schematic:

Layout Extracted Layout with parasitic RC

Date: Page No:
Experiment No:

Test Bench:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
4 nets
4 terminals
1 pmos
1 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
4 nets
4 terminals
1 pmos
1 nmos

Terminal correspondence points

N2 N1 gnd!
N1 N0 vdd!
N3 N2 vin
N0 N3 vout

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match.

Date: Page No:
Experiment No:

Waveforms:

Schematic:

Extracted:
Date: Page No:
Experiment No:

Observations:

 Maximum Gain is 12.57db at Wp = 600nm, Wn = 3μm.

 The 3db frequency or Bandwidth is 5.23G Hz.
 Phase Margin is 180o.
 The gain is varied by changing the frequency after 1GHz.
 The Gain at 1GHZ is 12.42db.
 The theoretical Gain is 20 log (-4.85) i.e., 13.7db.
 By Changing the value of L=350nm gain is 15.71db, L=500nm gain is 16.52db and
L=1um the gain is 22.31db.
 Gain is negative for Active Load CMOS Inverter Amplifier, Av = - gm1/gm2.
 The trade-off we have to make when gain has to be maximized is widths of Transistors
with respect to the technology.
 The signal swings between Vout (max) & Vout (min)
 Vout (max) = VDD- |Vtp| = 1.8-0.46=1.34v,
 Vout (min) = VDD-Vt-(VDD-VSS-Vt) / (1+ β2/ β1) = 0.008v.
 The limitation of the circuit is having the Low output Resistance.
 By applying 20mv, 100mv & 200mv inputs, all the gains at all these input voltages are
same.

Conclusion: Designed and analyzed the Active Load CMOS Inverter Amplifier with the given
specifications, maximized the gain in 180nm technology.
Date: Page No:
Experiment No:

Design of Current - Source CMOS Inverter Amplifier

Aim: Design and analysis of Current - source CMOS Inverter Amplifier with the given
specifications, maximizing the gain in 180nm technology.

Tool: Cadence ICFB.

Description: Often an inverting amplifier is required that has gain higher than that achievable
by active load inverting amplifier. A second inverting amplifier configuration, which has higher
gain, is the current-source inverter. Instead of a PMOS diode as the load, a current source load is
used. The current source is a common-gate configuration using a p-channel transistor with the
gate connected to a dc bias voltage.

The maximum positive output voltage is

The minimum output voltage is

Schematic:
Date: Page No:
Experiment No:

Layout:

Extracted Layout with parasitic RC:

Date: Page No:
Experiment No:

Test Bench:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
5 nets
5 terminals
1 pmos
1 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
5 nets
5 terminals
1 pmos
1 nmos

Terminal correspondence points

N1 N1 gnd!
N0 N5 vb
N3 N0 vdd!
N4 N2 vin
N2 N4 vout

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match.

Date: Page No:
Experiment No:

Simulation Waveforms:

Schematic:

Extracted:
Date: Page No:
Experiment No:

Observations:

 Maximum Gain is 25.46db at Wp = 600nm & Wn = 1μm.

 The 3db frequency or Bandwidth is 1.24GHz.
 Phase Margin is 180o.
 Gain is varied by changing the frequency after 200MHz.
 The Gain at 1GHZ is 23.27db.
 By Changing the value of L=350nm the gain is 32.11db.
 Gain is negative for Current Source CMOS Inverter Amplifier, Av = -gm1/(gds1+gds2).
 When gain has to be maximized we need to change the width of the NMOS transistor,
which is more effective.
 The signal swings between Vout(max) and Vout(min),where
Vout (max) ≈ Vdd = 1.8v.
Vout (min) = (Vdd-Vt1){1-[1-(β2/β1)((Vsg2- |Vt2|)/(Vdd-Vt1))2] ½}
 The limitation of the circuit is working at lower bandwidths due to High output
impedance.
 By applying 20mv, 100mv & 200mv inputs, all the gains at all these input voltages are
same.

Conclusion: Designed and analyzed the Current Source CMOS Inverter Amplifier with the
given specifications, maximized the gain in 180nm technology.
Date: Page No:
Experiment No:

Design of Current - Source Amplifier

Aim: Design and analysis of Current - source Amplifier with the given specifications,
maximizing gain in 180nm technology.

Tool: Cadence ICFB.

Description:

A common use of simple current mirrors is in a single – stage amplifier with an active
load, as shown in schematic. This common-source topology is the most popular gain stage,
especially when high-input impedance is desired.

Here, an n-channel common-source amplifier has a p-channel current mirror used as an

active load to supply the bias current for the drive transistor. By using an active load, a high
impedance output load can be realized without using excessively large resistors or a large power-
supply voltage. As a result, for a given power-supply voltage, a larger voltage gain can be
achieved using an active load than would be possible if a resistor were used for the load.

Using small-signal analysis,Vgs1 = Vin

Av = Vout /Vin = -(gm1R2) = -gm1(rds1|| rds2)

Depending on the device sizes, currents, and the technology used, a typical gain for this
circuit is in the range of -10 to -100.

To achieve similar gains with resistive loads, much larger power-supply voltages more than 5v
must be used. This resistive load approach also greatly increases the power dissipation.

It should be mentioned here that for low-gain, high-frequency stages, it may be desirable
to use resistors loads, because they often have less parasitic capacitances associated with them.
They are also typically less noisy than active loads.

Applied 20mv of Vin to find the gain.

Date: Page No:
Experiment No:

Schematic:

Layout:
Date: Page No:
Experiment No:

Extracted Layout with parasitic RC:

Test Bench:
Date: Page No:
Experiment No:

Results:

LVS Report:
GENERIC PDK LVS Rules

Net-list summary for /home/vlsi/icfb_gpdk/LVS/layout/netlist

count
5 nets
5 terminals
2 pmos
1 nmos

Net-list summary for /home/vlsi/icfb_gpdk/LVS/schematic/netlist

count
5 nets
5 terminals
2 pmos
1 nmos

Terminal correspondence points

N4 N5 a
N1 N0 gnd!
N2 N4 out
N0 N3 vb
N3 N1 vdd!

Devices in the netlist but not in the rules:

pcapacitor presistor
Devices in the rules but not in the netlist:
nplusres polyres nmoscap mimcap vpnp npn pnp inductor ndio pdio

The net-lists match.

Simulation Waveforms:
Schematic:
Date: Page No:
Experiment No:

Extracted:

Observations:

 Maximum Gain is 27.29db at Wp = 2μm. & Wn = 3.6μm.

 The 3db frequency or Bandwidth is 920MHz.
 Phase Margin is 180o.
 Gain is varied by changing the frequency after 100MHz.
 The Gain at 1GHZ is 24.03db.
 By Changing the value of L=350nm the gain is 35.48db.
 Gain is negative for Current Source Amplifier, Av = -gm1(rds1|| rds2).
 When gain has to be maximized we need to change the width of the NMOS transistor,
which is more effective.
 The limitation of the circuit is working at lower bandwidths due to High output
impedance.
 By applying 20mv, 100mv & 200mv inputs, all the gains at all these input voltages are
same.

Conclusion: Designed and analyzed the Current Source Amplifier with the given
specifications, maximized the gain in 180nm technology.
Date: Page No:
Experiment No:

Design of Sample and Hold circuit

Aim: Design of Sample and hold Circuit with Verilog- A Program and simulating program for
Functional Verification.

Tool: Cadence ICFB.

Verilog – A Program:

1. `include "constants.vams"
2. `include "disciplines.vams"
3. module sh(in,out,smpl);
4. output out;
5. input in,smpl;
6. electrical in,out,smpl;
7. real state;
8. analog
9. begin
10. @(cross(V(smpl)-2.5,+1))
11. state=V(in);
12. V(out) <+ transition (state,0,0,0);
13. end
14. endmodule

Description:

Line 1,2: `include "disciplines.vams",`include "disciplines.vams"

This line includes the definitions for electrical nodes, among other things, and should be the first
line of most Verilog-A files. Note the use of the ` symbol. It is not a normal apostrophe (').On
most keyboards it is located on the upper left key, the same key as the tilde (~).
Line 3: module sh(in,out,smpl);
Declares the start of a module named sh with three external terminals, in,smpl and out. These
terminals are used in order by GENESYS, so in becomes pin 1 and smpl becomes pin 2 and out
becomes pin3 in the symbol.
Line 4: output out;
Declares that these ports are output ports.
Date: Page No:
Experiment No:

Line 5: input in,smpl;

Declares that these ports are input ports.
Line 6: electrical in,out,smpl;
Declares that these nodes are electrical. If internal nodes are needed, they should be added to this
line.
Line 7: real state;
state is an intermediate signal declared of type real
Line 8: analog
Header for the analog equations. Required in all files.
Line 9: begin
Starts the actual analog equations. Often, this is combined with "analog" on one line: "analog
begin".
Line 10: @(cross(V(in),+1))
Cross function specifies which crossings generate a cross event.
If you want to Detect only zero crossings where the value is increasing then Set direction equal
to +1
Line 11: state=V(smpl);
From above condition voltage of smpl is stored at state
Line12: V(out) <+ transition (state,0,0);
The transition filter, transition(), is used to smooth out piecewise constant waveforms. The
transition filter should be used for transitions and delays on digital signals as it provides
controlled transitions between discrete signal levels.
state=> V(smpl)
0=> delay time (if needed specify delay time)
0=> rise time (if needed specify rise time)
0=> fall time (if needed specify fall time)
Line 13: end
Ends the analog equations started at line 8.
Line 14: endmodule
Ends the sh module started at line 3.
Date: Page No:
Experiment No:

Test Bench:

Simulation Waveform:

Conclusion: Designed Sample and hold Circuit with Verilog- A Program and Functionally
verified the program by simulating.
Date: Page No:
Experiment No:

Design of Low Pass Filter

Aim: Design of Low Pass Filter with Verilog- A Program and Functional Verification with
Simulation.

Tool: Cadence ICFB.

Verilog – A Program:

`include "constants.vams"
`include "disciplines.vams"
module lpf(vin,vout);
input vin;
output vout;
electrical vin,vout;
parameter real bw = 100M;
real r, c, wc;
analog begin
@(initial_step("tran","ac","dc"))
begin
r = 1k;
wc = 2 * 3.14 * bw;
c = 1 / (r * wc);
end
V(vout,vin) <+ I(vout, vin) * r;
I(vout) <+ ddt(V(vout) * c);
end
endmodule
Date: Page No:
Experiment No:

Test Bench:

Simulation Waveform:

Conclusion: Designed Low Pass Filter with Verilog- A Program and Functionally verified the
program by simulating.