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I S P D: 2016 Nternational Ymposium On Hysical Esign

The 2016 International Symposium on Physical Design provides a forum for exchanging ideas on VLSI and other advanced technology system layout design. It includes sessions on topics like 3D circuits, directed self-assembly, timing and clock optimization, reliability, FPGAs, and statistical learning methods. A special session commemorates the contributions of Prof. Ralph Otten to physical design flows. The 3-day event in Santa Rosa, California features keynote speeches and over 30 presentations.

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74 views2 pages

I S P D: 2016 Nternational Ymposium On Hysical Esign

The 2016 International Symposium on Physical Design provides a forum for exchanging ideas on VLSI and other advanced technology system layout design. It includes sessions on topics like 3D circuits, directed self-assembly, timing and clock optimization, reliability, FPGAs, and statistical learning methods. A special session commemorates the contributions of Prof. Ralph Otten to physical design flows. The 3-day event in Santa Rosa, California features keynote speeches and over 30 presentations.

Uploaded by

Usama Javed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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2016 International Symposium on Physical Design

With a Tribute to Prof. Ralph Otten


Santa Rosa, California, April 3-6, 2016
www.ispd.cc

PROGRAM
The International Symposium on Physical Design 2:00 – 3:30 pm Session 2: Directed Self Assembly
provides a high-quality forum for the exchange of ideas on
the physical layout design of VLSI, biological or other Session Chair: Dwight Hill (Synopsys)
advanced technology systems. The scope of this
symposium includes all aspects of physical design, from (Invited) “Cell-Based Design Methods for Directed Self-
high-level interactions with logic synthesis, down to back- Assembly”, Karl Berggren, Caroline A. Ross, Hyung Wan Do,
end performance optimization and design for Jae-Byum Chang, Hong Kyoon Choi (MIT)
manufacturing.
“Concurrent Guiding Template Assignment and
Regular presentations are 30 minutes. Redundant Via Insertion for DSA-MP Hybrid
Lithography”, Jiaojiao Ou, Bei Yu and David Z. Pan.
SUNDAY, April 3
5:30 – 7:00 pm: Reception “Double-Patterning Aware DSA Template Guided Cut
Redistribution for Advanced 1-D Gridded Designs”,
Zhi-Wen Lin and Yao-Wen Chang.
MONDAY, April 4
8:45 – 10:00 am: Welcome and Keynote Address 3:30 – 4:00 pm: Afternoon Break
Host: Evangeline Young (Chinese University of Hong
Kong) 4:00 – 5:30 pm Session 3: Special Session
Monday Keynote: “Circuit Design in Nano-Scale CMOS
Technologies”, Kevin Zhang (Intel) Session Chair: Mahesh A. Iyer (Intel Corporation)

10:00 – 10:30 am: Morning Break (Invited) “Technology Inflection Points”, Victor Moroz
(Synopsys)
10:30 am - 12:30 pm Session 1: 3D Circuits
(Invited) “Challenges and Opportunities with Place and
Session Chair: David Chinnery (Mentor Graphics) Route of Modern FPGA Designs”, Raymond Nijssen
(Invited) “Physical Design Automation for 3D Chip (Achronix)
Stacks -- Challenges and Solutions”, Johann Knechtel
(Masdar Institute of Science and Technology), Jens Lienig (Dresden (Invited) “Design and Tool Flow of IBM's TrueNorth:
University of Technology) An Ultra-Low Power Programmable Neurosynaptic Chip
with 1 Million Neurons”, Filipp Akopyan (IBM)
“ePlace-3D: Electrostatics based Placement for 3D-ICs”,
Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen and 6:15 – 8:00 pm: Dinner Banquet
Chung-Kuan Cheng.
“A Compressive-sensing based Testing Vehicle for 3D
TSV Pre-bond and Post-bond Testing Data”, Hantao TUESDAY, April 5
Huang, Hao Yu, Cheng Zhuo and Fengbo Ren.
9:00 – 10:00 am: Tuesday Keynote Address
“PLATON: A Force-Directed Placement Algorithm for
3D Optical Networks-on-Chip”, Anja von Beuningen and Host: Yao-Wen Chang (National Taiwan University)
Ulf Schlichtmann.
Tuesday Keynote: “Some Observations on the Physical
12:30 – 2:00 pm: Lunch Design of the Next Decade”, Antun Domic (Synopsys)
Host: Qi Zhu (University of California, Riverside)
10:00 – 10:30 am: Morning Break
(Invited) “Optimizing for Power, Speed, Cost and
Emissions in Automotive Drivetrains”, Patrick Groeneveld
(Synopsys)
10:30 am – 12:30 pm Session 4: Timing and Clock WEDNESDAY, April 6
Optimization
Session Chair: Gustavo Wilke (Synopsys) 8:30 – 10:10 am Session 7: FPGA Physical Design

(Invited) “A Designer’s Perspective on Timing Closure”, Session Chair: Sabya Das (Xilinx)
Greg Ford (Global Foundries) (Invited) “An Interactive Physical Synthesis Methodology
“Cell Selection for High-Performance Designs in an for High-frequency FPGA Designs”, Sabya Das, Rajat
Industrial Design Flow”, Tiago J. Reimann, Cliff C. N. Sze Aggarwal, Zhiyong Wang (Xilinx)
and Ricardo Reis. (Invited) “Power Optimization of FPGA Interconnect
“Drive Strength Aware Cell Movement Techniques for Via Circuit and CAD Techniques”, Safeen Huda and Jason
Timing Driven Placement”, Guilherme Flach, Mateus Anderson (Univ. of Toronto)
Fogaça, Jucemar Monteiro, Marcelo Johann and Ricardo Reis. (Invited) “Scaling Up Physical Design: Challenges and
“Construction of Latency-Bounded Clock Trees”, Rickard Opportunities”, Guojie Luo, Wentai Zhang, Jiaxi Zhang
Ewetz, Chuan Yean Tan, and Cheng-Kok Koh. (Peking Univ.), Jason Cong (UCLA)
(Invited) “Routability-Driven FPGA Placement
12:30 – 2:00 pm: Lunch Contest”, Stephen Yang, Aman Gayasen, Chandra Mulpuri,
2:00 – 3:30 pm Session 5: PD for Reliability and Sainath Reddy, Rajat Aggarwal (Xilinx)
Adaptability
Session Chair: Shuai Li (Cadence) 10:10 – 10:30 am: Morning Break

(Invited) “Scaling Beyond 7nm: Design-Technology Co-


optimization at the Rescue”, Julien Ryckaert (IMEC) 10:30 am – 12:00 pm Session 8: Statistical and
Machine Learning-Based CAD
“Proximity Optimization for Adaptive Circuit Design”,
Session Chair: Jackey Yan (Cadence)
Ang Lu, Hao He and Jiang Hu.
“Generating Routing-Driven Power Distribution
“Load-Aware Redundant Via Insertion for
Networks with Machine-Learning Technique”, Wen-
Electromigration Avoidance”, Steve Bigalke and Jens Lienig.
Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu,
Mango C.-T. Chao, Cheng-Hong Tsai, Yen-Chih Chiu.
3:30 – 4:00 pm: Afternoon Break
“Hyperspherical Clustering and Sampling for Rare Event
4:00 – 6:00 pm Session 6: Commemoration for Prof.
Analysis with Multiple Failure Region Coverage”, Wei
Ralph Otten
Wu, Srinivas Bodapati and Lei He.
Session Chair: Michael Burstein (MediaBoost)
“A Machine Learning Based Framework for Sub-
(Invited) “The Early Days of Automatic Floorplan Resolution Assist Feature Generation”, Xiaoqing Xu,
Design”, Martin Wong (UIUC) Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama,
Toshiya Kotani and David Pan.
(Invited) “The Annealing Algorithm Revisited”, Lukas
van Ginneken (DigiPen Institute of Technology)
12:00 pm – 12:10 pm: Closing Remarks
(Invited) “Trailblazing Physical Design Flows: Ralph
Otten’s Impact on Design Automation”, Patrick
12:10 – 1:30 pm: Lunch
Groeneveld (Synopsys)
(Invited) “Complexity and Diversity in IC Layout 1:30 – 5:30 pm: Social Activity
Design”, Ralph Otten (Technische Universiteit Eindhoven)

6:15 – 8:30 pm: Dinner Banquet

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