17 Virtual Memory
17 Virtual Memory
CPSC 457
Virtual Memory
Fall 2017
Contains slides from Mea Wang, Andrew Tanenbaum and Herbert Bos, Silberschatz, Galvin and Gagne
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CPSC 457
Virtual memory
physical
memory
(RAM)
process's
● virtual memory is a memory management technique virtual
memory
○ allows the OS to present a process with logical
address space that appears contiguous
another
○ while physical address space can be process
discontiguous
○ and some parts of logical address space can be
mapped to a backing store
● improves memory management
● allows parts of programs to be 'swapped' in/out
DISK
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Paging
● paging is the most common implementation of physical
memory
virtual memory (RAM)
(ptr in PCB)
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Paging
● if a program tries to address a page that does not map to physical memory
○ CPU issues a trap ― called page fault
○ OS suspends the process
○ OS locates the missing page on disk
□ what happens if not on disk? → invalid page fault
results in a crash, segmentation fault, core dump ...
○ OS loads the missing page from disk
○ OS updates the page table
○ OS resumes the process
● if OS only loads pages as a result of page fault, we call that demand paging
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Paging
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Paging
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Paging example
● virtual address space = 64KB
● physical address space = 32KB
● page size = 4KB
● calculate:
○ frame size = ?
○ # of pages = ?
○ # of frames = ?
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CPSC 457
Paging example
● virtual address space = 64KB
● physical address space = 32KB
● page size = 4KB
● calculate:
○ frame size = 4KB (same as page size)
○ # of pages = 16 (64KB / 4KB)
○ # of frames = 8 (32KB / 4KB)
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Paging example
● Assume page size = 2KB, and a process needs 71 KB to load. How many pages do we need?
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Paging example
● Assume page size = 2KB, and a process needs 71 KB to load. How many pages do we need?
● Observations:
m-bit logical address space (2m), and n-bit page size (2n)
p = page number
d = page offset
f = frame number
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Paging Model of Logical and Physical Memory
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Paging Model of Logical and Physical Memory
0:
4: i
0: a j
k
1: b l
2: c 8: m
n
3: d o
4: e p
0: 5 12:
5: f 1: 6
logical address physical
6: g 2: 1
space memory
7: h 3: 2 16:
8: i
4 bytes per 9: j
10: k page table 20: a
page
b
11: l c
12: m d
24: e
13: n f
14: o g
h
15: p 28:
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Free frames
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TLB as associative memory
● TLB is often implemented as associative memory
○ hardware capable of fast parallel search based on content
● given a "Page #", TLB will return corresponding "Frame #" in constant amount of time
● but TLB only stores a subset of the page table
● if TLB does not contain entry for "page #", it must be obtained from page table in memory
○ TLB-hit vs TLB-miss
● effective memory-access time = (1-p) * (tlbs + 2 * ma) + p * (tlbs + ma)
p = probability of TLB-hit (TLB-hit ratio), tlbs = TLB search time 19
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Paging hardware with TLB
● memory protection is usually implemented by associating a protection bit with each frame
○ the bit indicates if read-only or read-write access is allowed
○ note: we can can also add other protection bits (execute only, etc)
● valid bit ― another bit in each page table entry:
○ valid=1 indicates that the corresponding frame is in physical memory
○ valid=0 (“invalid”) the corresponding frame is not in physical memory
○ alternative: use page-table length register (PTLR) to indicate which pages not in RAM
● any violations result in a trap to the kernel, eg.:
○ accessing page with invalid bit set → page fault
○ accessing page past the PTLR → page fault
○ trying to write to a page with read-only bit set → general protection fault
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Typical structure of page table entry
aka dirty bit
set by hardware
automatically on
aka valid/invalid bit
write access
invalid → page fault
set by hardware
various bits, eg.
automatically on
read/write/execute
any access
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Structure of the Page Table
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Summary
● address space, logical/virtual, physical
● MMU, base & limit registers
● address binding - compile- / load- / execution-time
● swapping
● free memory management
○ fixed/dynamic partitioning
○ bitmaps, linked lists
○ placement algorithms: first fit, best fit, worst fit, next fit, quick fit
● virtual memory
○ pages, frames, demand paging, page table, page fault, effective access time
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Questions?
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