Introduction To Computer Science-1
Introduction To Computer Science-1
CSCI 109
Readings
St. Amant, Ch. 3
China – Tianhe-2
Andrew Goodney
Fall 2017
1
Schedule
Date Topic Assigned Due Quizzes/Midterm/Final
What is computing, how did computers
21-Aug Introduction
come to be?
How is a modern computer built? Basic
28-Aug Computer architecture HW1
architecture and assembly
4-Sep Labor day
Why organize data? Basic structures for
11-Sep Data structures HW1
organizing data
Last day to drop a Monday-only class without a mark of “W” and receive a
18-Sep
refund or change to Pass/No Pass or Audit for Session 001
Quiz 1 on material taught in
25-Sep Data structures More structures for organizing data HW2
class 8/21-8/28
Operating on data, the notion of Quiz 2 on material taught in
2-Oct Algorithms
efficiency, simple algorithms class 9/11-9/25
6-Oct Last day to drop a course without a mark of “W” on the transcript
(Somewhat) More complicated algorithms Quiz 3 on material taught in
9-Oct Algorithms and programming HW2
and simple programming constructs class 10/2
Quiz 4 on material taught in
16-Oct Operating systems What is an OS? Why do you need one? HW3
class 10/9
Midterm on all material
23-Oct Midterm Midterm
taught so far.
How are networks organized? How is the
30-Oct Computer networks HW3
Internet organized?
What is AI? Search, plannning and a quick Quiz 5 on material taught in
6-Nov Artificial intelligence HW4
introduction to machine learning class 10/30
10-Nov Last day to drop a class with a mark of “W” for Session 001
Quiz 6 on material taught in
13-Nov The limits of computation What can (and can't) be computed?
class 11/6
Robotics: background and modern Quiz 7 on material taught in
20-Nov Robotics HW4
systems (e.g., self-driving cars) class 11/13
Quiz 8 on material taught in
27-Nov Summary, recap, review Summary, recap, review for final
class 11/20
Final on all material covered
8-Dec Final exam 11 am - 1 pm in SAL 101
in the semester 2
Computer Architecture
u Storage
Reading:
St. Amant Ch. 3
3
The von Neumann Architecture
Input Controller
Memory
Arithmetic and
Output
Logic Unit
4
The Central Processing Unit (CPU)
u Controller + ALU = Central Processing Unit (CPU)
u CPU has a small amount of temporary memory within it
v Registers
v A special register called the program counter (PC)
5
Typical Controller Tasks
Input Controller
Memory
Input Controller
Memory
Input Controller
Memory
Input Controller
Memory
Arithmetic and Logic
Output
Unit
v Retrieval is by address
9
Storage: Modular and Hierarchical
u Analogy with office files
v Each (physical) file has a number
CPU
Input Controller
MemoryRAM Disk
Arithmetic and
Logic Unit
Arithmetic and Logic
Output
Unit Registers
11
The Storage Hierarchy
CPU
Input Controller
RAM Disk
Arithmetic and
Logic Unit
Output
Registers
RAM (memory)
RAM
Cache RAM Disk Disk
Arithmetic and
Logic Unit
Output
Registers
13
Cache
u Small (but bigger than registers)
u Volatile
u Fast (not as fast as registers, but faster than RAM)
u What to keep in the cache ?
v Things that programs are likely to need in the future
v Locality principle:
14
Input and Output
u Input: Interrupt-driven
v e.g., Key strokes are slow, CPU treats them like special
events
u Output: Write to special memory (e.g., video memory)
CPU
Input Controller
15
Creating Assembly (Machine) Code
16
Programs at Different Abstraction Levels
u C code a = b + c
u Assembly code add a, b, c
u Machine code 00000010001100100100000000100000
17
Programs at Different Abstraction Levels
u C code a = b + c
u Assembly code add a, b, c
u Machine code 00000010001100100100000000100000
6 bits – opcode
5 bits: source register 1
5 bits: source register 2
5 bits: destination register
5 bits: shift amount
5 bits: functions
18
Typical Operations
u ADD Ri Rj Rk Add contents of registers Ri and Rj and put result in register Rk
u SUBTRACT Ri Rj Rk Subtract register Rj from register Ri and put result in register Rk
u AND Ri Rj Rk Bitwise AND contents of registers Ri, Rj and put result in register Rk
u NOT Ri Bitwise NOT the contents of register Ri
u OR Ri Rj Rk Bitwise OR the contents of registers Ri, Rj and put result in register Rk
u SET Ri value Set register Ri to given value
u SHIFT-LEFT Ri Shift bits of register Ri left
u SHIFT-RIGHT Ri Shift bits of register Ri right
u MOVE Ri Rj Copy contents from register Ri to register Rj
u LOAD Mi Ri Copy contents of memory location Mi to register Ri
u WRITE Ri Mi Copy contents of register Ri to memory location Mi
u GOTO Mi Jump to instruction stored in memory location Mi
u COND_GOTO Ri Rj Mi If Ri > Rj and R2, jump to instruction stored in memory location Mi
19
A Typical Day at PaniCorp
u Central processing: Connie and Alun
u The bus: Buster
u Storage (Memory): Mr. Lager Read St. Amant Ch. 3
u Input and output
20
M100 SET R1 MI
M101 SET R2 0
M102 SET R3 1
M103 SET R6 0
M104 ADD R1 R2 R4
M105 SUB R1 R3 R5
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M101 SET R2 0 3
M102 SET R3 1
M103 SET R6 0
M104 ADD R1 R2 R4
M105 SUB R1 R3 R5
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M103 SET R6 0
M104 ADD R1 R2 R4
M105 SUB R1 R3 R5
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M104 ADD R1 R2 R4
M105 SUB R1 R3 R5
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M105 SUB R1 R3 R5
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M106 MOVE R5 R1
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M107 MOVE R4 R2
M108 COND_GOTO R1 R6 104
M109 WRITE R2 M2
M110 END
M100 SET R1 MI PC R1 R2 R3 R4 R5 R6 M1 M2
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
M101 SET R2 0 3
45