Scribd
Upload
39 views

Tech Presq

This document summarizes a project involving time synchronization between LabVIEW and an FPGA for data acquisition. It discusses using an FPGA for its precise timing capabilities compared to alternatives like microcontrollers or ASICs. It also covers synchronizing multiple time-critical tasks like signal acquisition and generation through the FPGA while a less critical processing task is handled by the CPU. LabVIEW is presented as an interface for prototyping and controlling the system.

Uploaded by

engr_n_n_malik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
39 views

Tech Presq

This document summarizes a project involving time synchronization between LabVIEW and an FPGA for data acquisition. It discusses using an FPGA for its precise timing capabilities compared to alternatives like microcontrollers or ASICs. It also covers synchronizing multiple time-critical tasks like signal acquisition and generation through the FPGA while a less critical processing task is handled by the CPU. LabVIEW is presented as an interface for prototyping and controlling the system.

Uploaded by

engr_n_n_malik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 28

ECE480

Team 4
LabVIEW and FPGA Time Synchronization

Ali Aqel
Garrett Warnell
Scott Warren
Michael Weingarten
Michael Volz
Topics
 Overview
 Data Acquisition Hardware
 Field Programmable Gate Arrays
 Synchronization
 LabVIEW Fundamentals
 LabVIEW Demo
Introduction
 Many systems deal with real-world
signals
• Audio
• Video
• Biomedical
 Require a way to capture and
process them with precise timing
The Challenge
 Find a way to achieve precise sampling
rates for data acquisition
 Achieve time synchronization between
multiple data acquisition tasks
• Many time-critical tasks happening
simultaneously

 Concerns:
• Hardware
• Synchronization
Data Acquisition Hardware

 Multiple hardware solutions capable


of acquiring samples
• Microcontrollers
• ASIC - Application specific integrated
circuit
• FPGA - Field programmable gate array
Data Acquisition Hardware
 Microcontrollers
• Poor timing characteristics
• Sequential tasking not conducive to
juggling multiple tasks while
maintaining precise timing
 Possible, but difficult
Data Acquisition Hardware
 Application-Specific Integrated
Circuits (ASICs)
• Tailored to the application
 Precision timing

• Not reconfigurable
• Expensive
Data Acquisition
Hardware
 FPGA
• Tailored to the application
 Precision timing

• Reconfigurable
• Inexpensive
Common FPGAs
 Low-Cost FPGAs
• Spartan-3 - Xilinx
• Cyclone – Altera
• Arria – Altera

 High Performance FPGAs


• Virtex-4/5 – Xilinix
• Stratix – Altera
FPGA Fundamentals
 Programmable Hardware
• Adapt quickly to design changes
• Realize a variety of hardware
• Reuse, reduce, recycle
 Inherent parallelism
• Multiple hardware modules realized at
once on the same FPGA
FPGA Programming
 Hardware Description Languages
(HDL)
• VHDL
• Verilog
 Code can become complicated
 LabVIEW (Alternative)
• Modular design
Synchronization
 Two time-critical tasks (signal acquisition/generation)
 One less time-critical task (signal processing)
• We have in effect three “processes”

Dataflow
Main Program
Control Signal
Processing

Data Waveform
Acquisition Generation
Time-Critical Time-Critical
Synchronization
 Need precise timing (for signal acquisition &
generation)
 MPU: Can only do one (precisely timed) thing at a
time!
Get
samples Subroutine
Sample
Wait…
Sample
MPU Wait…
.
main .
program Return array .
(deterministic) of samples
Process
samples The Yellow area of time
is wasted!
Synchronization
 Need hardware to perform precision tasks under
the direction of a third, master process
 MPU can perform other actions while waiting for
paralleled tasks
FPGA
Get/generate
samples Generate
FPGA Sample
Wait…
Wait…
Do other Generate
Sample
MPU useful Wait…
Wait…
main things .
..
program .
Return array ..
(deterministic) .
of samples ..
Process
samples Done
Zero wasted time!
Synchronization
 Shared FIFO, First In First Out, memory buffers
are used to transfer data between the two
processes
 Interrupts are used to enforce mutually exclusive
access to the FIFO memory
main program MPU
(deterministic)

Supervisor (deterministic) User interface (non-deterministic)


Interrupt

FIFO FIFO FIFO

Real-time Task 1 RT Task 2 Fully parallel, synch’d RT Task N


processes
N FIFOs N results
FPGA
LabVIEW Fundamentals
 Popular development environment
for rapid prototyping
 Graphical programming language
• Development conducted through
functional “blocks”
 Designed to work with a wide variety
of data acquisition devices
LabVIEW and FPGAs
 LabVIEW determines FPGA gate
utilization
• Which portions of code can operate as
concurrent hardware
 Provides a variety of software
modules used to interface with
FPGAs
LabVIEW Demo
Questions

You might also like