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    Lab Print 8

    Uploaded by

    Muhammad Tehsin Rashad
    The document provides lab tasks for implementing a 2-bit comparator circuit, designing an additional combinational circuit to construct a magnitude comparator using a subtractor, and modeling a 4-bit magnitude comparator using Verilog. Specifically, it asks the student to: design the additional combinational circuit using minimum gates; provide the function table, pin layout, and demonstration of a 4-bit magnitude comparator IC; and give the dataflow modeling of a magnitude comparator in Verilog.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Lab Print 8

    Uploaded by

    Muhammad Tehsin Rashad
    141 views4 pages
    The document provides lab tasks for implementing a 2-bit comparator circuit, designing an additional combinational circuit to construct a magnitude comparator using a subtractor, and modeling a 4-bit magnitude comparator using Verilog. Specifically, it asks the student to: design the additional combinational circuit using minimum gates; provide the function table, pin layout, and demonstration of a 4-bit magnitude comparator IC; and give the dataflow modeling of a magnitude comparator in Verilog.

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    The document provides lab tasks for implementing a 2-bit comparator circuit, designing an additional combinational circuit to construct a magnitude comparator using a subtractor, and modeling a 4-bit magnitude comparator using Verilog. Specifically, it asks the student to: design the additional combinational circuit using minimum gates; provide the function table, pin layout, and demonstration of a 4-bit magnitude comparator IC; and give the dataflow modeling of a magnitude comparator in Verilog.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    141 views4 pages

    Lab Print 8

    Uploaded by

    Muhammad Tehsin Rashad
    The document provides lab tasks for implementing a 2-bit comparator circuit, designing an additional combinational circuit to construct a magnitude comparator using a subtractor, and modeling a 4-bit magnitude comparator using Verilog. Specifically, it asks the student to: design the additional combinational circuit using minimum gates; provide the function table, pin layout, and demonstration of a 4-bit magnitude comparator IC; and give the dataflow modeling of a magnitude comparator in Verilog.

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    © All Rights Reserved
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    Lab Tasks:

    4. Implement the 2-bit Comparator circuit you arrived in your Pre-lab Task. Give the Complete
    circuit diagram here again. (6 Marks)

    5. A magnitude comparator can be constructed by using a subtractor and an additional


    combinational circuit. This is done with a combinational circuit that has 5 inputs S1, S2, S3,
    S4, and Co, and three outputs E, G, L as shown below.
    E = 1 if A=B i.e. when S = 0000, L = 1 if A<B i.e. when Co = 0, G = 1 if A > B i.e. when Co = 1
    and S ≠ 0000.

    Design and construct this additional combinational circuit using minimum number of gates.
    (5 Marks)
    E

    ?
    G

    You have to design this part

    Schematic Diagram(Additional Combinational Circuit):


    6. Get the 4 bit magnitude comparator IC from the lab. Give its function table, Pin Layout and
    show its working in hardware.
    7. Give the dataflow modeling of the magnitude comparator using Verilog. (5 Marks)

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