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Lab5 BCD-to-Excess-3 Code Conversion2

This document contains instructions for a lab assignment on designing a BCD to excess-3 code converter and modeling it in Verilog. The lab has three parts: pre-lab tasks, lab tasks, and post-lab evaluation. In the pre-lab, students are asked to explain decimal codes, write the excess-3 code for their registration number, and derive the logic expressions for the converter. The lab tasks involve implementing the converter with NAND gates and writing Verilog code to model and test the design.

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Muhammad Tehsin Rashad
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1K views10 pages

Lab5 BCD-to-Excess-3 Code Conversion2

This document contains instructions for a lab assignment on designing a BCD to excess-3 code converter and modeling it in Verilog. The lab has three parts: pre-lab tasks, lab tasks, and post-lab evaluation. In the pre-lab, students are asked to explain decimal codes, write the excess-3 code for their registration number, and derive the logic expressions for the converter. The lab tasks involve implementing the converter with NAND gates and writing Verilog code to model and test the design.

Uploaded by

Muhammad Tehsin Rashad
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Department of Electrical Engineering

Faculty/LabEngr:___________________ Date: ___________________

Course/Section:_____________________ Semester:________________

EE221: Digital Logic Design


Lab5: Part (a): BCD to Excess-3 Code Conversion

Lab5: Part (b): Gate-level Modeling in Verilog

Name Reg. No. Report Evaluation Total


Marks / 25 Marks / 10 Marks / 35

EE221: Digital Logic Design Page 1


Lab 5: BCD to Excess-3 Code Conversion

This Lab has been divided into two parts: Psychomotor Level P-4
In first part you are required to design and implement a BCD to Excess-3 code converter.
The next part is the Verilog Modeling and Simulation of the Circuit you implemented in you first
lab.
Objectives:

 Understand steps involved in design of combinational circuits


 Understand binary codes for decimals and their hardware realization
 Write code for combinational circuits using Verilog Gate Level Modeling
 Design a circuit in Verilog by calling different modules

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab
Viva session.
 The lab report will be uploaded on LMS three days before scheduled lab date. The
students will get hard copy of lab report, complete the Pre-lab task before coming to
the lab and deposit it with teacher/lab engineer for necessary evaluation.
 The students will start lab task and demonstrate design steps separately for step-
wise evaluation(course instructor/lab engineer will sign each step after ascertaining
functional verification).
 Remember that a neat logic diagram with pins numbered coupled with nicely
patched circuit will simplify trouble-shooting process.
 After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
 The students will complete lab task and submit complete report to Lab Engineer
before leaving lab.
 There are related questions at the end of this activity. Give complete answers.

EE221: Digital Logic Design Page 2


Pre-Lab Tasks: (To be done before coming to the lab)
1. What do you understand by decimal codes? Name any three of these. Express the last
four digits of your registration number duly negated in signed magnitude, 10’s
complement, and 9’s complement forms for the following codes:
a. 8,4,2,1
b. Excess-3
(4 Marks)

2. What is the significance of BCD code? Write its application in digital circuits.(1 Mark)

3. In the lab you would be implementing a BCD to Excess-3 code converter. Make a truth
table for both the codes by filling in the following tables and Simplify the expressions for
W,X,Y,Z in terms of A,B,C,D.( Use backside of the page if necessary). Use unused
combinations as don’t care conditions. (5 Marks)

Dec BCD XS-3

A B C D W X Y Z
W= ((BD)' . (AD)' . (AB')' . (BC)')'
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0 X= ((BC'D)' . (B'D)' . (B'C)')'
2 0 0 1 0 0 1 0 1
Y= ((C'D')' . (CD)')'
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1 Z = D'
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0

EE221: Digital Logic Design Page 3


4. Draw the logic diagram for BCD to Excess-3 code converter using NAND gates in the
space provided below. (5 Marks)

EE221: Digital Logic Design Page 4


EE221: Digital Logic Design Page 5
Choose the required gates out of the following gates.

Lab Tasks: (To be completed in the lab)

Lab Task 1:

Realize the BCD to Excess-3 code converter using NAND gates only. Make the Schematic
Diagram. Show the results to your Teacher/Lab Engr. (5+5 Marks)

EE221: Digital Logic Design Page 6


Lab Task2:

Design and simulate the gate-level model of the circuit you patched. Give the code in the space
provided below. (5+5 Marks)

module mod(w,x,y,z,a,b,c,d);

input a,b,c,d; // inputs

output w,x,y,z; // outputs

nand(An,a,a); // a not

nand(Bn,b,b); // b not

nand(Cn,c,c); // c not

nand(Dn,d,d); // d not

EE221: Digital Logic Design Page 7


// code for w

nand(w1,b,d); // (bd)'

nand(w2,a,d); // (ad)'

nand(w3,a,Bn); // (ab')'

nand(w4,b,Cn); // (bc')'

nand(w,w1,w2,w3,w4); // w

// code for x

nand(x1,b,Cn,d); // (bc'd)'

nand(x2,Bn,d); // (b'd)'

nand(x3,Bn,c); // (b'c)'

nand(x,x1,x2,x3); // x

//code for y

nand(y1,Cn,Dn); // (c'd')'

nand(y2,c,d); // (cd)'

nand(y,y1,y2);

// code for z

nand(z,d,d); // z

// testbench

module myTest();

reg A,B,C,D;

EE221: Digital Logic Design Page 8


wire W,X,Y,Z;

mod d(W,X,Y,Z,A,B,C,D);

initial

begin

A=1'b0;B=1'b0;C=1'b0;D=1'b0; // 0

#100A=1'b0;B=1'b0;C=1'b0;D=1'b1; // 1

#100A=1'b0;B=1'b0;C=1'b1;D=1'b0; // 2

#100A=1'b0;B=1'b0;C=1'b1;D=1'b1; // 3

#100A=1'b0;B=1'b1;C=1'b0;D=1'b0; // 4

#100A=1'b0;B=1'b1;C=1'b0;D=1'b1; // 5

#100A=1'b0;B=1'b1;C=1'b1;D=1'b0; // 6

#100A=1'b0;B=1'b1;C=1'b1;D=1'b1; // 7

#100A=1'b1;B=1'b0;C=1'b0;D=1'b0; // 8

#100A=1'b1;B=1'b0;C=1'b0;D=1'b1; // 9

#100;

end

endmodule

EE221: Digital Logic Design Page 9


EE221: Digital Logic Design Page 10

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