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III. Ratioed Logic Circuit

Ratioed MOS circuits use weaker pull-up devices and stronger pull-down devices to reduce input capacitance and improve logical effort. They were commonly used despite high power dissipation. A 4-input NAND gate example shows a pseudo-NMOS logic using a single always-on pMOS transistor instead of a pull-up network, reducing components, area, capacitance and complexity compared to a static gate.

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166 views1 page

III. Ratioed Logic Circuit

Ratioed MOS circuits use weaker pull-up devices and stronger pull-down devices to reduce input capacitance and improve logical effort. They were commonly used despite high power dissipation. A 4-input NAND gate example shows a pseudo-NMOS logic using a single always-on pMOS transistor instead of a pull-up network, reducing components, area, capacitance and complexity compared to a static gate.

Uploaded by

aishwarya wagh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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III.

Ratioed Logic Circuit

Ratioed MOS circuits have been known for many years, and were used widely in the past despite

their high power dissipation because they are fast static circuits[3]. Ratioed circuits use weak

pull-up devices and stronger pull-down devices. They reduce the input capacitance and hence

improve logical effort by eliminating large PMOS transistors loading the inputs. Fig.4 shows the

schematic circuit diagram of 4-input NAND gate using pseudo-NMOS logic gates, which are the

most common form of CMOS ratioed logic. The pull-down network is like that of a static

gate,but the pull-up network has been replaced with a single pMOS transistor that is grounded so

it is always ON[1]. The main advantage of 4 -input pseudo NMOS logic gate is that there is 1-

pMOS and 4-NMOS transistors is used, so the number of components has reduced and area also

reduced. It also reduces the complexities of the circuit. Because of less hardware used so the

capacitance become reduced.

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