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    Chapter4 Hw4 Modelanswer

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    crkrisky
    This document contains the model answers to 6 questions from a digital logic design homework assignment. Question 1 involves drawing the truth table and deriving the simplified Boolean expression for a 4-input, 1-output function. Question 2 asks to design a circuit to compare two 4-bit numbers. Question 3 involves using five 2-to-4 decoders to create a 4-to-16 line decoder. Question 4 asks to implement an 8-to-1 multiplexer using smaller multiplexers. Question 5 is about designing a priority encoder and deriving its output expressions. Question 6 concludes by deriving the Boolean function F from a given logic diagram.

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    Chapter4 Hw4 Modelanswer

    Uploaded by

    crkrisky
    21 views4 pages
    This document contains the model answers to 6 questions from a digital logic design homework assignment. Question 1 involves drawing the truth table and deriving the simplified Boolean expression for a 4-input, 1-output function. Question 2 asks to design a circuit to compare two 4-bit numbers. Question 3 involves using five 2-to-4 decoders to create a 4-to-16 line decoder. Question 4 asks to implement an 8-to-1 multiplexer using smaller multiplexers. Question 5 is about designing a priority encoder and deriving its output expressions. Question 6 concludes by deriving the Boolean function F from a given logic diagram.

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    Chapter4 Hw4 Modelanswer (2)

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    This document contains the model answers to 6 questions from a digital logic design homework assignment. Question 1 involves drawing the truth table and deriving the simplified Boolean expression for a 4-input, 1-output function. Question 2 asks to design a circuit to compare two 4-bit numbers. Question 3 involves using five 2-to-4 decoders to create a 4-to-16 line decoder. Question 4 asks to implement an 8-to-1 multiplexer using smaller multiplexers. Question 5 is about designing a priority encoder and deriving its output expressions. Question 6 concludes by deriving the Boolean function F from a given logic diagram.

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    © All Rights Reserved
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    Download as docx, pdf, or txt
    21 views4 pages

    Chapter4 Hw4 Modelanswer

    Uploaded by

    crkrisky
    This document contains the model answers to 6 questions from a digital logic design homework assignment. Question 1 involves drawing the truth table and deriving the simplified Boolean expression for a 4-input, 1-output function. Question 2 asks to design a circuit to compare two 4-bit numbers. Question 3 involves using five 2-to-4 decoders to create a 4-to-16 line decoder. Question 4 asks to implement an 8-to-1 multiplexer using smaller multiplexers. Question 5 is about designing a priority encoder and deriving its output expressions. Question 6 concludes by deriving the Boolean function F from a given logic diagram.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 4

    Princess Nora University CS 121- Digital Logic Design

    College of Computer and Information Sciences Homework -4 (Chapter 4)


    Department of Computer Sciences 2nd Semester 1433-1434H

    Model Answer

    Q1: The four input function (A,B,C,D) and one output ( Y ) , the output (Y) equal ( 1 )
    when ABCD is greater than 5 and the binary input value is even , otherwise the output
    is equal BD .
    a) Draw the truth table

    A B C D Y
    0 0 0 0 0
    0 0 0 1 1
    0 0 1 0 0
    0 0 1 1 1
    0 1 0 0 1
    0 1 0 1 0
    0 1 1 0 1
    0 1 1 1 0
    1 0 0 0 1
    1 0 0 1 1
    1 0 1 0 1
    1 0 1 1 1
    1 1 0 0 1
    1 1 0 1 0
    1 1 1 0 1
    1 1 1 1 0

    b) Find the simplify function of ( Y ) by k-map

    Y= AB + BD+ BD
    c) Draw function gate

    Best wishes
    Q2: Design a circuit that compares two 4-bit numbers, A and B, to check if they are
    equal. The circuit has one output X, so that X=1 if A=B, and X=0 if A! = B.

    A B E
    0 0 1
    0 1 0
    1 0 0
    1 1 1

    E=AB+AB =(A xor B)

    Q3: Design a 4-to-16 line decoder with enable using five 2-to-4 line decoders with
    enable.
    A0 D0
    2X4
    A1 Decoder
    EN
    D3

    A0 2X4 D4
    Decoder
    A2 2X4 A1 EN
    D7
    A3 Decoder
    3 A0 2X4 D8
    Decoder
    A1 EN
    D11

    A0 2X4 D12
    Decoder
    A1 EN
    D15

    Best wishes
    Q4:Design an 8-to-1 line multiplexer using 4-to-1 line multiplexer and one 2-to-1-line
    multiplexer.
    S0
    4X1
    S1
    MUX S2
    I0
    I1
    I2 2X1
    I3 Y
    MUX

    S0 4X1
    S1
    MUX
    I4
    I5
    I6
    I7

    Q5.Priority Encoder used to resolve the ambiguity of illegal inputs, please read chapter
    4 (slide 41), draw the Karnaugh maps for simplifying outputs x and y where D0 has the
    highest priority and D3 lower priority and then draw the circuit.

    input output
    D0 D1 D2 D3 X Y V
    0 0 0 0 x x 0
    1 x x x 0 0 1
    0 1 x x 0 1 1
    0 0 1 x 1 0 1
    0 0 0 1 1 1 1

    D2 D3
    D0 D1
    x 1 1 1

    X= D0 D1

    D2 D3
    D0 D1
    x 1
    1 1 1 1

    Y= D0 D1+ D0 D2

    Best wishes
    Q6: Derive the Boolean function F from Fig.

    F=( (AB)(CD + E))+E

    Best wishes

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