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Design of (7, 4) Hamming Encoder and Decoder

Using VHDL.

Conference Paper September 2015

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Design of (7, 4) Hamming Encoder and Decoder Using VHDL

Usman Sammani Sani1*, Ibrahim Haruna Shanono2
1,2
Department of Electrical Engineering,
Bayero University, Kano, P.M.B. 3011, Nigeria
Corresponding Authors Email: [email protected], Phone Number: 08025791503

ABSTRACT
Hamming code is one of the commonest codes used in the protection of information from error. It takes a block of k input
bits and produce n bits of codeword. This work presents a way of designing (7, 4) Hamming encoder and decoder using
Very High Speed Integrated Circuit Hardware Description Language (VHDL). The encoder takes 4 bits input data and
produces a 7 bit codeword. The encoder was designed through the usual generator matrix multiplication while in the
decoder design the computation of the syndrome vector was ignored. Meanwhile, the different states that can represent a
particular input were calculated and the decoder was designed to identify each codeword representing a particular input.
Results have shown that the method is also reliable.
Keywords: Hamming, VHDL, Encoder, Decoder, Syndrome vector.

single bit error (Peter, 2002) and are mostly used in

1. INTRODUCTION Random Access Memory for error correction
Hamming codes are used in error detection and purpose (Mistri et al, 2014).
correction in digital communication circuitries.
Hamming codes belong to the class of block codes
which are codes that work on a block of bits rather
than individual bits of data. A block code
designated by (n, k) means k bits of input data is
used in producing a codeword, C with n bits of data (3)
(Edward and David, 1994), (Richard, 2003). The n For a codeword C,
k bits added are called parity check bits. Thus a Z = Hr (4)
(7, 4) Hamming encoder produces 7 bits from 4 In this work, a (7, 4) Hamming encoder and
bits and the codeword has 4 parity check bits. decoder is designed using Very High Speed
Hamming codes are usually generated by Integrated Circuit Hardware Description Language
multiplying the input block, x by a generator (VHDL). VHDL is a programming language that
matrix, G (John, 2007). Digital communications became popular in the 1990s. It is similar to other
involves 0s and 1s. Both the generator matrix and high level programming languages such as C but in
the input matrix are in form of 0s and 1s. The its own case it doesnt have a compiler but has a
addition involved during the multiplication of the synthesizer. The synthesizer translates the written
two matrices is modulo two addition (Edward source code into an equivalent hardware described
and David, 1994). For example a (7, 4) Hamming by the source code. The process of this translation
code has the generator matrix is called synthesis (Enoch, 2006).
2. METHODOLOGY
The G and H matrices above were used in the
process. The encoder and decoder design will be
discussed separately.
(1) 2.1 Encoder Design
For an input x, The encoder has a generator matrix in which it
C = Gx (2) produces the codewords. The codeword is a vector
Hamming codes are decoded by multiplying the with seven bits. Each bit is obtained by multiplying
codeword received, r by a parity check matrix, H to the input matrix by a column in G as shown below:
see whether there is an error or not. The resulting C(1) = x(1)
matrix is called a syndrome vector, Z. If Z is zero, C(2) = x(2)
it means there is no error while if Z is not zero, C(3) = x(3)
then the position of the bit that is in error is C(4) = x(4)
indicated by Z. Hamming codes can only correct a C(5) = x(1) XOR x(2) XOR x(4)

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C(6) = x(1) XOR x(3) XOR x(4) 11 1010 1010101

C(7) = x(2) XOR x(3) XOR x(4) 12 1011 1011010
13 1100 1100011
C(n) stands for the nth bit in the codeword and x(n) 14 1101 1101100
stands for the nth bit of the input bits. The VHDL 15 1110 1110000
code was then developed and synthesized using 16 1111 1111111
XILINX ISE 10.1 software.
Hamming codes can correct a single error. So in
2.2 Decoder Design this work, bits of a codeword representing a
For restoring the original message, the codewords particular input were altered one by one and each
corresponding to the 16 possible combinations of new codeword represents that same input.
input were calculated using some Matlab codes. Therefore in this case the need of computing the
The results of the 16 combinations of 4 bit input syndrome vector and later on correcting the bit in
data resulted in the table below: error has been abandoned, unlike in (Saleh, 2015),
where the syndrome vector was computed. This
Table 1. Codewords for 4 input data. method also differs from that of (Hosamani and
S/N X C Karne, 2014), in which the parity bits were inserted
1 0000 0000000 directly without the use of a defined generator
2 0001 0001111 matrix at the encoder and then the received parity
3 0010 0010011 bits were also computed at the decoder. Thus in
4 0011 0011100 our own case, each of the 16 input combinations
5 0100 0100101 has 8 different codewords representing it. The
6 0101 0101010 whole seven bits possible combinations of
7 0110 0110110 codewords has thus been assigned the correct input
8 0111 0111001 representing it (i.e. 27 = (16 x 8) = 128). The table
9 1000 1000110 below shows the different combinations of
10 1001 1001001 codewords and there corresponding inputs.

Table 2. Codewords extension of 4 bits input.

S/N x C 1011100
1. 0000 0000000 0111100
1000000 0001100
0100000 0010100
0010000 0011000
0001000 0011110
0000100 0011101
0000010 5. 0100 0100101
0000001 1100101
2. 0001 0001111 0000101
1001111 0110101
0101111 0101101
0011111 0100001
0000111 0100111
0001011 0100100
0001101 6. 0101 0101010
0001110 1101010
3. 0010 0010011 0001010
1010011 0111010
0110011 0100010
0000011 0101110
0011011 0101000
0010111 0101011
0010001 7. 0110 0110110
0010010 1110110
4. 0011 0011100 0010110

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0100110 0011010
0111110 1111010
0110010 1001010
0110100 1010010
0110111 1011110
1011000
8. 0111 0111001 1011011
1111001 13. 1100 1100011
0011001 0100011
0101001 1000011
0110001 1110011
0111101 1101011
0111011 1100111
0111000 1100001
9. 1000 1000110 1100010
0000110 14. 1101 1101100
1100110 0101100
1010110 1001100
1001110 1111100
1000010 1100100
1000100 1101000
1000111 1101110
10. 1001 1001001 1101101
0001001 15. 1110 1110000
1101001 0110000
1011001 1010000
1000001 1100000
1001101 1111000
1001011 1110100
1001000 1110010
11. 1010 1010101 1110001
0010101 16. 1111 1111111
1110101 0111111
1000101 1011111
1011101 1101111
1010001 1110111
1010111 1111011
1010100 1111101
12. 1011 1011010 1111110

Codes were also written in VHDL to describe the

decoder.
3. RESULTS

Figure 1. Register transfer level of the encoder.

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Figure 2. Component view of the encoder

Figure 3. Register transfer level of the decoder

Figure 4. Component view of the Decoder

5. CONCLUSION Hosamani R., Karne A.S., design and Implementation of

The paper has presented a way of designing (7, 4) Hamming Code on FPGA Using Verilog, International
Hamming encoder and decoder using VHDL. The encoder journal of Engineering and Advanced technology, Vol.4,
was designed the normal way while some modifications Issue 2, 2014, pp 181-184.
were made in the decoder design that avoided the
computation of a syndrome vector. Results have shown John P., Masoud S., Digital Communications, McGraw-
how VHDL simplifies the design of digital hardware and Hill, 2007, pp 413-418.
how the design procedure is effective. The same process Peter S., Error Control Coding; from theory to practice,
can be used in the design of any Hamming encoder and John Wiley and Sons ltd, 2002, pp 6769.
decoder. The designed circuits can be used in places they
would be applicable or even be left as trainers for students Mistri R. K. et al, Reduced Area and Improved Delay
to understand the concept of Hamming encoding and Module Design of 16 bit Hamming Codec Using HSPICE
decoding. Thus several digital logic circuits meant for 22nm Technology Based on GDI Technique, international
experiment could be designed so that they can be used on a Journal of Scientific and Research publications, vol. 4,
single target device such as a Field Programmable Gate Issue 7, 2014, pp 1-6.
Array. This reduces the cost of setting up a laboratory.
Richard E. B., Algebraic Codes for Data Transmission,
REFERENCES Cambridge University Press, 2003, pp54.
Edward A. L., David G.M., Digital Communication,
Kluwer Academic Publishers, 1994, pp613-617. Saleh A.H., Design of Hamming Encoder and Decoder
Circuits for (64,7) Code and (128,8) Code Using VHDL,
Enoch O. H., Digital Logic and Microprocessor Design Journal of Scientific and Engineering Research, Vol. 4,
with VHDL, La Sierra University, 2006, pp 23-26. Issue 1, 2015, pp 1-4.

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