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Shrinathji Institute of Technology & Engineering Department of Electronics and Communication Engineering

This document provides the timetable for the final year B. Tech ECE semester VII class at the Shrinathji Institute of Technology & Engineering. The timetable lists the class schedule from Monday to Saturday, with periods running from 8:00-2:00 during summer and 9:00-3:00 during winter. Various subjects like VLSI Design, DSP, AWP, and their labs are scheduled during each period along with remedial/makeup classes and seminars. Project work is scheduled on Saturdays from 12:40-1:10 in room RN.08.

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45 views1 page

Shrinathji Institute of Technology & Engineering Department of Electronics and Communication Engineering

This document provides the timetable for the final year B. Tech ECE semester VII class at the Shrinathji Institute of Technology & Engineering. The timetable lists the class schedule from Monday to Saturday, with periods running from 8:00-2:00 during summer and 9:00-3:00 during winter. Various subjects like VLSI Design, DSP, AWP, and their labs are scheduled during each period along with remedial/makeup classes and seminars. Project work is scheduled on Saturdays from 12:40-1:10 in room RN.08.

Uploaded by

erkomal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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SHRINATHJI INSTITUTE OF TECHNOLOGY & ENGINEERING

Department of Electronics and Communication Engineering


UPALIODEN, NATHDWARA, RAJSAMAND. (RAJASTHAN)

TIME-TABLE

Class: Final Year B. Tech ECE Semester: VII Room No: 119 Session:2015-16
Come into force from: 01-Aug-2015

Periods I II III IV V VI
Days Summer 08:00 8:55 08:55 9:50 09:50 10:45 10:45 11:40 12:10 1:05 01:05 02:00
Winter 09.00 09.55 09.55 10.50 10.50 11.45 11.45 12.40
L 01.10 02.05 02.05 03.00
VLSI Design (L) AWP (L) WC (L) DSP (L)
U WC Lab
Monday
(Ms. Shinu Soni) (Ms. Komal Daiya) (Ms. Komal Daiya) (Ms. Shinu Soni) N (Ms. Komal Daiya)

VLSI Design (L) DSP (L) AWP (L) DIP (L)


C VHDL (L)
Tuesday (Ms. Shinu Soni) (Ms. ShinuSoni) (Ms. Komal Daiya) (Ms. Shinu Soni) H (Ms. Komal Library
Daiya)

VLSI Design (L) AWP (L) DIP (L) VHDL (L) Signal & Image Processing Lab
Wednesday
(Ms. ShinuSoni) (Ms. Komal Daiya) (Ms. ShinuSoni) (Ms. Komal Daiya) B (Ms. Shinu Soni)
R
VHDL (L) DIP (L) WC (L) DSP (L) Remedial Classes/
Thursday
(Ms. Komal Daiya) (Ms. Shinu Soni) (Ms. Komal Daiya) (Ms. Shinu Soni) E Makeup Classes
A
DIP (T) WC (L) AWP (T) DSP (T) Seminar
Friday (Ms. Shinu Soni) (Ms. Komal Daiya) (Ms. Komal Daiya) (Ms. Shinu Soni) K (Ms. Komal Daiya)
11:40
12:10
Project Stage-I Project Stage-I Project Stage-I
Saturday 12.40
RN.08 RN.08 01.10
RN.08

DIP: Digital Image Processing, WC: Wireless Communication, AWP: Antenna & Wave Propagation

Note: The students can submit the holding of remedial/makeup classes in any subject, which will be arranged on Thursday.

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