Pipelining DLX PDF
Pipelining DLX PDF
Pipelining DLX PDF
0 5 6 10 11 15 16 20 31
Register-register ALU operations: rd rs1 func rs2 Function encodes the data path operation:
Add, Sub .. Read/write special registers and moves.
J - Type instruction 6 bits 26 bits
0 5 6 31
Jump and jump and link. Trap and return from exception
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A Basic Multi-Cycle
Implementation of DLX
Every integer DLX instruction can be implemented in at
most five clock cycles:
1 Instruction fetch cycle (IF):
IR Mem[PC]
NPC PC + 4
Branch:
ALUOutput NPC + Imm;
Cond (A op 0)
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A Basic Implementation of DLX (continued)
Memory reference:
LMD Mem[ALUOutput] or
Mem[ALUOutput] B;
Branch:
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A Basic Implementation of DLX (continued)
5 Write-back cycle (WB):
Register-Register ALU instruction:
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A Multi-Cycle
DLX Datapath
Implementation
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Pipelining: Definitions
Pipelining is an implementation technique where multiple
operations on a number of instructions are overlapped in
execution.
An instruction execution pipeline involves a number of
steps, where each step completes a part of an instruction.
Each step is called a pipe stage or a pipe segment.
The stages or steps are connected one to the next to form a
pipe -- instructions enter at one end and progress through
the stage and exit at the other end.
Throughput of an instruction pipeline is determined by
how often an instruction exists the pipeline.
The time to move an instruction one step down the line is is
equal to the machine cycle and is determined by the stage
with the longest processing delay.
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Pipelining: Design Goals
The length of a machine clock cycle is determined by the
time required for the slowest pipe stage.
An important pipeline design consideration is to balance the
length of each pipeline stage.
If all stages are perfectly balanced, then the time per
instruction on a pipelined machine (assuming ideal
conditions with no stalls):
Time per instruction on unpipelined machine
Number of pipe stages
Under these ideal conditions:
Speedup from pipelining equals the number of pipeline stages: n,
One instruction is completed every cycle, CPI = 1 .
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Simple DLX Pipelined
Instruction Processing
Clock Number Time in clock cycles
Instruction Number 1 2 3 4 5 6 7 8 9
Instruction I IF ID EX MEM WB
Instruction I+1 IF ID EX MEM WB
Instruction I+2 IF ID EX MEM WB
Instruction I+3 IF ID EX MEM WB
Instruction I +4 IF ID EX MEM WB
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Basic Performance Issues In Pipelining
Pipelining increases the CPU instruction throughput:
The number of instructions completed per unit time.
Under ideal condition instruction throughput is one
instruction per machine cycle, or CPI = 1
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Pipelining Performance Example
Example: For an unpipelined machine:
Clock cycle = 10ns, 4 cycles for ALU operations and branches
and 5 cycles for memory operations with instruction frequencies
of 40%, 20% and 40%, respectively.
If pipelining adds 1ns to the machine clock cycle then the
speedup in instruction execution from pipelining is:
Non-pipelined Average instruction execution time = Clock cycle x Average CPI
= 10 ns x ((40% + 20%) x 4 + 40%x 5) = 10 ns x 4.4 = 44 ns
In the pipelined five implementation five stages are used with
an average instruction execution time of: 10 ns + 1 ns = 11 ns
Speedup from pipelining = Instruction time unpipelined
Instruction time pipelined
= 44 ns / 11 ns = 4 times
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Pipeline Hazards
Hazards are situations in pipelining which prevent the next
instruction in the instruction stream from executing during
the designated clock cycle.
Hazards reduce the ideal speedup gained from pipelining
and are classified into three classes:
Structural hazards: Arise from hardware resource
conflicts when the available hardware cannot support all
possible combinations of instructions.
Data hazards: Arise when an instruction depends on
the results of a previous instruction in a way that is
exposed by the overlapping of instructions in the
pipeline
Control hazards: Arise from the pipelining of conditional
branches and other instructions that change the PC
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Performance of Pipelines with Stalls
Hazards in pipelines may make it necessary to stall the
pipeline by one or more cycles and thus degrading
performance from the ideal CPI of 1.
CPI pipelined = Ideal CPI + Pipeline stall clock cycles per instruction
When all instructions take the same number of cycles and is equal to
the number of pipeline stages then:
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Performance of Pipelines with Stalls
If we think of pipelining as improving the effective clock cycle
time, then given the the CPI for the unpipelined machine and
the CPI of the ideal pipelined machine = 1, then effective
speedup of a pipeline with stalls over the unpipelind case is
given by:
Speedup = 1 X Clock cycles unpiplined
Clock cycle pipelined
1 + Pipeline stall cycles
When pipe stages are balanced with no overhead, the clock
cycle for the pipelined machine is smaller by a factor equal to
the pipelined depth:
Clock cycle pipelined = clock cycle unpipelined / pipeline depth
Pipeline depth = Clock cycle unpipelined / clock cycle pipelined
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Structural Hazards
In pipelined machines overlapped instruction execution
requires pipelining of functional units and duplication of
resources to allow all possible combinations of instructions
in the pipeline.
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Resolving A Structural
Hazard with Stalling
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A Structural Hazard Example
Given that data references are 40% for a specific
instruction mix or program, and that the ideal pipelined
CPI ignoring hazards is equal to 1.
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Data Hazards
Data hazards occur when the pipeline changes the order of
read/write accesses to instruction operands in such a way that
the resulting access order differs from the original sequential
instruction operand access order of the unpipelined machine
resulting in incorrect execution.
Data hazards usually require one or more instructions to be
stalled to ensure correct execution.
Example:
ADD R1, R2, R3
SUB R4, R1, R5
AND R6, R1, R7
OR R8,R1,R9
XOR R10, R1, R11
All the instructions after ADD use the result of the ADD instruction
SUB, AND instructions need to be stalled for correct execution.
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DLX Data
Hazard Example
Figure 3.9 The use of the result of the ADD instruction in the next three instructions
causes a hazard, since the register is not written until after those instructions read it.
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Minimizing Data hazard Stalls by Forwarding
Forwarding is a hardware-based technique (also called register
bypassing or short-circuiting) used to eliminate or minimize
data hazard stalls.
Using forwarding hardware, the result of an instruction is copied
directly from where it is produced (ALU, memory read port
etc.), to where subsequent instructions need it (ALU input
register, memory write port etc.)
For example, in the DLX pipeline with forwarding:
The ALU result from the EX/MEM register may be forwarded or fed
back to the ALU input latches as needed instead of the register
operand value read in the ID stage.
Similarly, the Data Memory Unit result from the MEM/WB register
may be fed back to the ALU input latches as needed .
If the forwarding hardware detects that a previous ALU operation is to
write the register corresponding to a source for the current ALU
operation, control logic selects the forwarded result as the ALU input
rather than the value read from the register file.
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Pipelined DLX
with Forwarding
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Load/Store Forwarding Example
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Data Hazard Classification
Given two instructions I, J, with I occurring before J
in an instruction stream:
RAW (read after write): A true data dependence
J tried to read a source before I writes to it, so J
incorrectly gets the old value.
WAW (write after write): A name dependence
J tries to write an operand before it is written by I
The writes end up being performed in the wrong order.
I (Write) I (Read)
Shared Shared
Operand Operand
J (Write) J (Read)
Write after Write (WAW) Read after Read (RAR) not a hazard
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Data Hazards Present in Current DLX Pipeline
Read after Write (RAW) Hazards: Possible?
Results from true data dependencies between instructions.
Yes possible, when an instruction requires an operand generated by a preceding
instruction with distance less than four.
Resolved by:
Forwarding or Stalling.
Write after Read (WAR):
Results when an instruction overwrites the result of an instruction before all
preceding instructions have read it.
Write after Write (WAW):
Results when an instruction writes into a register or memory location before a
preceding instruction have written its result.
Possible? Both WAR and WAW are impossible in the current pipeline.
Why?
Pipeline processes instructions in the same sequential order as in the program.
All instruction operand reads are completed before a following instruction
overwrites the operand.
Thus WAR is impossible in current DLX pipeline.
All instruction result writes are done in the same program order.
Thus WAW is impossible in current DLX pipeline.
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Data Hazards Requiring Stall Cycles
In some code sequence cases, potential data hazards
cannot be handled by bypassing. For example:
LW R1, 0 (R2)
SUB R4, R1, R5
AND R6, R1, R7
OR R8, R1, R9
The LW (load word) instruction has the data in clock
cycle 4 (MEM cycle).
The SUB instruction needs the data of R1 in the
beginning of that cycle.
Hazard prevented by hardware pipeline interlock
causing a stall cycle.
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Hardware Pipeline Interlocks
A hardware pipeline interlock detects a data hazard and
stalls the pipeline until the hazard is cleared.
The CPI for the stalled instruction increases by the
length of the stall.
For the Previous example, (no stall cycle):
LW R1, 0(R1) IF ID EX MEM WB
SUB R4,R1,R5 IF ID EX MEM WB
AND R6,R1,R7 IF ID EX MEM WB
OR R8, R1, R9 IF ID EX MEM WB
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Compiler Instruction Scheduling
for Data Hazard Stall Reduction
Many types of stalls resulting from data hazards are very
frequent. For example:
A = B+ C
produces a stall when loading the second data value (B).
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Compiler Instruction Scheduling Example
For the code sequence:
a, b, c, d ,e, and f
a=b+c are in memory
d=e-f
Assuming loads have a latency of one clock cycle, the following
code or pipeline compiler schedule eliminates stalls:
Original code with stalls: Scheduled code with no stalls:
LW Rb,b LW Rb,b
LW Rc,c LW Rc,c
Stall
ADD Ra,Rb,Rc LW Re,e
SW a,Ra ADD Ra,Rb,Rc
LW Re,e LW Rf,f
LW Rf,f SW a,Ra
Stall
SUB Rd,Re,Rf SUB Rd,Re,Rf
SW d,Rd SW d,Rd
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Control Hazards
When a conditional branch is executed it may change the PC
and, without any special measures, leads to stalling the pipeline
for a number of cycles until the branch condition is known.
In current DLX pipeline, the conditional branch is resolved in
the MEM stage resulting in three stall cycles as shown below:
Three clock cycles are wasted for every branch for current DLX pipeline
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Reducing Branch Stall Cycles
Pipeline hardware measures to reduce branch stall cycles:
1- Find out whether a branch is taken earlier in the pipeline.
2- Compute the taken PC earlier in the pipeline.
In DLX:
In DLX branch instructions BEQZ, BNEZ, test a register
for equality to zero.
This can be completed in the ID cycle by moving the zero
test into that cycle.
Both PCs (taken and not taken) must be computed early.
Requires an additional adder because the current ALU is
not useable until EX cycle.
This results in just a single cycle stall on branches.
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Modified DLX Pipeline:
Conditional Branches
Completed in ID Stage
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Compile-Time Reduction of Branch Penalties
One scheme discussed earlier is to flush or freeze the
pipeline by whenever a conditional branch is decoded by
holding or deleting any instructions in the pipeline until
the branch destination is known (zero pipeline registers,
control lines)).
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Static Compiler Branch Prediction
Two basic methods exist to statically predict branches
at compile time:
1 By examination of program behavior and the use of
information collected from earlier runs of the program.
For example, a program profile may show that most forward
branches and backward branches (often forming loops) are
taken. The simplest scheme in this case is to just predict the
branch as taken.
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Profile-Based Compiler Branch
Misprediction Rates
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Reduction of Branch Penalties:
Delayed Branch
When delayed branch is used, the branch is delayed by n cycles,
following this execution pattern:
conditional branch instruction
sequential successor1
sequential successor2
..
sequential successorn
branch target if taken
The sequential successor instruction are said to be in the branch
delay slots. These instructions are executed whether or not the
branch is taken.
In Practice, all machines that utilize delayed branching have
a single instruction delay slot.
The job of the compiler is to make the successor instructions
valid and useful instructions.
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Delayed Branch Example
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Delayed Branch-delay Slot Scheduling Strategies
The branch-delay slot instruction can be chosen from
three cases:
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Branch-delay Slot: Canceling Branches
In a canceling branch, a static compiler branch direction
prediction is included with the branch-delay slot
instruction.
When the branch goes as predicted, the instruction in the
branch delay slot is executed normally.
When the branch does not go as predicted the instruction
is turned into a no-op.
Canceling branches eliminate the conditions on
instruction selection in delay instruction strategies B, C
The effectiveness of this method depends on whether we
predict the branch correctly.
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DLX Performance Using Canceling Delay Branches
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Performance of Branch Schemes
The effective pipeline speedup with branch penalties:
(assuming an ideal pipeline CPI of 1)
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Pipeline Performance Example
Assume the following DLX instruction mix:
Type Frequency
Arith/Logic 40%
Load 30% of which 25% are followed immediately by
an instruction using the loaded value
Store 10%
branch 20% of which 45% are taken
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Pipelining and Handling of Exceptions
Exceptions are events that usually occur in normal program execution
where the normal execution order of the instructions is changed (often
called: interrupts, faults).
Types of exceptions include:
I/O device request
Invoking an operating system service
Tracing instruction execution
Breakpoint (programmer-requested interrupt).
Integer overflow or underflow
FP anomaly
Page fault (not in main memory)
Misaligned memory access
Memory protection violation
Undefined instruction
Hardware malfunctions
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Exception event IBM 360 VAX Motorola 680x0 Intel 80x86
I/O device request Input/output Device interrupt Exception (Level 0...7 Vectored interrupt
interruption autovector)
Invoking the operat- Supervisor call Exception (change Exception Interrupt
ing system service interruption mode supervisor (unimplemented (INT instruction)
from a user program trap) instruction)---
on Macintosh
Tracing instruction Not applicable Exception (trace Exception (trace) Interrupt (single-
execution fault) step trap)
Breakpoint Not applicable Exception (break- Exception (illegal Interrupt (break-
point fault) instruction or break- point trap)
point)
Integer arithmetic Program interrup- Exception (integer Exception Interrupt (overflow
overflow or under- tion (overflow or overflow trap or (floating-point trap or math unit
flow; FP trap underflow floating underflow coprocessor errors) exception)
exception) fault)
Page fault (not in Not applicable (only Exception (transla- Exception (memory- Interrupt
main memory) in 370) tion not valid fault) management unit (page fault)
errors)
Misaligned memory Program interrup- Not applicable Exception Not applicable
accesses tion (specification (address error)
exception)
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Handling of Resuming Exceptions
A resuming exception (e.g. a virtual memory page fault) usually
requires the intervention of the operating system.
The pipeline must be safely shut down and its state saved for
the execution to resume after the exception is handled as
follows:
1 Force a trap instruction into the pipeline on the next IF.
2 Turn of all writes for the faulting instruction and all
instructions in the pipeline. Place zeroes into pipeline latches
starting with the instruction that caused the fault to prevent
state changes.
3 The execution handling routine of the operating system
saves the PC of the faulting instruction and other state data
to be used to return from the exception.
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Exception Handling Issues
When using delayed branches ,as many PCs as the the
length of the branch delay plus one need to be saved and
restored to restore the state of the machine.
After the exception has been handled special instructions
are needed to return the machine to the state before the
exception occurred (RFE, Return to User code in DLX).
Precise exceptions imply that a pipeline is stopped so the
instructions just before the faulting instruction are
completed and and those after it can be restarted from
scratch.
Machines with arithmetic trap handlers and demand
paging must support precise exceptions.
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Exceptions in DLX
The following represent problem exceptions for the DLX
pipeline stages:
IF Page fault on instruction fetch; misaligned memory access;
memory-protection violation.
ID Undefined or illegal opcode
EX Arithmetic exception
MEM Page fault on data fetch; misaligned memory access;
memory-protection violation
WB None
Example: LW IF ID EX MEM WB
ADD IF ID EX MEM WB
can cause a data page fault and an arithmetic exception at the same
time ( LW in MEM and ADD in EX)
Handled by dealing with data page fault and then restarting execution,
then the second exception will occur but not the first.
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Precise Exception Handling in DLX
The instruction pipeline is required to handle exceptions of
instruction i before those of instruction i+1
The hardware posts all exceptions caused by an instruction
in a status vector associated with the instruction which is
carried along with the instruction as it goes through the
pipeline.
Once an exception indication is set in the vector, any control
signals that cause a data value write is turned off .
When an instruction enters WB the vector is checked, if any
exceptions are posted, they are handled in the order they
would be handled in an unpipelined machine.
Any action taken in earlier pipeline stages is invalid but
cannot change the state of the machine since writes where
disabled.
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