pornTS TO REMEMBER: «+ Boolean algebra works with binary variables, + A Boolean algebra is an algebraic system consisting of the set {0,1), ‘OR, AND, or NOT denoted by the symbols ——— —) operations called : + Boolean algebra enables the logic designer to simplify the circuit E economy of Construction and reli of oper . « Boolean algebra suggests the’ i (forward way 0 } circuitry used in any computer system. + Boolean algebra is unique in the way tha it tak Itdoes not have negative number. Itdoes not have fraction number. es only two different * The basic Boolean postulates: Logical Multiplications based on AND function. i 1. 00=0 2. 0.1=0 oe y Bs + 3. 10-0 a 21-1 Logical Additions based on OR function 0 a aa. based on NOT function. , vel19. = &yz 20. xHy+2)= (K+ yz pr Absorption laws: 21. xt+xy=x 22. x(x+y)=x 23. xtxy =x+y : 24. x(x'+y)=xy ‘ h) Demorgan’s laws. ; i 25. (x+y) =x.y } 26. (x.y = x+y’ * In Boolean algebra ‘1’ is called multiplicative identity and ‘0’ is called additive identity. * Literal: A primed or unprimed Boolean variable is called literal. Each variable can have maximum of two literals. Eg: x is a variable which can have two [i eer a 3 Proof for some important properties: « i 17. xtyz = (xty)(x+z) Oty\xtz) = xxtxztnyty.z a = xhatnytyz = x(14z)txytyz xtytyz = x(L4y) + yz xt ye* Logie Circuits can be b the following metho eae (@) Applying Boolean properties F (b) Kamaugh-map method. [of simplification ? (6) Tabulation method.” : > + The propenies of Boolean Algebra are useful fr the simplification of Boolean equation leading to minimal gate structure. a + Simplify the Boolean equation z = xy +x" +y). P xy + x(x ty) =xy tax t xy = xy XY =(xtxy=y. " + Duality Principle: The importint property of Boolean algebra is the duality principle, » mit atates that every algebraic expression deducible from theorems of Boolean algebra remains valid if the operators and identify elements are interchanged. Examples: ) xix =x by duality x1=1 by duality pees by duality xty=y by duality x= (y#z)=(xty) +2 by duality * The dual of the exclusive — OR is equal to its complement. * A simple procedure to find the complement of a function is to take the dual of the . function and complement cach literal. * Standard product or alminterm (m)} Consider two bins si set or almintern ler two binary variables x and y' ‘combined with an AND operation. Since each variable appears in direct faattorai its complement form there are four possible combinations. X' Y', X' Y, XY' and XY. Each of | these four AND terms is called a minterm or a standard product term. “YX Minterm —_(m) 0-0 beens 01 eV Som a XY. im ; Ta xy ms * {Standard sum gf bexterm (92) Tie bina aiden ag ‘operation we will get four possible combinations X + Y, X + ¥", Xie of these four OR terms i called a maxterm or w standard sum tetm,‘minterm for each rd Producto = canon of teen ‘may be ex?! A Bada OY aston Boolean ressed alg’ y of the variables which 920 + Y= SARE ard Sum of Product FON | function in Stanton nical form. you) tees roratSPOS) scaled STIS chard f mse Mca rth table by forming 8 ‘1 in the function, ically from a gi algebraically roduces then taking the OR of all those terms. 0 0 0 1 1 o i_7 * ction may be exp A Boole bination o| the maxterms for each com! function, and then taking the AND o ressed algebraically from a giv FOGY)= X¥+X'¥ = Ei This {the variables which produces zero f all those terms. + X/¥. ojo F a4 7 F=(X+ Y(X'+ Y= TTM(0,3). This representation is called SPOS form. (1,2). «representation is called SSOP form. fen truth table by forming *O’ in the * Sf one canonical form is given it is possible to express other canonical form. Example: The other canonical form of the equation F (X,Y,Z)= TI M(0,2,3,6) is FYZ)= Em(1,4,5,7). * Sum of all the minters of a given Boolean function is equal to 1. Example: (X,Y,Z) = £ m(0,1,2,3,4,5,6,7) = 1 jl * Product of all the maxterms of a given Boolean function is equal to 0. Example: F (X,Y,Z)= 11 M(0,1,2,3,4,5,6,7) = 0. * Boolean functions expressed as a sum of minterms or product of maxterms are said to be in canonical form. * Sum of products ffm can be implemented by using NAND-NAND realization, * NAND-NAND realization is same as AND-OR. * NOR-NOR realization is same as OR -AND. * Ifthe signals are propagating throu pate network. * Degenerative Form: A two level gate network is degenerates to a single operation Example: AND - AND is equivatent to AND Product of sums form can be implemented by using NOR-NOR realization, igh two stages of gates, then itis called two. level said to be degenerative if itNAND AND - ‘NOR - NAND NAND - NOR * A map is a diagram made up of squares. Each square represen 9 The number of squares in the Kamnaugh map is given by 2° w variable. 5 wo variable K-map consists of 4-clls or squares, Three variable K-map consists of 8-squares or 8 cells. — Four variable K-map consists of 16-squares or 16 cell: * To maintain adjacency property Gray code sequence is used in Ke adjacent cells will differ by only one bit). * Two variable K-map: Each cell represents a term of two literals. Grouping two adjacent (pair) squares contai ing 1"s represents Grouping four adjacent squares containing I's represent the fun Y oO 1 avi x o| xv | xy 1 * Three variable K-map: yz) Each cell represents a term of three literals, , Grouping two adjacent cells containing 1"s (Pair) represent a term of tw Grouping four adjacent cells containing 1's (Quad) represent a term of Grouping eight adjacent cells containing 1's represents the function =1. * Four variable K-ifap: n oe 00 Ol 1 10 ti To] Lif a ]2] otalSe ee © adjacent squares containing 1’s represents a term of three literals, * Grouping four adjacent squares conthining 1's représents a term of two literals. * Grouping eight adjacent squares containing I's represents a term of one literal. * Grouping sixteen adjacent squares containing 1's represent the function = 1. (aterm of zero literals). * Rules to simplify K-maps: 1-At the time of grouping the adjacent cells containing 1's alvvays use maximum possible group. 2. All the cells containing 1's must be covered atleast once in any group. 3. At the time of grouping don’t care.(X) values can be taken a5 1's. 4, All don’t care values need not be covered. * Tabulation method is used to simplify Boolean expressions when there are more than 5 variables. * In an n-variable K-map combining 8 adjacent cells containing 1's as a group will result a term octet and it result a term of (n 3) literals * Inan n-variable K-map combining 8 adjacent cells containing 1's as a group will eliminate 3 variables. SELF TE: 0A switching function f(A.B,C,D) = A’B'CD+A'BCD+A'BCD+AB'CD+AB'CD can also be written as Firch eleue 4 (@) Em (13,5,7,9) () 2m G,5,79,11) (©) Em G,5,9,11,13) (4) Em (5,7,9,11,13) \2/The switching function {(A,B,C,D) = Em (5,9,11,14) can be written as (3) A'B CC’ D+A B’C’D+A B' CD+ABCD' - Tee (b) (b) A'B'C'D+AB'C'D + A'B'CD + ABCD' ()A' BC D+ A’ BC'D'+ AB'C D'+ ABCD () None ue E pee fain (A,B,C) = (A+B'4C)(A'4B'+C)(A4B4C)) can also be written as 6) tb) Em (0,1,4,5,7) (c) Em (1,2,5,6,7 d) Im (0,2,4,6) 4 : sa AL Thetthes canonical form of {(A,B,C) = Dm (0,1,5,7) is (a) TIM 23.4.6) (0) 1M (2,4,6,8) (©) TIM (25,67) (@) TIM (1,8,5,2) variable switching function is expressed as the maxterms by product of fi ») then it ean also be expressed as the sum of minterms by -(b) TIM(1,2,4,7) N7, Given Boolean theorem AB¥A'C+BC = AB+A'C which of the following is true? (@) (A*B)(AC)B+C) = (A+BY AC) (b) AB+A' C+BC = AB+BC . (©) AB+A' CABC = (A¥B)(A'+C)(B+C) (@) (A+B)(A'+C)(BHC) = ABTA’ c 8. (A'+B'+Cy'is equal to F @) ABC!) ABC (c) AtB+C (4) ABYC’ 9% AB+A'C+BCis equivalent to @ AB+BC (b) AB+A'C (A'C+BC (d) ac 10. The dual of a Boolean theorem is obtained by (@) interchanging all zeros and ories only (b) changing all zeros to ones only (©) changing all ones to zeros only. 4) interchanging operators and identity elements 11. The SOP form of logical expression is most suitable for designing logic circuit using only (a) NOR gates {b) NAND gates (c) AND gates (d) X-OR gates 12. The POS form of logical expression is most suitable for designing logic cireuits using only (2) X-OR gates (b) AND gates (©)NAND gates (4) NOR gates “AT. The logic expression F = XY+XZ'+YZ is known as (2) SSOP form (b) SOP form (©) POS form (@) SPOS form NE The logic expression F = (x+y+z)(x+y')(y+2')(x+z) is known as (3) SOP form (b) SSOP form (©) SPOS form —_(d) POS form US. The logic expression F = E m (0,3,6,7,10,12,15) is equivalent to (a) F=11M(03,6,7,10,12,15) (b) F= 11MQ,2,4,5,8,9,11,13,14) (©) F=Em(0,1,5,6,7,12,15) (4) F= 5m (1,2,4,5,8,9,11,13,14) 46 In Boolean Algebra ‘1’ is called (a) Additive identity (b) Multiplicative identity (c) Eitherlor2 _(@) None M7 In Boolean Algebra 0’ is called (a) Additive identity _(b) Multiplicative identity () Both land2 (4) None * 18. A literal in Boolean algebra is a (2) Primed or unprimed Boolean variable (b) Primed Boolean (©) Unprimed Boolean variable only * (a) None 49 The Boolean expression x +x" is equal to ()x (b) xty “Oy @) 20. The Boolean expression (x+y)(x+z) is equal to - ayxte (b) xy| (stand © May Soum term or product term (None sd som of products form or standard product function expressed in standa (@ Both 1and2 —_(d) None | Boolean | of sums form is called ; {@) Canonical form —_(b) Conical form € 2 be realized by using —— logic : - TNAND-RAND form AND-OR (Either 102 (@)Nome e KEY FOR SELF-TEST =1.1 @b Qa Bb a @e Oc (ib (17a (18) 9 (19)b @0) © Ma ()b (yb (10) a @yb (24 @3)b (i4)d as) b Gna @b Qa GA)a Ae SELF TEST = 1.2 1. The dual of x+xy =x is (a) x47 (b)x (c) x(xty) =X (d) (xty)Gry) =x 2. The dual of the exclusive ~ OR gate is equal to 3 (a) NAND gate (b) X-OR gate (c) X-NOR gate (d) AND gate » Tentify the degenerative form from the following two level gate networks (@) AND-AND (b) OR-NOR (©)AND-NAND _(@) All the above 4. Identify the non-degenerative form from the following two level gate networ (2) AND-AND (b) NOR-AND (c)NAND-NOR —() NORNAND i; sil - 5. Boolean algebra can be used to (a) Simplify any algebraic expressions (b) Minimize the itches numb circuits (b) solve the mathematical problems (d) Perform arithmetic: call a, The valueof X © 0 is fa) Xx (bX ©) n'y theorems states that Band (AB)' © A'8' (bY (AYB)'= A "AB" and (AB)'= AWB (A) (A¥B) vt8. The logic expression A @Bissameas GAB+ABR ((ASBYAYD)_ (€)(ASBY(A'B) \9= The number of terms in a function of four variable are @4 8 (©)16 @i2 ~AA The minterm, designator of the term AB’ CD is @) 10 1 @iz (d) None ‘UT. The maxterm designator of the term A'+B'+C+D' is (@2 ©) 13 (© 10 @ is \2-The corresponds to decimal number 12 is @ ABCD \ (b) A#B+C'+D' * — (c) A'+B'+C+D @aA'BICD 70 J \J2-The mugterm corresponds to decimal number 14 is @) ABCD S pga O)AYBYCHD — @A'BIC'D (@) ABCD. ° NAN HHH HH Oe 14. The number of cells in a 6-variable K-map is @)6 (b) 12 (©) 36 (4) 64 15. The code used for labelling the cells of the K-map is (a) Natural BCD b) Hexadecimal ©) Gray (@) Octal 16. In K-map simplification, a group of cight adjacent ones leads to a term with {a) one literal less than the total number of variables (©) two literals less than the total number of variables (c) three literals less than the total number of variables (d) four literals less than the total number of variables 17, Minimization of logic expressions while designing digital systems helps in reducing (a) Cost (b) Space requirement (c) Power requirement (d) All of these 18: The Boolean expression X + X'Y = (a) X¥¥ (b) X+XY (© Y+¥Yx ; @xy 19.(X+¥)+Z=X+(¥+Z) (a) shows that the boolean operator OR is distributive (b) shows ¢hat the boolean operator OR is associative (c) implies the associativity of the boolean operator AND (d) none of the above. 20, The boolean expression AB + AB' + A'C+ AC is (A () B . Neh ls foliwing Boolean sgsing tatements | a + . C at C)=jllowing Boolean se a 7 () A+AB=B (c) (A+B) (A+C) =At+BC (@) none of these TEST 1.2 : [ Ole O2c% 03.4 04.b 05.4 06.b 07 e 082 O%c 1b Ikb Dis > dash) 14. 20.b aye 5 ie 16 17.4 18: 19.b . e mad Ba E & : © POINTS TO REMEMBER a4 * A gate isan electronic circuit with one output and one or more inputs, The output e always depends onthe input combinations = a * OR and NOT gates are called Basic gates. ] « «| NAND and NOR gates are called Univetsal gates) because by using only NAND gates 4 or by using only NOR gates we can sealize amy gate or any circuit, c * Special gates are Exclusive-OR gate an R gate.) ¢ +(Baclasive NOR OCNOR) pate is also called inclusive-OR or gate of equivalence. e * There are two types of logic systems: * ar € (a) Positive level logic system i (b) Negative level logic system € * Positive level logic system: Out of the given two voltage levels, the n € (PLLS) value is assumed as logic “1” and the « mielevel logic system: Out of the given two voltage levels, the more neg (NLLS) % ie assumed as logic ‘I’ and the other as lo; ‘Example: * AND gate : “The output of AND gate is high if all the inputs are high.” (or) “The output < Of AND gate is low if any one input is low or all the inputs are low.” Voc Truth Table B A ry en en”) es Y=AB B 0 . 1 -~en6 Internal Circuit diagram of AND gate with positive level logie system. * OR gate : “The output of an OR gate is high if any one input is high or all inputs archigh” (or) “The output of an OR gate is zero if all the inputs are zeros Internal Circuit‘ diagram of OR gate with positive level fogie system, Truth table A 0 0 1 I -c-9/” ¥ 0 1 1 1 * The ciccuit, which is working a5 AND gate with i OR gate with negative level logic system. a * The cirewit, which ¥always compliment of gate is Voc a Internal Circuit = “This is nothing but AND gate followed by NOT gate. “The output of NAND * NAND gate: gate is high if any one input or all inputs are low.” Truth table arte Sy A se ' veo] t B—_ aoe Y= AB = (AB) 1 {1 erst AND + NOT ao + NOR gate: ILis nothing but OR gate followed by NOT gate. “ The output of NOR gate is high ifall the inputs are-low.” (OR) “The output of NOR gate is low if any ‘one input is bigh or all inputs are high.” A o— = ees B Y= A+B=(A+B) B DR4 NoT * The circuit which is behaving as NAND gate with positive level logic system will behave as NOR gate with negative level logic system and vice ~ versa, * Exclusive-OR gate (X-OR) : “The output of an X-OR gate is high for odd number of high inputs... F Truth table A_B IY 0 0 |o A y= = AB MEAT caer oa A=)" — A@B = AB'+AB 2 1 11 fo ‘ * Exclusive-NOR gate (X-NOR) : Ibis X-OR followed b : (OR) : NOT, “The ourput is hij odd number of low inputs.” (OR) “The output is high kee noes oF gE aa* Realization of Basic gotes using NAND and NOR gates: | 1. NOT NAND gate ; A Y=A_ A—O “pey=(aay 1 ae Dan —— +0)" ee 5 at 2 A a A B — = AB A Y=AB B 3. OR Gate :D4Dy A yy 7Y a. B —{> Y=A4B Y=AtB * Realization of NAND gate using NOR gates: A A B Y=(ABY B * Realization of NOR gate using NAND gates:es ee r lize X- is four. + Thesninimum number of NAND gates required to realize X-OR gate is + Theminimum number of NOR gates required to realize X-OR gate is five. © Realization of X-NOR gate using NAND and NOR gates: o> Y=AB+A'B' pins bee gee + The minimum number of NAND gates required to realize X-NOR gate is 5. * The minimum number of NOR gates required to realize X-NOR gate is 4. * Altornate logic gate symbols:The alternate logic gate symbols for the standard gate symbols are obtain by interchanging AND and OR symbols, and by inverting all inputs and outputs. po) yeast ae : * A bubbled NAND gate is equivalent to OR gate s—_>- * A bubbled NOR gate is equivalent to AND gate. (A'B)'=A+B a ee B—_)-y=aB * A bubbled AND gate is equivalent to NOR gate, . As ' eset B)__P-y=asny = 14 AB =( sical 2—_ (A'+B)=AB * A bubbled OR gate is equivatent tq NAND gate tes $F Py atin 7The altemate logic gate symbols forthe standard gates are obtained based on Danmar Ian Tener too : ee PRUE Y= XGY s. XOX = 0 2 Keone . 6 XOY = YOX 3. XO1=x' 7. (xOY) = XY 4. XOX=1, , NAY The basic gates are————— E (@) AND, OR, NAND (b) AND,OR, NOR (©) AND, OR. NOT (@) NAND, NOR | 2) The output of a gate is | ifand only if all the input are high, what is that gate? (@) NOT (&) NAND (©) NOR (@) AND Sal 3) The output of the gate is I only for odd number of high inputs, what is that gate? (a) X-NOR (b) X-OR (c) NAND (d) NOR AF Identify the universal gate from the following gates (2) OR (b) AND (©) X-OR (4) NAND 5) The output of the gate is zero only when all the inputs are high, What is that gate? (a) AND (b) OR (c) NAND (d) NOR ©) The minimum number of NAND gates required to realize the X-OR gate are (a) 5 (b) 4 (c) 3 6 7) The output of a gate is Y=AB+ A’B” where A and B are inputs, what is that, (2) X-NOR (b) NAND (c) X-OR (d) all the 8) Identify the operation performed by the gate circuit shown in figure (@) AND (b) OR A 1 (c) NAND (d) NOR 2 Output of the given two voltage levels, if we choose more logic 1 and the other as logic 0,it is called as (2) positive logic level (b) negative logic level © 10) [densify the operation of the circuit inthe (3) AND. (b) OF