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Experiment - 8: Aim: To Design Alu Tools Used: Xilinx-Ise 8.2I, Modelsim Se Plus 6.2H VHDL Code

This document describes an experiment to design an arithmetic logic unit (ALU) using VHDL. It includes the VHDL code for an ALU entity with a 3-bit inputA, 3-bit inputB, 3-bit output, and 3-bit select line. The code uses a case statement to perform different operations on inputA and inputB depending on the value on the select line, including addition, subtraction, AND, OR, XOR, and NOT functions. It also mentions using Xilinx ISE and ModelSim tools to synthesize, implement a schematic, and simulate the ALU design.

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Anushka Chadha
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19 views3 pages

Experiment - 8: Aim: To Design Alu Tools Used: Xilinx-Ise 8.2I, Modelsim Se Plus 6.2H VHDL Code

This document describes an experiment to design an arithmetic logic unit (ALU) using VHDL. It includes the VHDL code for an ALU entity with a 3-bit inputA, 3-bit inputB, 3-bit output, and 3-bit select line. The code uses a case statement to perform different operations on inputA and inputB depending on the value on the select line, including addition, subtraction, AND, OR, XOR, and NOT functions. It also mentions using Xilinx ISE and ModelSim tools to synthesize, implement a schematic, and simulate the ALU design.

Uploaded by

Anushka Chadha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT 8

Aim: To design ALU

Tools used: Xilinx-ISE 8.2i,ModelSim SE PLUS 6.2h

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
port(
inputA,inputB:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
output:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0)
);
end ALU;

architecture alu of ALU is


begin
PROCESS(inputA,inputB,sel)
BEGIN
case sel is
when "000" => output<=inputA+inputB;
when "001" => output<=inputA-inputB;
when "010" => output<=inputA-1;
when "011" => output<=inputA+1;
when "100" => output<=inputA and inputB;
when "101" => output<=inputA or inputB;
when "110" => output<=not inputA;
when "111" => output<=inputA xor inputB;
when others => output<=NULL;
end case;
END PROCESS;
end alu;
Output :
Schematic

ISE Simulation
ModelSim Simualtion

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