2-1 Chapter 2: Data Representation

Principles of Computer Architecture

Miles Murdocca and Vincent Heuring

Chapter 2: Data Representation

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-2 Chapter 2: Data Representation

Chapter Contents
2.1 Introduction
2.2 Fixed Point Numbers
2.3 Floating Point Numbers
2.4 Case Study: Patriot Missile Defense Failure Caused by Loss of
Precision
2.5 Character Codes

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-3 Chapter 2: Data Representation

Fixed Point Numbers

Using only two digits of precision for signed base 10 numbers,
the range (interval between lowest and highest numbers) is
[-99, +99] and the precision (distance between successive num-
bers) is 1.
The maximum error, which is the difference between the value of a
real number and the closest representable number, is 1/2 the pre-
cision. For this case, the error is 1/2 1 = 0.5.
If we choose a = 70, b = 40, and c = -30, then a + (b + c) = 80 (which
is correct) but (a + b) + c = -30 which is incorrect. The problem is
that (a + b) is +110 for this example, which exceeds the range of
+99, and so only the rightmost two digits (+10) are retained in the
intermediate result. This is a problem that we need to keep in
mind when representing real numbers in a finite representation.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-4 Chapter 2: Data Representation

Weighted Position Code

The base, or radix of a number system defines the range of pos-
sible values that a digit may have: 0 9 for decimal; 0,1 for binary.
The general form for determining the decimal value of a number is
given by:

Example:
541.2510 = 5 102 + 4 101 + 1 100 + 2 10-1 + 5 10-2
= (500)10 + (40)10 + (1)10 + (2/10)10 + (5/100)10
= (541.25)10
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-5 Chapter 2: Data Representation

Base Conversion with the Remainder

Method
Example: Convert 23.37510 to base 2. Start by converting the inte-
ger portion:
Integer Remainder

23/2 = 11 R1 Least significant bit

11/2 = 5 R1

5/2 = 2 R1

2/2 = 1 R0

1/2 = 0 R1 Most significant bit

(23)10 = (10111)2

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-6 Chapter 2: Data Representation

Base Conversion with the Multiplica-

tion Method
Now, convert the fraction:

Most significant bit

.375 2 = 0.75

.75 2 = 1.5 0

.5 2 = 1.0 0
Least significant bit
(.375)10 = (.011)2

Putting it all together, 23.37510 = 10111.0112.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-7 Chapter 2: Data Representation

Nonterminating Base 2 Fraction

We cant always convert a terminating base 10 fraction into an
equivalent terminating base 2 fraction:
.2 2 = 0.4

.4 2 = 0.8

.8 2 = 1.6

.6 2 = 1.2

.2 2 = 0.4
.
.
.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-8 Chapter 2: Data Representation

Base 2, 8, 10, 16 Number Systems

Binary Octal Decimal Hexadecimal
(base 2) (base 8) (base 10) (base 16)
0 0 0 0
1 1 1 1
10 2 2 2
11 3 3 3
100 4 4 4
101 5 5 5
110 6 6 6
111 7 7 7
1000 10 8 8
1001 11 9 9
1010 12 10 A
1011 13 11 B
1100 14 12 C
1101 15 13 D
1110 16 14 E
1111 17 15 F

Example: Show a column for ternary (base 3). As an extension of

that, convert 1410 to base 3, using 3 as the divisor for the remain-
der method (instead of 2). Result is 1123
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-9 Chapter 2: Data Representation

More on Base Conversions

Converting among power-of-2 bases is particularly simple:
10112 = (102)(112) = 234
234 = (24)(34) = (102)(112) = 10112
1010102 = (1012)(0102) = 528
011011012 = (01102)(11012) = 6D16

How many bits should be used for each base 4, 8, etc., digit? For
base 2, in which 2 = 21, the exponent is 1 and so one bit is used
for each base 2 digit. For base 4, in which 4 = 22, the exponent is
2, so so two bits are used for each base 4 digit. Likewise, for base
8 and base 16, 8 = 23 and 16 = 24, and so 3 bits and 4 bits are used
for base 8 and base 16 digits, respectively.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-10 Chapter 2: Data Representation

Binary Addition
This simple binary addition example provides background for the
signed number representations to follow.

Carry in 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Operands
+ 0 + 1 + 0 + 1 + 0 + 1 + 0 + 1
0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

Example:
Carry Sum
out Carry 1 1 1 1 0 0 0 0
Addend: A 0 1 1 1 1 1 0 0 (124)10
Augend: B + 0 1 0 1 1 0 1 0 (90)10
Sum 1 1 0 1 0 1 1 0 (214)10
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-11 Chapter 2: Data Representation

Signed Fixed Point Numbers

For an 8-bit number, there are 28 = 256 possible bit patterns.
These bit patterns can represent negative numbers if we choose
to assign bit patterns to numbers in this way. We can assign half
of the bit patterns to negative numbers and half of the bit patterns
to positive numbers.
Four signed representations we will cover are:
Signed Magnitude
Ones Complement
Twos Complement
Excess (Biased)

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-12 Chapter 2: Data Representation

Signed Magnitude
Also know as sign and magnitude, the leftmost bit is the sign (0
= positive, 1 = negative) and the remaining bits are the magnitude.

Example:
+2510 = 000110012
-2510 = 100110012

Two representations for zero: +0 = 000000002, -0 = 100000002.

Largest number is +127, smallest number is -12710, using an 8-bit
representation.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-13 Chapter 2: Data Representation

Ones Complement
The leftmost bit is the sign (0 = positive, 1 = negative). Negative of
a number is obtained by subtracting each bit from 2 (essentially,
complementing each bit from 0 to 1 or from 1 to 0). This goes both
ways: converting positive numbers to negative numbers, and con-
verting negative numbers to positive numbers.

Example:
+2510 = 000110012
-2510 = 111001102

Two representations for zero: +0 = 000000002, -0 = 111111112.

Largest number is +12710, smallest number is -12710, using an 8-
bit representation.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-14 Chapter 2: Data Representation

Twos Complement
The leftmost bit is the sign (0 = positive, 1 = negative). Negative of
a number is obtained by adding 1 to the ones complement nega-
tive. This goes both ways, converting between positive and nega-
tive numbers.

Example (recall that -2510 in ones complement is 111001102):

+2510 = 000110012
-2510 = 111001112

One representation for zero: +0 = 000000002, -0 = 000000002.

Largest number is +12710, smallest number is -12810, using an 8-
bit representation.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-15 Chapter 2: Data Representation

Excess (Biased)
The leftmost bit is the sign (usually 1 = positive, 0 = negative).
Positive and negative representations of a number are obtained
by adding a bias to the twos complement representation. This
goes both ways, converting between positive and negative num-
bers. The effect is that numerically smaller numbers have smaller
bit patterns, simplifying comparisons for floating point exponents.

Example (excess 128 adds 128 to the twos complement ver-

sion, ignoring any carry out of the most significant bit) :
+1210 = 100011002
-1210 = 011101002

One representation for zero: +0 = 100000002, -0 = 100000002.

Largest number is +12710, smallest number is -12810, using an 8-
bit representation.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-16 Chapter 2: Data Representation

BCD Representations in Nines and

Tens Complement
Each binary coded decimal digit is composed of 4 bits.
(a) 0 0 0 0 0011 0000 0 0 0 1 (+301)10 Nines and tens
complement
(0)10 (3)10 (0)10 (1)10

(b) 1 0 0 1 0110 1001 1 0 0 0 (301)10 Nines complement

(9)10 (6)10 (9)10 (8)10

(c) 1 0 0 1 0110 1001 1 0 0 1 (301)10 Tens complement

(9)10 (6)10 (9)10 (9)10

Example: Represent +07910 in BCD: 0000 0111 1001

Example: Represent -07910 in BCD: 1001 0010 0001. This is ob-
tained by first subtracting each digit of 079 from 9 to obtain the
nines complement, so 999 - 079 = 920. Adding 1 produces the
tens complement: 920 + 1 = 921. Converting each base 10 digit of
921 to BCD produces 1001 0010 0001.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-17 Chapter 2: Data Representation

3-Bit Signed Integer Representations

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-18 Chapter 2: Data Representation

Base 10 Floating Point Numbers

Floating point numbers allow very large and very small numbers
to be represented using only a few digits, at the expense of preci-
sion. The precision is primarily determined by the number of dig-
its in the fraction (or significand, which has integer and fractional
parts), and the range is primarily determined by the number of
digits in the exponent.
Example (+6.023 1023):

Position of decimal point

+ 2 3 6 . 0 2 3

Sign Exponent Significand

(two digits) (four digits)

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-19 Chapter 2: Data Representation

Normalization
The base 10 number 254 can be represented in floating point form
as 254 100, or equivalently as:
25.4 101, or
2.54 102, or
.254 103, or
.0254 104, or
infinitely many other ways, which creates problems when making
comparisons, with so many representations of the same number.
Floating point numbers are usually normalized, in which the radix
point is located in only one possible position for a given number.
Usually, but not always, the normalized representation places the
radix point immediately to the left of the leftmost, nonzero digit in
the fraction, as in: .254 103.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-20 Chapter 2: Data Representation

Floating Point Example

Represent .254 103 in a normalized base 8 floating point format
with a sign bit, followed by a 3-bit excess 4 exponent, followed by
four base 8 digits.
Step #1: Convert to the target base.
.254 103 = 25410. Using the remainder method, we find that 25410
= 376 80:
254/8 = 31 R 6
31/8 = 3 R 7
3/8 = 0 R 3
Step #2: Normalize: 376 80 = .376 83.
Step #3: Fill in the bit fields, with a positive sign (sign bit = 0), an
exponent of 3 + 4 = 7 (excess 4), and 4-digit fraction = .3760:

0 111 . 011 111 110 000

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-21 Chapter 2: Data Representation

Error, Range, and Precision

In the previous example, we have the base b = 8, the number of
significant digits (not bits!) in the fraction s = 4, the largest expo-
nent value (not bit pattern) M = 3, and the smallest exponent value
m = -4.
In the previous example, there is no explicit representation of 0,
but there needs to be a special bit pattern reserved for 0 other-
wise there would be no way to represent 0 without violating the
normalization rule. We will assume a bit pattern of
0 000 000 000 000 000 represents 0.
Using b, s, M, and m, we would like to characterize this floating
point representation in terms of the largest positive representable
number, the smallest (nonzero) positive representable number,
the smallest gap between two successive numbers, the largest
gap between two successive numbers, and the total number of
numbers that can be represented.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-22 Chapter 2: Data Representation

Error, Range, and Precision (cont)

Largest representable number: bM (1 - b-s) = 83 (1 - 8-4)

Smallest representable number: bm b-1 = 8-4 - 1 = 8-5

Largest gap: bM b-s = 83 - 4 = 8-1

Smallest gap: bm b-s = 8-4 - 4= 8-8

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-23 Chapter 2: Data Representation

Error, Range, and Precision (cont)

A B C D E

2 ((M - m) + 1) (b - 1) bs-1 + 1

The number First digit Remaining

Sign bit of exponents of fraction digits of Zero
fraction
Number of representable numbers: There are 5 components: (A)
sign bit; for each number except 0 for this case, there is both a
positive and negative version; (B) (M - m) + 1 exponents; (C) b - 1
values for the first digit (0 is disallowed for the first normalized
digit); (D) bs-1 values for each of the s-1 remaining digits, plus (E)
a special representation for 0. For this example, the 5 components
result in: 2 ((3 - 4) + 1) (8 - 1) 84-1 + 1 numbers that can be
represented. Notice this number must be no greater than the num-
ber of possible bit patterns that can be generated, which is 216.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-24 Chapter 2: Data Representation

Example Floating Point Format

3 1 1 0 1 1 3
1 1
2 2 2 2
4 4
1 1 b = 2 M = +1
8 8 s = 3 m = 2
Smallest number is 1/8
Largest number is 7/4
Smallest gap is 1/32
Largest gap is 1/4
Number of representable numbers is 33.
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-25 Chapter 2: Data Representation

Gap Size Follows Exponent Size

The relative error is approximately the same for all numbers.
If we take the ratio of a large gap to a large number, and compare
that to the ratio of a small gap to a small number, then the ratios
are the same:

A large gap bMs bs 1

= =
A large number bM (1 bs) 1 bs bs1

A small gap bms bs 1

= =
A small number bm (1 bs) 1 bs bs1

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-26 Chapter 2: Data Representation

Conversion Example
Example: Convert (9.375 10-2)10 to base 2 scientific notation
Start by converting from base 10 floating point to base 10 fixed
point by moving the decimal point two positions to the left, which
corresponds to the -2 exponent: .09375.
Next, convert from base 10 fixed point to base 2 fixed point:
.09375 2 = 0.1875
.1875 2 = 0.375
.375 2 = 0.75
.75 2 = 1.5
.5 2 = 1.0
Thus, (.09375)10 = (.00011)2.
Finally, convert to normalized base 2 floating point:
.00011 = .00011 20 = 1.1 2-4
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-27 Chapter 2: Data Representation

IEEE-754 Floating Point Formats

32 bits

Single
8 bits 23 bits
precision
Exponent Fraction
Sign
(1 bit) 64 bits

Double
precision 11 bits 52 bits
Exponent Fraction

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-28 Chapter 2: Data Representation

IEEE-754 Examples
Value Bit Pattern
Sign Exponent Fraction
(a) +1.101 25 0 1000 0100 101 0000 0000 0000 0000 0000
(b) 1.01011 2126 1 0000 0001 010 1100 0000 0000 0000 0000
(c) +1.0 2127 0 1111 1110 000 0000 0000 0000 0000 0000
(d) +0 0 0000 0000 000 0000 0000 0000 0000 0000
(e) 0 1 0000 0000 000 0000 0000 0000 0000 0000
(f) + 0 1111 1111 000 0000 0000 0000 0000 0000
(g) +2128 0 0000 0000 010 0000 0000 0000 0000 0000
(h) +NaN 0 1111 1111 011 0111 0000 0000 0000 0000
(i) +2128 0 011 0111 1111 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-29 Chapter 2: Data Representation

IEEE-754 Conversion Example

Represent -12.62510 in single precision IEEE-754 format.
Step #1: Convert to target base. -12.62510 = -1100.1012
Step #2: Normalize. -1100.1012 = -1.1001012 23
Step #3: Fill in bit fields. Sign is negative, so sign bit is 1. Expo-
nent is in excess 127 (not excess 128!), so exponent is repre-
sented as the unsigned integer 3 + 127 = 130. Leading 1 of
significand is hidden, so final bit pattern is:

1 1000 0010 . 1001 0100 0000 0000 0000 000

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-30 Chapter 2: Data Representation

Effect of Loss of Precision

According to
the General Ac- Missile
counting Office outside of
of the U.S. Gov- Validation range gate
action
ernment, a loss
Range
of precision in Gate
converting 24- Area
Search action
bit integers into locates missile
somewhere
24-bit floating within beam
point numbers
was responsible Patriot
for the failure of Missile Radar
System
a Patriot anti-
missile battery.

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-31 Chapter 2: Data Representation

ASCII Character Code

ASCII is a 7-bit code, com-
00 NUL 10 DLE 20 SP 30 0 40 @ 50 P 60 ` 70 p
monly stored in 8-bit 01 SOH 11 DC1 21 ! 31 1 41 A 51 Q 61 a 71 q
02 STX 12 DC2 22 " 32 2 42 B 52 R 62 b 72 r
bytes. 03 ETX 13 DC3 23 # 33 3 43 C 53 S 63 c 73 s
04 EOT 14 DC4 24 $ 34 4 44 D 54 T 64 d 74 t
05 ENQ 15 NAK 25 % 35 5 45 E 55 U 65 e 75 u
A is at 4116. To convert 06 ACK 16 SYN 26 & 36 6 46 F 56 V 66 f 76 v
07 BEL 17 ETB 27 ' 37 7 47 G 57 W 67 g 77 w
upper case letters to 08 BS 18 CAN 28 ( 38 8 48 H 58 X 68 h 78 x
09 HT 19 EM 29 ) 39 9 49 I 59 Y 69 i 79 y
lower case letters, add 0A
0B
LF
VT
1A
1B
SUB
ESC
2A *
2B +
3A
3B
:
;
4A J
4B K
5A Z
5B [
6A j
6B k
7A z
7B {
2016. Thus a is at 4116 + 0C
0D
FF
CR
1C
1D
FS
GS
2C
2D -
3C
3D
<
=
4C L
4D M
5C \
5D ]
6C l
6D m
7C |
7D }
2016 = 6116. 0E
0F
SO
SI
1E
1F
RS
US
2E .
2F /
3E
3F
>
?
4E N
4F O
5E ^
5F _
6E n
6F o
7E ~
7F DEL

The character 5 at posi- NUL Null FF Form feed CAN Cancel

SOH Start of heading CR Carriage return EM End of medium
tion 3516 is different than STX
ETX
Start of text
End of text
SO
SI
Shift out
Shift in
SUB
ESC
Substitute
Escape
the number 5. To convert EOT
ENQ
End of transmission
Enquiry
DLE
DC1
Data link escape
Device control 1
FS
GS
File separator
Group separator
character-numbers into ACK
BEL
Acknowledge
Bell
DC2
DC3
Device control 2
Device control 3
RS
US
Record separator
Unit separator
number-numbers, sub- BS
HT
Backspace
Horizontal tab
DC4
NAK
Device control 4
Negative acknowledge
SP
DEL
Space
Delete
tract 3016: 3516 - 3016 = 5. LF
VT
Line feed
Vertical tab
SYN
ETB
Synchronous idle
End of transmission block

Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-32 Chapter 2: Data Representation

00 NUL 20 DS 40 SP 60 80 A0 C0 { E0 \

EBCDIC 01 SOH 21 SOS 41

02 STX 22 FS
03 ETX 23
42
43
61
62
63
/ 81 a
82 b
83 c
A1
A2
A3
~
s
t
C1
C2
C3
A
B
C
E1
E2
E3
S
T

Character 04 PF
05 HT
06 LC
24 BYP 44
25 LF
26 ETB 46
45
64
65
66
84 d
85 e
86 f
A4
A5
A6
u
v
w
C4
C5
C6
D
E
F
E4
E5
E6
U
V
W

Code 07 DEL 27 ESC 47

08
09
28
29
48
49
67
68
69
87 g
88 h
89 i
A7
A8
A9
x
y
z
C7
C8
C9
G
H
I
E7
E8
E9
X
Y
Z
0A SMM 2A SM 4A 6A 8A AA CA EA
EBCDIC is an 8-bit 0B VT 2B CU2 4B 6B , 8B AB CB EB
0C FF 2C 4C < 6C % 8C AC CC EC
code. 0D CR 2D ENQ 4D ( 6D _ 8D AD CD ED
0E SO 2E ACK 4E + 6E > 8E AE CE EE
0F SI 2F BEL 4F | 6F ? 8F AF CF EF
10 DLE 30 50 & 70 90 B0 D0 } F0 0
11 DC1 31 51 71 91 j B1 D1 J F1 1
12 DC2 32 SYN 52 72 92 k B2 D2 K F2 2
13 TM 33 53 73 93 l B3 D3 L F3 3
14 RES 34 PN 54 74 94 m B4 D4 M F4 4
STX Start of text RS Reader Stop DC1 Device Control 1 BEL Bell
DLE Data Link Escape PF Punch Off DC2 Device Control 2 SP 55
15 NL 35 RS Space 75 95 n B5 D5 N F5 5
BS Backspace DS Digit Select DC416Device
BS Control
36 4UCIL 56Idle 76 96 o B6 D6 O F6 6
ACK Acknowledge PN Punch On CU1 Customer Use 1 NUL Null
SOH Start of Heading SM Set Mode CU217Customer
IL 37 2 EOT 57
Use 77 97 p B7 D7 P F7 7
ENQ Enquiry LC Lower Case CU318Customer
CAN Use 38 3 58 78 98 q B8 D8 Q F8 8
ESC Escape CC Cursor Control SYN Synchronous Idle
BYP Bypass CR Carriage Return IFS 19Interchange
EM 39 File Separator59 79 99 r B9 D9 R F9 9
CAN Cancel EM End of Medium EOT End of Transmission
RES Restore FF Form Feed ETB1A CC
End 3A
of Transmission 5A !
Block 7A : 9A BA DA FA |
SI Shift In TM Tape Mark NAK 1BNegative
CU1 Acknowledge
3B CU3 5B $ 7B # 9B BB DB FB
SO Shift Out UC Upper Case SMM Start of Manual Message
DEL Delete FS Field Separator SOS1CStart
IFS 3C DC4 5C .
of Significance 7C @ 9C BC DC FC
SUB Substitute HT Horizontal Tab IGS 1DInterchange
IGS 3D NAK
Group 5D )
Separator 7D ' 9D BD DD FD
NL New Line VT Vertical Tab IRS Interchange Record Separator
LF Line Feed UC Upper Case IUS1EInterchange
IRS 3E 5E ;
Unit Separator 7E = 9E BE DE FE
1F IUS 3F SUB 5F 7F " 9F BF DF FF
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring
 2-33 Chapter 2: Data Representation
0000 NUL 0020 SP 0040 @ 0060 ` 0080 Ctrl 00A0 NBS 00C0 00E0
0001 SOH 0021 ! 0041 A 0061 a 0081 Ctrl 00A1 00C1 00E1
0002 STX 0022 " 0042 B 0062 b 0082 Ctrl 00A2 00C2 00E2

Unicode
0003 ETX 0023 # 0043 C 0063 c 0083 Ctrl 00A3 00C3 00E3
0004 EOT 0024 $ 0044 D 0064 d 0084 Ctrl 00A4 00C4 00E4
0005 ENQ 0025 % 0045 E 0065 e 0085 Ctrl 00A5 00C5 00E5
0006 ACK 0026 & 0046 F 0066 f 0086 Ctrl 00A6 00C6 00E6

Character 0007 BEL

0008 BS
0009 HT
0027
0028 (
0029 )
' 0047
0048
0049
G
H
I
0067 g
0068 h
0069 i
0087 Ctrl
0088 Ctrl
0089 Ctrl
00A7
00A8
00A9
00C7
00C8
00C9



00E7
00E8
00E9



000A LF 002A * 004A J 006A j 008A Ctrl 00AA a 00CA 00EA

Code 000B VT
000C FF
000D CR
002B +
002C
002D -
004B
004C
004D
K
L
M
006B k
006C l
006D m
008B Ctrl
008C Ctrl
008D Ctrl
00AB
00AC
00AD
00CB
00CC
00CD



00EB
00EC
00ED



000E SO 002E . 004E N 006E n 008E Ctrl 00AE 00CE 00EE
000F SI 002F / 004F O 006F o 008F Ctrl 00AF 00CF 00EF
0010 DLE 0030 0 0050 P 0070 p 0090 Ctrl 00B0 00D0 D 00F0
0011 DC1 0031 1 0051 Q 0071 q 0091 Ctrl 00B1 00D1 00F1
0012 DC2 0032 2 0052 R 0072 r 0092 Ctrl 00B2 2 00D2 00F2
0013 DC3 0033 3 0053 S 0073 s 0093 Ctrl 00B3 3 00D3 00F3
0014 DC4 0034 4 0054 T 0074 t 0094 Ctrl 00B4 00D4 00F4
0015 NAK 0035 5 0055 U 0075 u 0095 Ctrl 00B5 00D5 00F5
Unicode is a 16- 0016 SYN
0017 ETB
0036 6
0037 7
0056
0057
V
W
0076 v
0077 w
0096 Ctrl
0097 Ctrl
00B6
00B7
00D6
00D7


00F6
00F7


bit code. 0018 CAN
0019 EM
0038 8
0039 9
0058
0059
X
Y
0078 x
0079 y
0098 Ctrl
0099 Ctrl
00B8
00B9 1
00D8
00D9


00F8
00F9


001A SUB 003A : 005A Z 007A z 009A Ctrl 00BA o 00DA 00FA
001B ESC 003B ; 005B [ 007B { 009B Ctrl 00BB 00DB 00FB
001C FS 003C < 005C \ 007C | 009C Ctrl 00BC 1/4 00DC 00FC
P
001D GS 003D = 005D ] 007D } 009D Ctrl 00BD 1/2 00DD Y 00FD P
001E RS 003E > 005E ^ 007E ~ 009E Ctrl 00BE 3/4 00DE y 00FE pp
001F US 003F ? 005F _ 007F DEL 009F Ctrl 00BF 00DF 00FF
NUL Null SOH Start of heading CAN Cancel SP Space
STX Start of text EOT End of transmission EM End of medium DEL Delete
ETX End of text DC1 Device control 1 SUB Substitute Ctrl Control
ENQ Enquiry DC2 Device control 2 ESC Escape FF Form feed
ACK Acknowledge DC3 Device control 3 FS File separator CR Carriage return
BEL Bell DC4 Device control 4 GS Group separator SO Shift out
BS Backspace NAK Negative acknowledge RS Record separator SI Shift in
HT Horizontal tab NBS Non-breaking space US Unit separator DLE Data link escape
LF Line feed ETB End of transmission block SYN Synchronous idle VT Vertical tab
Principles of Computer Architecture by M. Murdocca and V. Heuring 1999 M. Murdocca and V. Heuring