Department Of ECE ECAD and VLSI Lab Manual

WEEK
PROGRAM CATEGORY TOPIC
NO
1.1 Design of Logic Gates using Data Flow Model
1.2 Design of Logic Gates using Behavioral Model
1.3 Design of Logic Gates using Structural Model
BASIC LOGIC GATES
1.4 Design of Logic Gates (3-input)using Behavioral
Model
1 1.5 Design of Logic Gates (3-input)using Data
Flow Model
2.1 Design of 2-to-4 Decoder with Behavioral
Model
2.2 Design of 2-to-4 Decoder with If Else
Statements
2.3 Design of 2-to-4 Decoder with Dataflow
Model
DECODER 2.4 Design of 3-to-8 Decoder with Structural
2
Model
2.5 Design of 3-to-8 Decoder with Behavioral
Model
3.1 Design of 8-to-3 Encoder Behavioral model
3.2 Design of 8-to-3 Encoder With Conditional
Statement
ENCODER 3.3 Design of 8-to-3 Encoder using Case statements
3.4 Design of 8-to-3 Encoder using With Parity Bit

3 3.5 Design of 4-to-2 Encoder using With Out Parity

Bit
4.1 Design of 8 to 1 Multiplexer
4.2 Design of 1 to 8 De-multiplexer
4.3 Design of 4 to 1 multiplexer using logical
4 MULTIPLEXER AND expressions
DEMULTIPLEXER 4.4 Design of 4 to 1 multiplexer in Dataflow
Model
4.5 Design of 4 to 1 multiplexer in Structural
model
5.1 Design of 4 BIT Binary to Gray conversion
5.2 Design of 4 BIT Binary to Gray conversion
using Always Statement

5.3 Design of 4 BIT Binary to Gray conversion

using structural model
BINARY TO GRAY 5.4 Design of BCD to 7 segment code Converter
CONVERSION using Behavioral model
5. 5.5 Design of BCD to 7 segment code Converter
using Conditional operator

MLR Institute of Technology 1

Department Of ECE ECAD and VLSI Lab Manual

6.1 Design of 4 bit Comparator

6.2 Design of 1 bit Comparator using Dataflow
model
6.3 Design of 2 bit Comparator using dataflow
COMPARATOR model
6. 6.4 Design of 4 bit Comparator using behavioral
model
6.5 Design of 4 bit Comparator using structural
model
7.1 Design of Full Adder Data flow
7.2 Design of Full adder Behavioral Model
FULL ADDER 7.3 Design of Full adder with Structural Model
7.4 Design of Full adder Procedural Model
7 7.5Design of Full adder using Two Half Adders
8.1 Design of SR Flip Flop
8.2 Design of D Flip Flop
8.3 Design of JK Flip Flop
FLIP FLOPS 8.4 Design of T Flip Flop
8.5 Design a Synchronous positive Edge JK Flip
8 flop

MLR Institute of Technology 2

Department Of ECE ECAD and VLSI Lab Manual

Logic Gates Introduction

Logic Gate Symbols:

Fig 1.1: Logic Gate symbols

MLR Institute of Technology 3

Department Of ECE ECAD and VLSI Lab Manual

Table 1: Logic gates representation using Truth Table

Theory:

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT,
NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid
of truth tables.

AND GATE:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot
(.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

OR GATE:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.

NOT GATE:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is
also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two
ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using
NOR logic gates in the same way.

NAND GATE:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all
NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on
the output. The small circle represents inversion

NOR GATE:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR
gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

MLR Institute of Technology 4

Department Of ECE ECAD and VLSI Lab Manual

EXOR GATE:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign is used to show the EOR operation.

EXNOR GATE:

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output ifeither,
but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output.
The small circle represents inversion.

The NAND and NOR gates are called universal functions since with either one the AND and OR
functions and NOT can be generated.

Note:

A function in sum of products form can be implemented using NAND gates by replacing all AND and
OR gates by NAND gates.

A neither function in product of sums form can be implemented using NOR gates by replacing all AND
and OR gates by NOR gates.

MLR Institute of Technology 5

Department Of ECE ECAD and VLSI Lab Manual

Procedural Steps:
The following procedure will guide you to develop a Xilinx ISE project.

a. Create a New Project:

The first step of any design in ISE is to create a new ISE project. In each ISE project, the target FPGA
device needs to be defined. Although this laboratory work does not require hardware, you are suggested
to create a new ISE project which targets at the FPGA device on the Spartan-3 Startup Kit by following
the steps below:
1. Open the Project Navigator of Xilinx software.
2. Select File New Project The New Project Wizard appears.
3. Type Logic gates in the Project Name field.
4. Enter or browse to a location of your choice for the new project. A Logic gates subdirectory is
created automatically.
5. Verify that HDL is selected from the Top-Level Source Type list.
6. Click Next to move to the device properties page.
7. Fill in the properties in the table as shown below:

Fig 1.2 (a): Device Properties

8. Say Next for 3 times, then click on Finish. When you find new project result, project summary,
click finish.
9. Click Next to proceed to the Create New Source window in the New Project Wizard. Then
proceed to Section b.

MLR Institute of Technology 6

Department Of ECE ECAD and VLSI Lab Manual

b. Create a new HDL Source:

In this section, you will create the top-level HDL file for your design.
Create a VHDL source file for the project
1. Click the New Source button in the New Project Wizard.
2. Select Verilog Module as the source type.
3. Type in the file name.

Fig 1.2 (b): New Source Wizard

4. Verify that the Add to project checkbox is selected.

5. Click Next.
6. Declare the ports for the lgates design that you are going to make by filling in the port
information as below:

MLR Institute of Technology 7

Department Of ECE ECAD and VLSI Lab Manual

Fig 1.2 (c): Port Information

7. Write Verilog code in HDL edition and save.

MLR Institute of Technology 8

Department Of ECE ECAD and VLSI Lab Manual

Fig 1.2 (d): VHDL Code in Xilinx

c. Check Syntax:
1. In process window go to sources for window and select behavioral simulaation.

Fig 1.2 (e): VHDL Code check syntax

d. To Create Test Bench Wave form:

1. For this right click on create a new source in process window and select .

Fig 1.2 (e): Continued

MLR Institute of Technology 9

Department Of ECE ECAD and VLSI Lab Manual

Fig 1.2(f): Different File name

Fig 1.2 (g): Test bench waveform

2. Select the desired parameters for simulating your design and click ok.
3. Assign all the signals to test bench wave form and save the file.

Fig 1.2(g): Continued

e. Simulation Process:
1. In source window from the dropdown menu select behavioral simulation to see the created
test bench file.
2. Select the test bench file from the source process window, click Xilinx ISE simulator. Now
double click simulate behavioral module.

Precautions
MLR Institute of Technology 10
Department Of ECE ECAD and VLSI Lab Manual

Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

MLR Institute of Technology 11

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 1
1.1 Logic Gates Data Flow Model
Aim: Write a verilog program to simulate and verify All Logic Gates using Data Flow Model.

Software: Xilinx 9.2i.

Program:
module allgates(a, b, c);
input a;
input b;
output [6:0] c;
assign c[0]= a & b;
assign c[1]= a | b;
assign c[2]= ~(a & b);
assign c[3]= ~(a | b);
assign c[4]= a ^ b;
assign c[5]= ~(a ^ b);
assign c[6]= ~ a;
endmodule

Simulation Waveform:

Result: The verilog Program for all logic gates by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 12

Department Of ECE ECAD and VLSI Lab Manual

1.2 Logic Gates Using Behavioral Model

Aim: Write a verilog program to simulate and verify the All Logic Gates using Behavioral Model
Software: Xilinx 9.2i.
Program:
Moudle allgates(a,b,not1,or2,and3,nor4,nand5,xor6,xnor7);
Input a;
Input b;
Output nor1;
Output or2;
Output and3;
Output nor4;
Output nand5;
Output xor6;
Output xnor7;
Reg nor1;
Reg or2;
Reg and3;
Reg nor4;
Reg nand5;
Reg xor6;
Reg xnor7;
always@(a or b)
begin
not1 = ~a;
or2 =alb;
and3 = a@b;
nor4 = ~(alb);
nand5 ~(a&b);
xor6 = (a^b);
xnor = ~(a^b);
end
endmoudle

Simulation Waveform:

Result: The verilog Program for all logic gates by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 13

Department Of ECE ECAD and VLSI Lab Manual

1.3 Nand Logic Gate Using Structural Model

Aim: Write a verilog program to simulate and verify the Nand Gate using Structural Model

Software: Xilinx 9.2i.

Algorithm:
module nand1(c,a,b);
output c;
input a,b;
wire d;
and1 u1(d,a,b);
inv u2(c,d);
endmodule

Simulation Waveform:

Result: The verilog Program for Nand logic gates by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 14

Department Of ECE ECAD and VLSI Lab Manual

1.4Nor Logic Gate using Structural Model

Aim: Write a verilog program to simulate and verify the Nor Gate using Structural Model

Software: Xilinx 9.2i.

Program:
module nor1(c,a,b);
output c;
input a,b;
wire d;
or1 u1(d,a,b);
inv u2(c,d);
endmodule

-- program for xor1

module xor1(c,a,b);
output c;
input a,b;
wire d,e,f,g;
inv u1(d,a);
inv u2(e,b);
and1 u3(f,a,e);
and1 u4(g,b,d);
or1 u5(c,f,g);
endmodule

Simulation Waveform:

Result: The verilog Program for NOR logic gates by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 15

Department Of ECE ECAD and VLSI Lab Manual

1.5 XNOR Logic Gate using Structural Model

Aim: Write a verilog program to simulate and verify the XNOR Gate using Structural Model

Software : Xilinx 9.2i.

Program:
module xnor_gate(X, A, B);
output X;
input A;
input B;

xnor(X, A, B);

endmodule

Simulation Waveform:

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Viva Questions:
1. What are universal gates?
2. What are special purpose gates?
3. Design XOR gate using NAND gates?
4. How many NOR gates required to design NAND gate?
5. Which gates follows commutative and associative law

Result: The verilog Program for XOR logic gates by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 16

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 2
2.1 Design of 2-to-4 Decoder using Behavioral Model

Aim: Write a verilog program to simulate and verify the 2 to 4 Decoder using Behavioral Model

Software:

Xilinx 9.2i.

Block Diagram:

Fig 2.1: Block Diagram of 2 to 4 decoder

Truth Table:

Fig 2.2: Logic gates representation using Truth Table

Theory:

Decoders :

A decoder is a combinational circuit that converts coded inputs to another coded outputs. The famous
examples of decoders are binary n-to-2n decoders and seven-segment decoders. A binary decoder has
n inputs and a maximum of 2n outputs. As we know, an n-bit binary number provides 2n minterms or
maxterms. This type of decoder produces one of the 2n minterms or maxterms at the outputs based on
the input combinations.

Lets take the 2-to-4 decoder as an example, the block diagram and the truth table of this decoder is
shown in Figure 2.1
MLR Institute of Technology 17
Department Of ECE ECAD and VLSI Lab Manual

From the truth table, you can observe the basic operation of n-to-2n decoders, there is only one active
output ( minterm ) for each input combination. The Boolean expression of the output signals are :
D0 = E x' y',
D1= E x' y,
D2 = E x y' and
D3= E x y
Now, the logic diagram for the 2-to-4 decoder can obtained as shown in Figure 2.2.

Fig 2.3: Internal Circuit Diagram of 2 to 4 decoder

In the same way, we can obtained the logic diagram for any n-to-2n type decoder. The commercially
available decoders are normally built using NAND gates instead of using AND gates because they are
easy and less expensive to build. An example of a commercial n-to-2n line decoder is the 74139 chip.
This chip has two 2-to-4 decoders with active low enable for each , They constructed using the NAND
gates (see its pinout diagram and Function Table )

Because any Boolean function can be expressed as a sum of products (minterms) or a

product of sums (maxterms), we can use a decoder to implement any Boolean function.

MLR Institute of Technology 18

Department Of ECE ECAD and VLSI Lab Manual

Program

module decoder_2x4(
input [1:0] a,
output reg [3:0] y);
always@(a)
case(a)
2'b00: y= 4'b0001;
2'b01: y= 4'b0010;
2'b10: y= 4'b0100;
2'b11: y= 4'b1000;
endcase
endmodule

Simulation Waveform:

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Viva Questions:
1. Which gates are used to implement active high decoder and active low decoders?
2. Design half adder using 2 to 4 Decoder.
3. Design half subtractor using 2 to 4 Decoder.
4. What are the uses of decoder?
5. What are the applications of decoder?

Result: The verilog Program for 2-to-4 decoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 19

Department Of ECE ECAD and VLSI Lab Manual

2.2 Design of 2-to-4 Decoder using If Else Statements

Aim: Write a verilog program to simulate and verify the 2 to 4 Decoder using If Else Statements

Program

Module decoder2to4(sel,en,y);
Input [1:0] sel;
Input en;
output [3:0]y;
reg [3:0] y;
always @ (sel,en)
begin
if(en==0)
y=4b1111;
else
if (sel == 2b00)
y=4b1110;
else if (sel == 2b01)
y=4b1101;
else if (sel == 2b10)
y=4b1011;
else
y=4b0111;
end
endmoudle

Simulated waveform:

Result: The verilog Program for 2-to-4 decoder by using Xilinx 9.2i Software is Simulated and verified
successfully
MLR Institute of Technology 20
Department Of ECE ECAD and VLSI Lab Manual

2.3 Design of 2-to-4 Decoder using Dataflow Model

Aim: Write a verilog program to simulate and verify the 2 to 4 Decoder using Dataflow Model

Progarm

module decoder2_4 ( a ,b ,w ,x ,y ,z );
output w ;
output x ;
output y ;
output z ;
input a ;
input b ;
assign w = (~a) & (~b);
assign x = (~a) & b;
assign y = a & (~b);
assign z = a & b;
endmodule

Simulated waveform:

Output Waveform for 2 : 4 Decoder

Result: The verilog Program for 2-to-4 decoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 21

Department Of ECE ECAD and VLSI Lab Manual

2.4 Design of 3-to-8 Decoder using structural Model

Aim: Write a verilog program to simulate and verify the 3 to 8 Decoder using Structural Model

Program

module decoder( D, A, B, enable );

output [0:3] D;
input A, B;
input enable;
wire Anot, Bnot, enableNot;
not
G1 (Anot, A),
G2 (Bnot, B),
G3 (enableNot, enable);
nand
G4 (D[0], Anot, Bnot, enableNot ),
G5 (D[1], Anot, B, enableNot ),
G6 (D[2], A, Bnot, enableNot ),
G7 (D[3], A, B, enableNot );
Endmodule

Simulated waveform:

Result: The verilog Program for 3-to-8 decoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 22

Department Of ECE ECAD and VLSI Lab Manual

2.5 Design of 3-to-8 Decoder using Behavioral Model

Aim: Write a verilog program to simulate and verify the 3 to 8 Decoder using Behavioral Model

Program

module decoder(
input [1:0] a,
output reg [3:0] y
);
always@(a)
case(a)
2'b00: y= 4'b0001;
2'b01: y= 4'b0010;
2'b10: y= 4'b0100;
2'b11: y= 4'b1000;
endcase
endmodule

Simulated waveform:

Result: The verilog Program for 3-to-8 decoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 23

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 3

3.1 Design of 8-to-3 Encoder using Behavioral Model

Aim: Write a verilog program to simulate and verify the 8 to 3 encoder using Behaveriol Model

Software:
Xilinx 9.2i.

Block Diagram:

Fig 3.1: Block Diagram of 8 to 3 encoder without Priority

Truth Table:

Fig 3.2: Truth Table of octal to binary encoder

Logic Diagram:

Fig 3 3: Logic Diagram of octal to binary encoder

MLR Institute of Technology 24

Department Of ECE ECAD and VLSI Lab Manual

Theory:

Encoder :

An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization, speed,
secrecy, security, or saving space by shrinking size. Encoders are combinational logic circuits and they
are exactly opposite of decoders. They accept one or more inputs and generate a multibit output code.

Encoders perform exactly reverse operation than decoder. An encoder has M input and N output lines.
Out of M input lines only one is activated at a time and produces equivalent code on output N lines. If a
device output code has fewer bits than the input code has, the device is usually called an encoder.

Octal to binary encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8
decoder does. At any one time, only one input line has a value of 1. The figure below shows the truth
table of an Octal-to-binary encoder.

Fig 3.4: Truth Table of octal to binary encoder (Without Priority)

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:

Y0 = I1 + I3 + I5 + I7

Y1= I2 + I3 + I6 + I7

Y2 = I4 + I5 + I6 +I7

MLR Institute of Technology 25

Department Of ECE ECAD and VLSI Lab Manual

Program:
module encoder_8x3(
input [7:0] a,
output reg [2:0] y);

always @(a)
begin
if (a==8'b00000001) y=3'b000;
else if (a==8'b00000010) y=3'b001;
else if (a==8'b00000100) y=3'b010;
else if (a==8'b00001000) y=3'b011;
else if (a==8'b00010000) y=3'b100;
else if (a==8'b00100000) y=3'b101;
else if (a==8'b01000000) y=3'b110;
else if (a==8'b10000000) y=3'b111;
else y=3'bX;
end
endmodule

Simulation Waveform:

Result: The verilog Program for 8-to-3 encoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 26

Department Of ECE ECAD and VLSI Lab Manual

3.2 Design of 8-to-3 Encoder using conditional operator

Aim: Write a verilog program to simulate and verify the 8 to 3 encoder using conditional operator

Software:

Xilinx 9.1i.

Block Diagram:

Fig 3 5: Block Diagram of 8 to 3 encoder without Priority

Truth Table:

Digital Inputs Binary Output

D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

Fig 3.6: Truth Table of 8 to 3 encoder (With Priority)

Theory:

Priority encoder:

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the ordinal number
starting from zero of the most significant input bit. They are often used to control interrupt requests by
acting on the highest priority request. It includes priority function. If 2 or more inputs are equal to 1 at
the same time, the input having the highest priority will take precedence. Internal hardware will check
this condition and priority is set.

Priority encoders are available in standard IC form and the TTL 74LS148 is an 8-to-3 bit priority
encoder which has eight active LOW (logic "0") inputs and provides a 3-bit code of the highest ranked
MLR Institute of Technology 27
Department Of ECE ECAD and VLSI Lab Manual

input at its output. Priority encoders output the highest order input first for example, if input lines "D2",
"D3" and "D5" are applied simultaneously the output code would be for input "D5" ("101") as this has
the highest order out of the 3 inputs. Once input "D5" had been removed the next highest output code
would be for input "D3" ("011"), and so on.

Program:

module parity_encoder ( din ,dout );

output [2:0] dout ;

wire [2:0] dout ;

input [7:0] din ;

wire [7:0] din ;

assign dout = din[7] ? 0 :

din[6] ? 1 :
din[5] ? 2 :
din[4] ? 3 :
din[3] ? 4 :
din[2] ? 5 :
din[1] ? 6 :
din[0] ? 7 : 1'bzzz

Simulation Waveform:

Result: The verilog Program for 8-to-3 encoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 28

Department Of ECE ECAD and VLSI Lab Manual

Viva Questions:
1. Which gates are used to 8X3 encoder?
2. What are the uses of encoder?
3. What is the difference between encoder with priority and with priority?
4. Which IC is used for encoder?
5. Which Of the following encode used for many code conversions?
(a) Octal to binary (b) Decimal to BCD (C) Hex to binary

MLR Institute of Technology 29

Department Of ECE ECAD and VLSI Lab Manual

3.2 Design of 8-to-3 Encoder using case statement

Aim: Write a verilog program to simulate and verify the 8 to 3 encoder using case statement

Program

module encoder_8_to_3(

input [7:0] i,
output reg [2:0] out
);
always@(*)
begin
case(i)
8'b00000001: out <= 3'b000;
8'b00000010: out <= 3'b001;
8'b00000100: out <= 3'b010;
8'b00001000: out <= 3'b011;
8'b00010000: out <= 3'b100;
8'b00100000: out <= 3'b101;
8'b01000000: out <= 3'b110;
8'b10000000: out <= 3'b111;
default: out<= 3'bxxx;
endcase
end
endmodule

Simulated waveform:

Result: The verilog Program for 8-to-3 encoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 30

Department Of ECE ECAD and VLSI Lab Manual

3.3 Design of 8-to-3 Encoder using parity bit

Aim: Write a verilog program to simulate and verify the 8 to 3 encoder using with parity bit

Program

module priority_encoder (code, valid_data, data);

output [2:0] code;
output valid data;
input [7:0] data;
reg [2:0] code;

assign valid_data= |data; // Use of "reduction or" operator

always @ (data)
begin
if(data[7]) code=7; else
if(data[6]) code=6; else
if(data[5]) code=5; else
if(data[4]) code=4; else
if(data[3]) code=3; else
if(data[2]) code=2; else
if(data[1]) code=1; else
if(data[0]) code=0; else
code=3'bx;
end
endmodule

Simulated wave form:

Result: The verilog Program for 8-to-3 encoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 31

Department Of ECE ECAD and VLSI Lab Manual

3.4 Design of 8-to-3 Encoder using without parity bit

Aim: Write a verilog program to simulate and verify the 8 to 3 encoder using without parity bit

Program

module encoder8x3(
input [7:0] a,
output reg [2:0] y
);
always @(a)
begin
if (a==8'b00000001) y=3'b000;
else if (a==8'b00000010) y=3'b001;
else if (a==8'b00000100) y=3'b010;
else if (a==8'b00001000) y=3'b011;
else if (a==8'b00010000) y=3'b100;
else if (a==8'b00100000) y=3'b101;
else if (a==8'b01000000) y=3'b110;
else if (a==8'b10000000) y=3'b111;
else y=3'bX;
end
endmodule

Simulated waveform:

Result: The verilog Program for 8-to-3 encoder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 32

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 4

4.1 Design of 8 to 1 Multiplexer Using Behavioral Model

Aim: Write a verilog program to simulate and verify the 8 to 1 Multiplexer using Behavioral Model

Software:
Xilinx 9.2i
Block Diagram:

Fig 4.1: Block Diagram of 8 to 1 multiplexer

Truth Table:

Fig 4.2: Truth Table of 8:1 MUX

Internal Circuit Diagram:

MLR Institute of Technology 33

Department Of ECE ECAD and VLSI Lab Manual

Fig 4.3: Internal Circuit Diagram of 8 to 1 Multiplexer

Fig 4.4: Block Diagram of 8 to 1 Multiplexer

Program:

module multiplier_8x1(
input [7:0] a,
input [2:0] s,
output reg y);
always@(a,s)
case(s)
3'b000: y=a[0];
3'b001: y=a[1];
3'b010: y=a[2];
3'b011: y=a[3];
3'b100: y=a[4];
3'b101: y=a[5];
3'b110: y=a[6];
3'b111: y=a[7];
endcase
endmodule

Theory:

Multiplexer:

In electronics, a multiplexer or mux is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select lines,
which are used to select which input line to send to the output. An electronic multiplexer can be

MLR Institute of Technology 34

Department Of ECE ECAD and VLSI Lab Manual

considered as a multiple-input, single-output switch i.e. digitally controlled multi-position switch. The
digital code applied at the select inputs determines which data inputs will be switched to output.

A common example of multiplexing or sharing occurs when several peripheral devices share a
single transmission line or bus to communicate with computer. Each device in succession is allocated a
brief time to send and receive data. At any given time, one and only one device is using the line. This is
an example of time multiplexing since each device is given a specific time interval to use the line.

In frequency multiplexing, several devices share a common line by transmitting at different.

Fig 4.5: Truth Table of 8:1 MUX

Simulation Waveform:

Procedure:
1. On the schematic editor of tina pro software connect the circuit as shown in the figure 1.1.

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

MLR Institute of Technology 35

Department Of ECE ECAD and VLSI Lab Manual

Viva Questions:

1. Why MUX is called universal element?

2. To implement 64X1 MUX how many number of 2X1 MUX required?
3. To implement 2nX1 MUX how many number of 2X1 MUX required?
4. To implement NOT gate, how many number of 2X1 MUX required?
5. To implement half adder how many number of 2X1 MUX required?

Result: The verilog Program for 8x1 mux by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 36

Department Of ECE ECAD and VLSI Lab Manual

4.2 Design of 1 to 8 Demultiplexer using Behavioral Model

Aim: Write a verilog program to simulate and verify the 1 to 8 Multiplexer using Behavioral Model

Software:
Xilinx 9.2i

Block Diagram:

Fig 6.1: Block Diagram of 1 to 8 Demultiplexer

Truth Table:

Fig 6.2:1 to 8 Demultiplexer representation using Truth Table

Theory:

DeMultiplexer:

A demultiplexer (or demux) is a device taking a single input signal and selecting one of many data-
output-lines, which is connected to the single input. A multiplexer is often used with a complementary
demultiplexer on the receiving end. A demultiplexer is a single-input, multiple-output switch.
Demultiplexers take one data input and a number of selection inputs, and they have several outputs.
They forward the data input to one of the outputs depending on the values of the selection inputs.

Demultiplexers are sometimes convenient for designing general purpose logic, because if the
demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function
of the selection bits can be constructed by logically OR-ing the correct set of outputs. Demultiplexer is
called as a distributro, since it transmits the same data to different destinations.

MLR Institute of Technology 37

Department Of ECE ECAD and VLSI Lab Manual

Fig 6.3: Logic Diagram of 1:8 DEMUX

Program:
module Demux8to1(
input a,
input [2:0] s,
output reg [7:0] z =0 );
always@(a,s)
if (s==0) z[0] = a;
else if (s==1) z[1] = a;
else if (s==2) z[2] = a;
else if (s==3) z[3] = a;
else if (s==4) z[4] = a;
else if (s==5) z[5] = a;
else if (s==6) z[6] = a;
else if (s==7) z[7] = a;
endmodule

MLR Institute of Technology 38

Department Of ECE ECAD and VLSI Lab Manual

Simulation Waveform:

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Result: The verilog Program for 1x8 demux by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 39

Department Of ECE ECAD and VLSI Lab Manual

4.3 4 to 1 multiplexer using logical expression

Aim: Write a verilog program to simulate and verify the 4 to 1 Multiplexer using logical expression

Program

module multiplexer4_1 ( a ,b ,c ,d ,x ,y ,dout );

output dout ;
input a ;
input b ;
input c ;
input d ;
input x ;
input y ;
assign dout = (a & (~x) & (~y)) |
(b & (~x) & (y)) |
(c & x & (~y)) |
(d & x & y);
endmodule

Simulated wave form:

Result: The verilog Program for 4x1 mux by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 40

Department Of ECE ECAD and VLSI Lab Manual

4.4 4 to 1 multiplexer Using Dataflow Model

Aim: Write a verilog program to simulate and verify the 4 to 1 Multiplexer using Dataflow Model

Program

module mux (a, b, c, d, s, o);

input a,b,c,d;
input [3:0] s;
output o;

assign o = s[3] ? a :1'bz;

assign o = s[2] ? b :1'bz;
assign o = s[1] ? c :1'bz;
assign o = s[0] ? d :1'bz;

endmodule

Simulated waveform:

Result: The verilog Program for 8x1 mux by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 41

Department Of ECE ECAD and VLSI Lab Manual

4.5 4 to 1 multiplexer in Structural model

Aim: Write a verilog program to simulate and verify the 4 to 1 Multiplexer using Structural Model

Program

module multiplexer4_1 ( a ,b ,c ,d ,x ,y ,dout );

output dout ;
input a ;
input b ;
input c ;
input d ;
input x ;
input y ;
assign dout = (a & (~x) & (~y)) |
(b & (~x) & (y)) |
(c & x & (~y)) |
(d & x & y);
endmodule

Simulated waveform:

Result: The verilog Program for 8x1 mux by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 42

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 5

5.1 Design of 4 BIT Binary to Gray conversion Using Behavioral model

Aim: Write a verilog program to simulate and verify the 4 Binary to Gray conversion Using
Behavioral model
Software:
Xilinx 9.2i

Block Diagram:

Fig 5.1: Block Diagram of 4 Bit Binary to Gray conversion

Truth Table:
Dec Gray Binary
0 000 000
1 001 001
2 011 010
3 010 011
4 110 100
5 111 101
6 101 110
7 100 111

Fig 5.2: Truth Table of 8:1 MUX

Internal Circuit Diagram:

Fig 5.3: RTL Diagram of 4 Bit Binary to Gray conversion

MLR Institute of Technology 43
Department Of ECE ECAD and VLSI Lab Manual

Fig 5.4: Internal circuit diagram for 4 Bit Binary to Gray conversion
Theory:

4 Bit Binary to Gray conversion:

The reflected binary code, also known as Gray code/Cyclic Code/Unique Distance Code after Frank
Gray, is a binary numeral system where two successive values differ in only one bit. It is a non-
weighted code.
The reflected binary code was originally designed to prevent spurious output from electromechanical
switches. Today, Gray codes are widely used to facilitate error correction in digital communications
such as digital terrestrial television and some cable TV systems.
Many devices indicate position by closing and opening switches. If that device uses natural binary
codes, these two positions would be right next to each other:
...
011
100
...

The problem with natural binary codes is that, with real (mechanical) switches, it is very
unlikely that switches will change states exactly in synchrony. In the transition between the two states
shown above, all three switches change state. In the brief period while all are changing, the switches
will read some spurious position. Even without key bounce, the transition might look like 011 001
101 100. When the switches appear to be in position 001, the observer cannot tell if that is the
"real" position 001, or a transitional state between two other positions. If the output feeds into a
sequential system (possibly via combinational logic) then the sequential system may store a false
value.The reflected binary code solves this problem by changing only one switch at a time, so there is
never any ambiguity of position,

Dec Gray Binary

0 000 000
1 001 001
2 011 010
3 010 011
4 110 100
5 111 101
6 101 110
7 100 111

MLR Institute of Technology 44

Department Of ECE ECAD and VLSI Lab Manual

Notice that state 7 can roll over to state 0 with only one switch change. This is called the "cyclic"
property of a Gray code. In the standard Gray coding the least significant bit follows a repetitive pattern
of 2 on, 2 off ( 11001100 ); the next digit a pattern of 4 on, 4 off; and so forth.

More formally, a Gray code is a code assigning to each of a contiguous set of integers, or to
each member of a circular list, a word of symbols such that each two adjacent code words differ by one
symbol. These codes are also known as single-distance codes, reflecting the Hamming distance of 1
between adjacent codes. There can be more than one Gray code for a given word length, but the term
was first applied to a particular binary code for the non-negative integers, the binary-reflected Gray
code, or BRGC, the three-bit version of which is shown above.

Program:
module binary_gray(
input [3:0] b,
output [3:0] g);
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule

Simulation Waveform:

MLR Institute of Technology 45

Department Of ECE ECAD and VLSI Lab Manual

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Viva Questions:
1. Why gray code is called cyclic code or unique distance code?
2. Give application of gray code.
3. Convert 1010 binary code to gray code.
4. Convert 1110 gray code to binary code.
5. Solve the Boolean expression AB+A bar B bar

Result: The verilog Program for 4 bit binary to gray conversion by using Xilinx 9.2i Software is
Simulated and verified successfully

MLR Institute of Technology 46

Department Of ECE ECAD and VLSI Lab Manual

5.2 Design of 4 BIT Binary to Gray Using Always statement

Aim: Write a verilog program to simulate and verify the 4 Binary to Gray conversion Using Always
statement

Program
module bin_to_gray(
input clk,
input [2:0]gray_input,
output reg [2:0]bin_out
);
always@(posedge clk)
begin
bin_out[2] <= gray_input[2];
bin_out[1] <= bin_out[2] ^ gray_input[1];
bin_out[0] <= bin_out[1] ^ gray_input[0];
end
endmodule

Simulated waveform:

Result: The verilog Program for 4 bit binary to gray conversion by using Xilinx 9.2i Software is
Simulated and verified successfully

MLR Institute of Technology 47

Department Of ECE ECAD and VLSI Lab Manual

5.3 Design of 4 BIT Binary to Gray conversion using structural model

Aim: Write a verilog program to simulate and verify the 4 Binary to Gray conversion Using
Structural Model

Program

module binary_to_gray ( din ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input [3:0] din ;

wire [3:0] din ;

always @ (din) begin

if (din==0)
dout = 0;
else if (din==1)
dout = 1;
else if (din==2)
dout = 3;
else if (din==3)
dout = 2;
else if (din==4)
dout = 6;
else if (din==5)
dout = 7;
else if (din==6)
dout = 5;
else if (din==7)
dout = 4;
else if (din==8)
dout = 12;
else if (din==9)
dout = 13;
else if (din==10)
dout = 15;
else if (din==11)
dout = 14;
else if (din==12)
dout = 10;
else if (din==13)
dout = 11;
else if (din==14)
dout = 9;
else
dout = 8;
end
MLR Institute of Technology 48
Department Of ECE ECAD and VLSI Lab Manual

endmodule

Simulated waveform:

Result: The verilog Program for 4 bit binary to gray conversion by using Xilinx 9.2i Software is
Simulated and verified successfully

MLR Institute of Technology 49

Department Of ECE ECAD and VLSI Lab Manual

5.4 Design of BCD to 7 segment code Converter using behavioral Model

Aim: Write a verilog program to simulate and verify the 7 segment code Gray conversion using
behavioral Model

Program

module BCD_to_7seg ( bcd ,seg7 );

output [6:0] seg7 ;
reg [6:0] seg7 ;

input [3:0] bcd ;

wire [3:0] bcd ;

always @ (bcd) begin

if (bcd==0)
seg7 = 7'b0000001;
else if (bcd==1)
seg7 = 7'b1001111;
else if (bcd==2)
seg7 = 7'b0010010;
else if (bcd==3)
seg7 = 7'b0000110;
else if (bcd==4)
seg7 = 7'b1001100;
else if (bcd==5)
seg7 = 7'b0100100;
else if (bcd==6)
seg7 = 7'b1100000;
else if (bcd==7)
seg7 = 7'b0001111;
else if (bcd==8)
seg7 = 7'b0000000;
else if (bcd==9)
seg7 = 7'b0001100;
else
seg7 = 7'b1111111;
end
endmodule

MLR Institute of Technology 50

Department Of ECE ECAD and VLSI Lab Manual

Simulated waveform:

Result: The verilog Program for BCD to 7 segment code conversion by using Xilinx 9.2i Software is
Simulated and verified successfully

MLR Institute of Technology 51

Department Of ECE ECAD and VLSI Lab Manual

5.5 Design of BCD to 7 segment code Converter using conditional operator

Aim: Write a verilog program to simulate and verify the 7 segment code Gray conversion using
conditional operator

Program

module bcd_to_7segment_CK ( bcd ,seg7 );

output [6:0] seg7 ;

input [2:0] bcd ;

assign seg7 = (bcd==0) ? 7'b1111110 :

(bcd==1) ? 7'b0110000 :
(bcd==2) ? 7'b1101101 :
(bcd==3) ? 7'b1111001 :
(bcd==4) ? 7'b0110011 :
(bcd==5) ? 7'b1011011 :
(bcd==6) ? 7'b0011111 :
(bcd==7) ? 7'b1110000 :
(bcd==8) ? 7'b1111111 :
(bcd==9) ? 7'b1110011 :
7'b0000000 ;

endmodule

Simulated waveform:

Result: The verilog Program for BCD to 7 segment code conversion by using Xilinx 9.2i Software is
Simulated and verified successfully

MLR Institute of Technology 52

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 6

6.1 Design of 4 BIT COMPARATOR USING DATA FLOW MODEL

Aim: Write a verilog program to simulate and verify 4 BIT COMPARATOR using Data Flow Model

Software:

Xilinx 9.1i.

Block Diagram:

Fig 6.4: Block Diagram of 2 BIT Comparator

Truth Table:

Fig 6.5: 2 Bit Comparator Truth Table

MLR Institute of Technology 53

Department Of ECE ECAD and VLSI Lab Manual

Fig 6.6: RTL Diagram For 2 Bit Comparator Truth Table

Theory:

2 BIT Binary Comparator:

A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or equal
to the other number. Comparators are used in a central processing units (CPU) and microcontrollers
Examples of digital comparator include the CMOS 4063 and 4585 and the TTL 7485 and 74682-'89.

MLR Institute of Technology 54

Department Of ECE ECAD and VLSI Lab Manual

The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers have
analog comparators on some of their inputs that can be read or trigger an interrupt.

The purpose of a two-bit binary comparator is quite simple. It determines whether one 2-bit input
number is larger than, equal to, or less than the other. The circuitry accomplishes this through several
logic gates that operate on the principles of Boolean algebra. Since the circuitry is based upon an
algebraic system it can not only be made simpler through mathematical manipulation, but there is also
no absolute solution to the given task

Design

The first step in the creation of the comparator circuit is the generation of a truth table that lists the
input variables, their possible values, and the resulting outputs for each of those values. The truth table
used for this experiment is shown

Fig 6.7: 2 Bit Comparator Truth Table

From the truth table, canonical minterm equations were generated for each output variable. These
equations were then simplified to represent as few logic gates as possible

The final equations were then used to sketch a circuit schematic for each variable. Once each
variable had a schematic, common values were found and the three schematics were combined to create
a single circuit diagram.

MLR Institute of Technology 55

Department Of ECE ECAD and VLSI Lab Manual

The three minterm equations were able to be simplified down to

The other problem with the circuit design is its inability to interpret signed numbers. For example,
when A is 10 and B is 00, the circuit shows that A is greater than B. If A is interpreted as a signed
number its value is negative two. In this case, the comparator should show L as a high as A would be
less than B.

Program:
module Comparator(
input [3:0] a,
input [3:0] b,
output a_gt_b,
output a_ls_b,
output a_eq_b
);
assign a_gt_b = (a > b);
assign a_ls_b = (a < b);
assign a_eq_b = (a == b);
endmodule

Simulation Waveform:

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

MLR Institute of Technology 56

Department Of ECE ECAD and VLSI Lab Manual

Viva Questions:
1. Explain what is the differnce between decoder and demultiplexer?
2. Which gates are used to implement Demultiplexier?
3. To Design 1X8 De-Mux. How many number of 1X2 De-Mux required.
4. Write the output expression for 2-bit comparator?
5. What are the applications of comparator?

Result: The verilog Program for 4 bit comparator by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 57

Department Of ECE ECAD and VLSI Lab Manual

6.2 Design of 1 bit Comparator using dataflow model

Aim: Write a verilog program to simulate and verify 1 BIT COMPARATOR using Data Flow Model

Program

module comp4bit(eq,gr,ls,a,b);
input [3:0] a,b;
output eq,gr,ls;
assign eq = (a==b) ? 1 : 0;
assign gr = (a>b) ? 1 : 0;
assign ls = (a<b) ? 1 : 0;
endmodule

Simulated waveform:

Result: The verilog Program for 1 bit comparator by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 58

Department Of ECE ECAD and VLSI Lab Manual

6.3 Design of 2 Bit Comparator Using Dataflow Model

Aim: Write a verilog program to simulate and verify 2 BIT COMPARATOR using Data Flow Model

Program

module comparator_2bit ( a ,b ,equal ,greater ,lower );

output equal ;
output greater ;
output lower ;
input [1:0] a ;
input [1:0] b ;
assign equal = (a==b) ? 1 : 0;
assign greater = (a>b) ? 1 : 0;
assign lower = (a<b) ? 1 : 0;

endmodule

Simulated waveform:

Result: The verilog Program for 2 bit comparator by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 59

Department Of ECE ECAD and VLSI Lab Manual

6.4 Design of 4 bit Comparator using behavioral model

Aim: Write a verilog program to simulate and verify 4 BIT COMPARATOR using behavioral model

Program

module comparator ( a ,b ,equal ,greater ,lower );

output equal ;
reg equal ;
output greater ;
reg greater ;
output lower ;
reg lower ;
input [3:0] a ;
wire [3:0] a ;
input [3:0] b ;
wire [3:0] b ;
always @ (a or b) begin
if (a<b) begin
equal = 0;
lower = 1;
greater = 0;
end else if (a==b) begin
equal = 1;
lower = 0;
greater = 0;
end else begin
equal = 0;
lower = 0;
greater = 1;
end
end
endmodule

simulation wave form:

Result: The verilog Program for 4 bit comparator by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 60

Department Of ECE ECAD and VLSI Lab Manual

6.5 Design of 4 bit Comparator using structural model

Aim: Write a verilog program to simulate and verify 4 BIT COMPARATOR using structural
model

Program

module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin

if (reset)
dout <= 0;
else
dout <= dout + 1;
end

endmodule

simulated waveform :

Result: The verilog Program for 4 bit comparator by using Xilinx 9.2i Software is Simulated and
verified successfully

MLR Institute of Technology 61

Department Of ECE ECAD and VLSI Lab Manual

Experiment No: 7
7.1 Full Adder Using Dataflow Model

Aim: Write a verilog program to simulate and verify Full Adder using Dataflow Model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

MLR Institute of Technology 62

Department Of ECE ECAD and VLSI Lab Manual

Internal Circuit Diagram:

Fig 7.2: Internal Circuit Diagram of Full Adder

Fig 7.3: Internal Circuit Diagram of Full Adder

Theory:

Full Adder:

A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder
adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit
MLR Institute of Technology 63
Department Of ECE ECAD and VLSI Lab Manual

carried in from the next less significant stage. The full-adder is usually a component in a cascade of
adders, which add 8, 16, 32, etc. binary numbers. The circuit produces a two-bit output sum typically
represented by the signals Cout and S.

A full adder can be implemented in many different ways such as with a custom Transistor level
circuit or composed of other gates. One example implementation is with and
.

In this implementation, the final OR Gate before the carry-out output may be replaced by an XOR Gate
without altering the result

ing logic. Using only two types of gates is convenient if the circuit is being implemented using simple
IC chips which contain only one gate type per chip. In this light, Cout can be implemented as
.

A full adder can be constructed from two half adders by connecting A and B to the input of one half
adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input
and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and
Cout could be made the three-bit majority function of A, B, and Ci.

Program:
module fa_structural(x,y,cin,s,cout);
input x,y,cin;
output s,cout;
wire s1,c1,c2,c3;
xor(s1,x,y);
xor(s,cin,s1);
and(c1,x,y);
and(c2,y,cin);
and(c3,x,cin);
or(cout,c1,c2,c3);
endmodule

Simulation Waveform:

MLR Institute of Technology 64

Department Of ECE ECAD and VLSI Lab Manual

Procedure:
1. On the schematic editor of tina pro software connect the circuit as shown in the figure 1.1.

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Result: The verilog Program for full adder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 65

Department Of ECE ECAD and VLSI Lab Manual

7.2 Design of Full adder using Behavioral Model

Aim: Write a verilog program to simulate and verify Full Adder using Behavioral Model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

MLR Institute of Technology 66

Department Of ECE ECAD and VLSI Lab Manual

Internal Circuit Diagram:

Fig 7.2: Internal Circuit Diagram of Full Adder

Fig 7.3: Internal Circuit Diagram of Full Adder

MLR Institute of Technology 67

Department Of ECE ECAD and VLSI Lab Manual

Program:

module FullAdder_CtAssign(
input A,
input B,
input Ci,
output S,
output Co
);
assign S =A^B^Ci;
assign Co= (A&B) | (Ci&A) | (Ci&B);
endmodule

Simulation Waveform:

Procedure:
1. On the schematic editor of tina pro software connect the circuit as shown in the figure 1.1.

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Result: The verilog Program for full adder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 68

Department Of ECE ECAD and VLSI Lab Manual

7.3 Design Of Full Adder Using Structural Model

Aim: Write a verilog program to simulate and verify Full Adder using Behavioral Model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

MLR Institute of Technology 69

Department Of ECE ECAD and VLSI Lab Manual

Internal Circuit Diagram:

Fig 7.2: Internal Circuit Diagram of Full Adder

Program:

module FullAdder_Structural(
input A,
input B,
input Ci,
output S,
output Co
);
wire z1,z2,z3,z4;
and And1(z1,A,B);
and And2(z2,A,Ci);
and And3(z3,B,Ci);
or Or1(Co, z1, z2, z3);
xor Xor1(z4, A, B);
xor Xor2(S,z4,Ci);
endmodule

Simulation Waveform:

Result: The verilog Program for full adder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 70

Department Of ECE ECAD and VLSI Lab Manual

7.4 Design of Full adder Using Procedural Model

Aim: Write a verilog program to simulate and verify Full Adder using Procedural Model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

MLR Institute of Technology 71

Department Of ECE ECAD and VLSI Lab Manual

Program:
module FullAdder_Procedural(
input A,
input B,
input Ci,
output reg S,
output reg Co
);
always @(Ci, A, B)
begin
case({Ci, A, B})
3'b000: {Co,S}= 'b00;
3'b001: {Co,S}= 'b01;
3'b010: {Co,S}= 'b01;
3'b011: {Co,S}= 'b10;
3'b100: {Co,S}= 'b00;
3'b101: {Co,S}= 'b10;
3'b110: {Co,S}= 'b10;
3'b111: {Co,S}= 'b11;
Endcase

Simulation Waveform:

Result: The verilog Program for full adder by using Xilinx 9.2i Software is Simulated and verified
successfully

Precautions
Use Computer with proper care and shut down it after completion of the work.
DONT INSERT PEN DRIVES.

Viva Questions:

1. How many number of NAND and NOR gates are required to implement Full adder?
2. Write the other expressions for Sum and Carry for full adder and full subtractor?
3. Design Full adder using 3X8 Decoder.
4. What are the difference between combinational circuits and sequential circuits?
5. What is the main difference between Half adder and Full adder?
MLR Institute of Technology 72
Department Of ECE ECAD and VLSI Lab Manual

7.5 Design Of Full Adder Using Two Half Adder

Aim: Write a verilog program to simulate and verify Full Adder using Two Half Adder

Program
module ha(sumh,carryh,a,b);
input a,b;
output sumh,carryh;
xor x1(sumh,a,b);
and a1(carryh,a,b);
endmodule
//full adder
module fastrc(sum,carry,A,B,Cin);
input A,B,Cin;
output sum,carry;
wire sum1,carry1,carry2;
ha h1(sum1,carry1,A,B);
ha h2(sum,carry2,sum1,Cin);
or o1(carry,carry2,carry1);
endmodule
Simulation Wave Form

Result: The verilog Program for full adder by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 73

Department Of ECE ECAD and VLSI Lab Manual

8.1 Design of SR Flip flop using Behavioral Model

Aim: Write a verilog program to simulate and verify SR flip flop using behavioral model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

Internal Circuit diagram:

Theory:
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state
information. The circuit can be made to change state by signals applied to one or more control inputs and will
have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a
fundamental building block of digital electronics systems used in computers, communications, and many other
types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for storage of state,
and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state
depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be
used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered); the simple
ones are commonly called latches. The word latch is mainly used for storage elements, while clocked devices
are described as flip-flops.

Flip-flop types
Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[16]), T ("toggle"), and JK types are the common
ones. The behavior of a particular type can be described by what is termed the characteristic equation, which derives the "next" (i.e.,
after the next clock pulse) output, , in terms of the input signal(s) and/or the current output, .

MLR Institute of Technology 74

Department Of ECE ECAD and VLSI Lab Manual

Simple set-reset latches

SR NOR latch

An SR latch, constructed from a pair of cross-coupled NOR gates (an animated picture). Red and black mean logical '1' and '0', respectively.

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand
for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked
Q.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S
(Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R
is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

SR latch operation[17]

Characteristic table Excitation table

S R Qnext Action Q Qnext S R

0 0 Q hold state 0 0 0 x

0 1 0 reset 0 1 1 0

1 0 1 set 1 0 0 1

1 1 X not allowed 1 1 X 0

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output zeros,
it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go
low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation
time relations between the gates (a race condition). In certain implementations, it could also lead to
longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values (errors) in high-frequency
digital circuits. Although this condition is usually avoided, it can be useful in some applications.

To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to one of the non-
restricted combinations. That can be:

Q = 1 (1,0) referred to as an S-latch

MLR Institute of Technology 75

Department Of ECE ECAD and VLSI Lab Manual

Q = 0 (0,1) referred to as an R-latch

Keep state (0,0) referred to as an E-latch

Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.

Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.

SR NAND latch

An SR latch

This is an alternate model of the simple SR latch built with NAND (not AND) logic gates. Set and reset now become active low
signals, denoted S and R respectively. Otherwise, operation is identical to that of the SR latch. Historically, SR-latches have been
predominant despite the notational inconvenience of active-low inputs.

SR latch operation

S R Action

0 0 Restricted combination

0 1 Q=1
Symbol for an SRNAND latch

1 0 Q=0

1 1 No Change

JK latch
The JK latch is much less used than the JK flip-flop. The JK latch follows the following state table:

JK latch truth table

J K Qnext Comment

0 0 Q No change

MLR Institute of Technology 76

Department Of ECE ECAD and VLSI Lab Manual

0 1 0 Reset

1 0 1 Set

1 1 Q Toggle

Hence, the JK latch is an SR latch that is made to toggle its output when passed the restricted combination of 11. Unlike the JK flip-flop, the 11 input combination
[19]
for the SR latch is not useful because there is no clock that directs toggling.

Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output; when several transparentlatches follow each other,
using the same clock signal, signals can propagate through all of them at once. Alternatively, additional logic can be added to a simple transparent latch to make
it non-transparent or opaque when another input (an "enable" input) is not asserted. By following a transparent-high latch with a transparent-low (or opaque-high)
latch, a masterslave flip-flop is implemented.

Gated SR latch

A gated SR latch circuit diagram constructed from NOR gates.

A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of
AND gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would
transform into a gated SR latch with inverted enable).

With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately
reproduce on the (Q,Q) output, i.e. the latch is transparent.

With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high.

The enable input is sometimes a clock signal, but more often a read or write strobe.

Gated SR latch operation

E/C Action

0 No action (keep state)

Symbol for a gated SR latch

1 The same as non-clocked SR latch

MLR Institute of Technology 77

Department Of ECE ECAD and VLSI Lab Manual

Program:
module sr_ff(input S,input R,input Clk,output reg Qa =1'b0,
output reg Qb =1'b1);
reg a,b;
always@(S,R,Clk)
begin
a=Qa;
b=Qb;
if (Clk==1'b1)
case({S,R})
'b00: {Qa,Qb} ={a,b};
'b01: {Qa,Qb} = 'b01;
'b10: {Qa,Qb} = 'b10;
endcase
else if(Clk==1'b0)
{Qa,Qb} ={a,b};
end
endmodule

Simulation Waveform:

Result: The verilog Program for SR flip flop by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 78

Department Of ECE ECAD and VLSI Lab Manual

8.2 Design of D Flip Flop using Behavioral model

Aim: Write a verilog program to simulate and verify D flip flop using behavioral model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

Internal Circuit diagram:

Theory:
D flip-flop

D flip-flop symbol

The D ip-op is widely used. It is also known as a data or delay flip-flop. The D flip-flop captures the value of the
D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value
becomes the Q output. At other times, the output Q does not change. The D flip-flop can be viewed as a memory
cell, a zero-order hold, or a delay line.

Truth table:

Clock D Qnext

Rising edge 0 0

Rising edge 1 1

MLR Institute of Technology 79

Department Of ECE ECAD and VLSI Lab Manual

Non-Rising X Q

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D
and clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-
flops. By setting S = R = 0, the flip-flop can be used as described above.

Inputs Outputs

S R D > Q Q'

0 1 X X 0 1

1 0 X X 1 0

1 1 X X 1 1

4-bit serial-in, parallel-out (SIPO) shift register

These flip-flops are very useful, as they form the basis for shift registers, which are an essential part of
many electronic devices. The advantage of the D flip-flop over the D-type "transparent latch" is that the
signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the
D input will be ignored until the next clock event. An exception is that some flip-flops have a "reset"
signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the
clock.

The above circuit shifts the contents of the register to the right, one bit position on each active transition
of the clock. The input X is shifted into the leftmost bit position.

D-Flipflop (Delay)

To avoid the undesirable state in RS-FF, we let and rename as

. Now only the middle two states in the above RS-FF remain and the resulting circuit is a D-
flipflop:

MLR Institute of Technology 80

Department Of ECE ECAD and VLSI Lab Manual

Program:
module ff_d(data,clk,reset,q );
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk or negedge reset)
if (reset) begin
q <= 1'b0;
end
else begin
q <= data;
end
endmodule

Simulation Waveform:

Result: The verilog Program for SR flip flop by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 81

Department Of ECE ECAD and VLSI Lab Manual

8.3 Design Of Jk Flip Flop Using Behavioural Model

Aim: To simulate and verify the JK flip flop using Behavioral model

Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

Internal Circuit diagram:

Theory:
JK flip-flop

A circuit symbol for a positive-edge-triggered JK flip-flop

JK flip-flop timing diagram

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the
combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a
command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather,
will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-
flop is therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

MLR Institute of Technology 82

Department Of ECE ECAD and VLSI Lab Manual

JK Flip Flop operation

Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment

0 0 Q hold state 0 0 0 X No change

0 1 0 reset 0 1 1 X Set

1 0 1 set 1 0 X 1 Reset

1 1 Q toggle 1 1 X 0 No change

Another way to avoid the problem of the RS flip-flop when R=S=1 is to have feedbacks
from Q and Q' to the input AND gates, as shown below. The resulting circuit is called JK
flip-flop with two inputs J=S and K=R.

It is not difficult to obtain the truth table of this JK flip-flop. Note that when J=K=1, the
flip-flop always complements its previous output. In the following the clock CLK is omitted
as the circuit is active only when CLK=1.

MLR Institute of Technology 83

Department Of ECE ECAD and VLSI Lab Manual

Program:
module jk_ff(input wire J,
input wire K,
input wire Clk,
output reg Q=0,
output reg Qbar=1);

reg a,b;
always@(posedge Clk)
begin
a=Q; b=~Q;
case({J,K})
'b00: {Q,Qbar} = {a,b};
'b01:
begin
Q=0; a=Q; b=~Q; Qbar =b;
end
'b10:
begin
Q=1; a=Q; b=~Q; Qbar =b;
end
'b11: {Q,Qbar} = {b,a};
endcase
end
endmodule

Simulation Waveform:

Result: The verilog Program for JK flip flop by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 84

Department Of ECE ECAD and VLSI Lab Manual

8.4 Design of T Flip Flop using

Aim: To simulate and verify the T flip flop using Behavioral model
Software:
Xilinx 9.2i

Block Diagram:

Fig 2.1: Block Diagram of Full Adder

Truth Table:

Internal Circuit diagram:

Theory:
T flip-flop

A circuit symbol for a T-type flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If the T input is
low, the flip-flop holds the previous value. This behavior is described by the characteristic equation:

(expanding the XOR operator)

and can be described in a truth table:

T flip-flop operation

Characteristic table Excitation table

Comment Comment

0 0 0 hold state (no clk) 0 0 0 No change

MLR Institute of Technology 85

Department Of ECE ECAD and VLSI Lab Manual

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is
4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has
application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins
are connected together and act as T) or D flip-flop (T input and Qprevious is connected to the D input through
an XOR gate). A T flip-flop can also be built using an edge-triggered D flip-flop with its D input fed from its
own inverted output.

T-Flipflop (Toggle)

If the J and K inputs are tied together and renamed as T (for toggle), only the first
and last states of JK-FF remain and the FF becomes a toggle FF:

The different types of Flipflops (R,S, J,K, D, T) can also be described by their excitation

table as shown below. The left side shows the desired transition from to ,
the right side gives the triggering signals of various types of FFs needed for the transitions.

MLR Institute of Technology 86

Department Of ECE ECAD and VLSI Lab Manual

Program:
module t_ff(input T,input Clk,output reg Q=0,output reg Qbar,output reg Di);

always@(posedge Clk)
begin
Di=T^Q; Q=Di; Qbar=~Q;
end
endmodule

Simulation Waveform:

Result: The verilog Program for T flip flop by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 87

Department Of ECE ECAD and VLSI Lab Manual

8.5 Design a Synchronous JK flip flop using case statement

Aim: To simulate and verify the Synchronous JK flip flop using case statement

Program
module JKflipflop(
input wire J,
input wire K,
input wire Clk,
output reg Q=0,
output reg Qbar=1);
reg a,b;
always@(posedge Clk)
begin
a=Q; b=~Q;
case({J,K})
'b00: {Q,Qbar} = {a,b};
'b01:
begin
Q=0; a=Q; b=~Q; Qbar =b;
end
'b10:
begin
Q=1; a=Q; b=~Q; Qbar =b;
end
'b11: {Q,Qbar} = {b,a};
Endcase

MLR Institute of Technology 88

Department Of ECE ECAD and VLSI Lab Manual

Simulation wave forms

Result: The verilog Program for JK flip flop by using Xilinx 9.2i Software is Simulated and verified
successfully

MLR Institute of Technology 89