EEE 525: VLSI Design, L-01

Introduction

Spring 2007, ASU

Yu (Kevin) Cao, [email protected], GWC 336

Highlight
ƒ Course orientation
– Objective, textbook, assignments, and grading policy
ƒ VLSI design
– History, today, and tomorrow
– Design flow: Integration and abstraction
ƒ Key design metrics:
– Area, performance, power, reliability, and cost
ƒ Challenges and trend for nano-VLSI
ƒ Reading: Chapter 1
ƒ Handout: the syllabus and schedule
EEE525, ASU, Y. Cao Lecture 01 -2-

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Basic Information
ƒ Instructor: Y. Kevin Cao, GWC 336
– Office hour: MW, 1:30-2:30pm; E-mail: [email protected]
ƒ Textbook:
– CMOS VLSI Design: A Circuits and Systems Perspective, by
Neil H. E. Weste and David Harris
ƒ Other references:
– Design of High-Performance Microprocessor Circuits, Edited by
A. Chandrakasan, et al.
– Digital Integrated Circuits: A Design Perspective, by Jan M.
Rabaey, et al. (http://bwrc.eecs.berkeley.edu/IcBook/)
ƒ Lab at GWC 273, with TA available
ƒ Lectures etc. are available at http://my.asu.edu
EEE525, ASU, Y. Cao Lecture 01 -3-

What will you learn

ƒ VLSI design knowledge that is both fundamental and practical, in the
context of key design principles
– ~40% overlapped with EEE 425; focus on VLSI system design
ƒ Pre-requisite: basic understanding of CMOS and digital circuits
– Online students are required to have their own access to design tools
ƒ Content:

Design metrics
Fundamental Practical
CMOS, interconnect, ALU, memory, datapath,
cost, performance,
inverter, logic styles clock, power, I/O, CAD
power, and reliability

ƒ Further study: computer architecture, CAD, and analog design

EEE525, ASU, Y. Cao Lecture 01 -4-

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Assignments
ƒ Homework (15%): exercise your learning
– Totally five: three before Midterm and two after it
– Part of them will be software labs
ƒ Project : design and optimization of a datapath circuit
– Phase I (15%): schematic design with Spectre/SPICE
– Phase II (15%): layout, extraction, and optimization
– Two people per group, with balanced contribution
– The load will be adjusted for online students
– Grade is based on the ranking of design quality: speed, power,
area, layout, and report
ƒ Examination: evaluate your knowledge
– One mid-term (25%): design fundamentals
– Final (30%): majority of the final is from the second half
EEE525, ASU, Y. Cao Lecture 01 -5-

Grading Policy
ƒ Letter grade depends on the relative distribution,
with + and – (µ: average; σ: standard deviation)
– A+: top 10%
– A: > µ + 0.5·σ
– A-: > µ
– B+: > µ - 0.5·σ
– B: > µ - σ
– C: > µ - 1.5·σ
– D: else
ƒ HW (15%), Project (30%), Midterm (25%),
Final (30%)
EEE525, ASU, Y. Cao Lecture 01 -6-

3
Highlight
ƒ Course orientation
– Objective, textbook, assignments, and grading policy
ƒ VLSI design
– History, today, and tomorrow
– Design flow: Integration and abstraction
ƒ Key design metrics:
– Area, performance, power, reliability, and cost
ƒ Challenges and trend for nano-VLSI
ƒ Reading: Chapter 1
ƒ Handout: the syllabus and schedule
EEE525, ASU, Y. Cao Lecture 01 -7-

The First Computing System

Abacus
(3000 B.C. – 300 A. D.)
by Chinese
and Mesoamerican

Size: > 10cm

Speed: your finger-run
Power: no sweating
Cost: home made

EEE525, ASU, Y. Cao Lecture 01 -8-

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The First Electronic Computer

ENIAC
(1946)
by U.S.A.

Size: 1800 ft2

Speed: 40 div./sec.
Power: 160kW
Cost: $486, 804.22

EEE525, ASU, Y. Cao Lecture 01 -9-

The First Transistor: A Revolution

Transistor
(1947)
by Bell Labs

Nobel Prize, 1951

Shockley, Bardeen,
and Brattain

Much better scalability and reliability

EEE525, ASU, Y. Cao Lecture 01 - 10 -

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The First Integrated Circuit

Integrated Circuit
(1958)
by TI

Nobel Prize, 2000

Kilby

1 transistor, 3 resistors, and 1 capacitor

EEE525, ASU, Y. Cao Lecture 01 - 11 -

The First Microprocessor Chip

4004 CPU
(1971)
by Intel

Size: ~ 9mm2,
2.3 K transistors @10µm
Speed: 1MHz
Design team: 3

EEE525, ASU, Y. Cao Lecture 01 - 12 -

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The Pentium 4 CPU
MOSFET

Interconnect

P4 CPU (2002)
Size: ~217mm2, 42M @ 0.18µm
Speed: 2GHz
Design team: 1000
EEE525, ASU, Y. Cao Lecture 01 - 13 -

Moore’s Law
ƒ In 1965, Gordon Moore (Intel) noted that the number of
transistors on a chip doubled every 18 to 24 months.
ƒ Prediction: semiconductor technology will double its
effectiveness every 18 months
16
COMPONENTS PER INTEGRATED FUNCTION

15
14
13
LOG2 OF THE NUMBER OF

12
11
10
9
8
7
6

Electronics,
5
4
3
2
1
0 April 19, 1965
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975

EEE525, ASU, Y. Cao Lecture 01 - 14 -

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Moore’s Law in Microprocessors
Year
Chip
Transistors 1980 1990 2000 2010 Frequency
(Hz)

1000M 3.2G

100M
Itanium 1.0G
10M
Pentium 200M
1M
80386
• Transistor counts: 2x
33M/ 2 years
100K
8086 • Channel length: 0.7 5M
/ 18 months
Technology 3.0µm 1.0µm 0.35µm 180nm 50nm
Node

EEE525, ASU, Y. Cao Lecture 01 - 15 -

Clock Frequency

10000
Doubles every
1000
2 years
Frequency (Mhz)

P6
100
Pentium ® proc
486
10 8085 386
8086 286

1 8080
8008 • Clock frequency: 2x / 2 years
4004
0.1
1970 1980 1990 2000 2010
Year

EEE525, ASU, Y. Cao Courtesy, Intel Lecture 01 - 16 -

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Evolution in Complexity

EEE525, ASU, Y. Cao Lecture 01 - 17 -

Die Size Growth

100
Die size (mm)

P6
10 486 Pentium ® proc
386
286
8080 8086
8085
8008 • Die Size: 14% / 2 years
4004
or 2x in 10 years
1
1970 1980 1990 2000 2010
Year

EEE525, ASU, Y. Cao Courtesy, Intel Lecture 01 - 18 -

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Driving Forces
ƒ Technology scaling
– Semiconductor device shrinks by 0.7x / generation
ƒ Circuit and System design
ƒ “Cleverness”
ƒ Functions per chip doubles every generation;
chip cost does not increase significantly
– Cost of a function decreases by 2x
ƒ On the other hand:
– Design population does not double every two years…
– Productivity per designer decreases due to
complexities of design and team management

EEE525, ASU, Y. Cao Lecture 01 - 19 -

Design Abstraction
SYSTEM

MODULE

GATE

CIRCUIT

DEVICE
G
S D
n+ n+

EEE525, ASU, Y. Cao Lecture 01 - 20 -

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Top-Down Design Flow

systems
systems

application software
Outp
ut M2
h=
system software 3;

k = h; h
k >3;
T h<
M1
platform / architecture h
sa pchg#
3;

circuits
LA T C H
s a b it
s a b it #
devices/interconnect

structures
structures

materials
materials

physics
physics

EEE525, ASU, Y. Cao Lecture 01 - 21 -

Job of a VLSI Designer

ƒ Design objectives:
speed speed speed/power
/reliability
area/cost speed/power
reliable ultra-
power low power low power

ƒ Design knobs:
– Architecture (gates/block, register count, etc)
– Circuit style (static, dynamic, etc)
– Circuit implementation (sizing, layout, VDD, etc.)
– Physical design (placement, routing, etc.)
EEE525, ASU, Y. Cao Lecture 01 - 22 -

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IC Design Tools
ƒ Synthesis
– Micro-architectural, Logic, Automatic physical generation

ƒ Static Analysis
– Design rule checking (DRC), Circuit parasitics extraction,
Timing analysis, Test generation
ƒ Dynamic Analysis
– Architectural simulation, Logic, Circuit simulation (SPICE)
for speed and power, Test verification
ƒ Tool capability is limited and exploited by your
physical understanding

EEE525, ASU, Y. Cao Lecture 01 - 23 -

Highlight
ƒ Course orientation
– Objective, textbook, assignments, and grading policy
ƒ VLSI design
– History, today, and tomorrow
– Design flow: Integration and abstraction
ƒ Key design metrics:
– Area, performance, power, reliability, and cost
ƒ Challenges and trend for nano-VLSI
ƒ Reading: Chapter 1
ƒ Handout: the syllabus and schedule
EEE525, ASU, Y. Cao Lecture 01 - 24 -

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 Challenges in Future VLSI
“Microscopic Problems” “Macroscopic Issues”
• Ultra-high speed design • Time-to-Market
• Interconnect • Millions of Gates
• Noise, Crosstalk • High-Level Abstractions
• Reliability, Manufacturability • Reuse & IP: Portability
• Power Dissipation • Predictability
• Clock distribution

• Main roadblocks: power, cost, and reliability

EEE525, ASU, Y. Cao Lecture 01 - 25 -

Power Dissipation
105 103
18KW
104 5KW 102 Switching
1.5KW
101
Power (Watts)

Power (W)

103 500W
100
Pentium® proc
102 10-1
486 10-2
10 8086 386
8080 10-3 Source: Intel
Leakage
1 4004 10-4
10µm 1µm 100nm 10nm
0.1
Technology node
1971 1974 1978 1985 1992 2000 2004 2008
Year

• Power delivery and dissipation will be prohibitive

EEE525, ASU, Y. Cao Courtesy, Intel Lecture 01 - 26 -

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Power Density
ƒ Power/transistor switching goes down with
technology scaling, but:
10000
Rocket
Power Density (W/cm2)

1000 Nozzle
Nuclear
100 Reactor
Hot Plate
8086
10 P6
4004
8008 8085 386 Pentium
286 486
8080
1
1970 1980 1990 2000 2010
Source: Intel
Year
EEE525, ASU, Y. Cao Lecture 01 - 27 -

Innovative Design Demanded

14
Module Heat Flux (w/cm2)

IBM ES9000
12
Bipolar CMOS
10

8 Fujitsu VP2000
IBM 3090S IBM RY5
NTT
6 IBM RY7
Fujitsu M-780

4 IBM3090
CDC Cyber 205
Pulsar
IBM RY6
IBM4381
IBM3084 IBM RY4
2 IBM370 Fujitsu
Apache
IBM360 IBM3033 M380 Pentium II
0
1950 1960 1970 1980 1990 2000 2010
Year of Announcement

ƒ Technology used to be the answer for this

trouble; but, no candidate around the corner
EEE525, ASU, Y. Cao Lecture 01 - 28 -

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Cost of Integrated Circuits
ƒ NRE (non-recurrent engineering) costs
– design time and effort, mask generation
– one-time cost factor
ƒ Recurrent costs
– silicon processing, packaging, test
– proportional to volume
– proportional to chip area

EEE525, ASU, Y. Cao Lecture 01 - 29 -

NRE Cost

EEE525, ASU, Y. Cao Lecture 01 - 30 -

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Recurrent Cost
Cost per Transistor
10-4
10-5
Dollar
10-6
10-7
10-8
10-9
1µm 100nm 10nm

ƒ Wafer size goes up to 12” (300mm)

ƒ Cost per production line increases to ~$5 Billion
ƒ Defect rate also explodes with technology scaling
EEE525, ASU, Y. Cao Lecture 01 - 31 -

Reliability
ƒ Process variations
ƒ Dynamic uncertainties:
– Temperature
– Power supply (Ldi/dt noise)
138 W/cm2
– Crosstalk
– Soft error

ƒ All degrade your yield

and waste resource

EEE525, ASU, Y. Cao Lecture 01 - 32 -

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Design Trend I: Integration
ƒ Integrate various technologies
ƒ Integral design solutions

Small Power
Signal RF RF

Power
Management

Analog
Baseband

Digital Baseband
(DSP + MCU)

EEE525, ASU, Y. Cao Lecture 01 - 33 -

Design of Nanoelectronics

1947 1958

???
Carbon Nanotube
FET

1993 2006

EEE525, ASU, Y. Cao Lecture 01 - 34 -

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Design Trend II: Parallelism

ƒ Concurrency for better

reliability, programmability,
and cost factor
ƒ Examples:
– Multiple core processor
– Regular array structures

EEE525, ASU, Y. Cao Lecture 01 - 35 -

Broader Applications
ƒ Digital IC have come a long way and still have
quite some potential left for the coming
decades:
– Computation and Communications
– Automobile (30-70 chips/car now)
– Consumer electronics
– Energy conservation
– Security and intelligence
– Biomedical
– Much more with your innovation

EEE525, ASU, Y. Cao Lecture 01 - 36 -

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Summary
ƒ EEE 525: design fundamentals and practices
underlying the VLSI system integration
ƒ Metrics: area, speed, power, reliability, and cost
ƒ Challenges ahead: power, cost, and reliability
ƒ Clear understanding from a circuit perspective
ƒ Contact: [email protected]
ƒ Office hours: MW 1:30-2:30pm, GWC 336
ƒ Web access: http://my.asu.edu

EEE525, ASU, Y. Cao Lecture 01 - 37 -

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