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Edited - 7 On Chip Clock Controller

The document discusses using on-chip clock controllers (OCC) to enable at-speed scan testing by alternating between a slow test clock from automatic test equipment and a fast clock from an on-chip PLL. OCC logic can be automatically generated and inserted at the RTL level to control switching between these clocks. This allows ATPG tools to generate tests for asynchronous interfaces between different clock domains using the more accurate on-chip clocks rather than external clocks from testers.

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Jayesh Popat
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3K views8 pages

Edited - 7 On Chip Clock Controller

The document discusses using on-chip clock controllers (OCC) to enable at-speed scan testing by alternating between a slow test clock from automatic test equipment and a fast clock from an on-chip PLL. OCC logic can be automatically generated and inserted at the RTL level to control switching between these clocks. This allows ATPG tools to generate tests for asynchronous interfaces between different clock domains using the more accurate on-chip clocks rather than external clocks from testers.

Uploaded by

Jayesh Popat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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On-Chip Clock Controller

OCC -Overview
On-Chip Clock Control (OCC)
At-speed scan testing, or scan testing at the actual system operating
frequency, is important to ensure the quality of a fast SoC.
However, there is a limit to the clock frequency that can be applied by
automatic test equipment (ATE).
Thus, clock pulses generated by an on-chip PLL are used for at-speed scan
testing.
Since it is not necessary to shift scan chains at-speed, scan testing proceeds,
alternating between a slow test clock and a fast PLL clock.
The logic that controls the run-time switching between these clocks is called
on-chip clock controller (OCC).
You can automatically generate and insert OCC logic at the RTL.
It allows an ATPG tool to automatically generate an at-speed test for the
asynchronous interfaces between clock domains running at different
frequencies.
At-speed Clocks
An at-speed test clock is required to deliver timing for at-speed tests. There are
two main sources for the at-speed test clocks.
One is the external ATE and the other is on-chip clocks.
Traditionally, ATE has always supplied the test clocks. In some cases, the ATE is
still a viable source for the at-speed testing clocks.
However, the sophistication and cost of the tester increase as the clocking speeds
and accuracy requirements rise.
The second source of clocks can come from inside the chip itself.
More and more designs include a phase-locked loop (PLL) or other on-chip clock
generating circuitry. Using these functional clocks for test purposes can provide
several advantages over using the ATE clocks.
First, test timing is more accurate when the test clocks exactly match the
functional clocks.
Secondly, the high-speed on-chip clocks reduce the ATE requirements, enabling
use of a less sophisticated and, thus, less expensive tester.
On-Chip Clock Control (OCC)
On-Chip Clock Control (OCC)
In this situation, the design has both internal and external clocks and control signals.
By using something called "named capture procedures," the user can specify the
functionality and relationships between the internal and external signals.
The ATPG tool then uses these relationships to create accurate at-speed test patterns
driven by the on-chip clocks.
Control registers are typically used to program which clocks to pulse and when.
These internal control registers can be loaded with specific values by the ATPG tool.
The ATPG user simply needs to specify the desired register values by using "condition
statements" in the named capture procedures.
This method is much easier than loading values through a boundary scan test access port
(TAP) controller, and it does not require extra external pins to feed in those register
values.
OCC generated clock for At-speed testing
Thank You!

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