Lecture-55

System Interface:
To interface 8253 with 8085A processor, CS signal is to be
generated. Whenever CS =0, chip is selected and depending upon A1
and A0 one of the internal registers is selected for data transfer. Let
the chip be interfaced using isolated I/O. Since in isolated I/O
mapped interfacing, IN PORT & OUT PORT instructions are used,
therefore 8-bit port address is duplicated as explained earlier.
A15 - A8 = A7 - A0
Since A1 and A0 select the internal register, these bits are not used to
generate CS . Let us consider the remaining bits A15 A11 be 00010
and A10 is not used to simplify the decoding circuit. Therefore, chip
will be selected whenever higher address A15 A8 be 00010xxx. The
two bits A1(or A9) and A0(or A8) select one of the timer or the control
word register. Accordingly, the addresses for timer/counters and
control word register would be as below:
Primary Address Fold Back Address
Timer/Counter 0 0001 0000 = 10H 0001 0100 = 14H
Timer/Counter 1 0001 0001 = 11H 0001 0101 = 15H
Timer/Counter 2 0001 0010 = 12H 0001 0110 = 16H
Control Word Register 0001 0011 = 13H 0001 0111 = 17H

Using these addresses, interfacing circuit can be developed. The

interfacing circuit for 8253 is shown below:
 IO/M
A15
A14 A1 A0 AD7-AD0 RD WR
A13
A12
A11 8

CS A1 A0 D7-D0 RD WR

8253
Timer 0 Timer 1 Timer 2

CLK0 GATE0 OUT0 CLK1 GATE1 OUT1 CLK2 GATE2 OUT2

Fig.10.4 Interfacing of 8253 with Microprocessor

The other possible circuit may have IO/M combined with RD and WR
to generate IO/M and IO/W and these signals are then connected to
RD and WR. In this case IO/M need not be used for generating CS.

Initialization:
Each of the three timers of 8253, TM0, TM1 and TM2 can be
independently programmed to operate in six different modes of
operation. To initialize the timers, microprocessor writes a command
word to control word register to select the operational parameters for
the counter, that is, to specify which of the six modes is to be used, to
select either binary or BCD decrementing and a code to specify
whether 8-bit or 16-bit value is to loaded or latch the counter. One
control word is required for each timer and they can be programmed
in any sequence; need not be in a sequence TM0, TM1 and TM2.
When the power is first turned ON, the timers are in undefined states.
 The control word format is shown below:
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RL1 RL0 M2 M1 M0 BCD

SC1 & SC0:

These bits indicate whether the control word being issued is
intended for Timer/Counter 0, 1 or 2 as indicated in the table:
SC1 SC0
0 0 Select counter 0
0 1 Select counter 1
1 0 Select counter 2
1 1 Illegal, Not permitted

RL1, RL0:
Each of the 8253s counters is 16-bit down counter. Since they
are accessed via an 8-bit data bus, two separate read or write
operations are required to completely read or write the count value
from/to one counter. The 8253 allows the user to read or write either
8-bit or 16-bit data and thus allows a substantial degree of freedom in
this regard. The next two bits RL1 and RL0 selects one of this
operation as shown below:
RL1 RL0
0 0 Counter latching operation
0 1 Read/ Load least significant byte only
1 0 Read/ Load most significant byte only
Read/ Load least significant byte first, then
1 1
most significant byte.
If both RL1 and RL0 are 0, the four lower order bits (M2, M1, M0 and
BCD) are dont cares. In this case, the control word being issued is to
latch the count value in the selected counter.

M2, M1, M0:

The mode of operation of the timer is selected by these three
bits as per table below:.
M2 M1 M0 Mode
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5

BCD:
A 0 in this bit position programs the selected counter to
operate as a 16-bit binary counter. The maximum value in binary is
FFFFH. A 1 in this bit programs the selected counter to operate as a
4-digit BCD counter. The maximum value in BCD is 9999D. The 16-
bit counters are down counters. This means that number in a counter
will be decrement by each clock pulse. The zero count is checked
after the counter is decremented. Therefore, the maximum count
value in both cases will be 0000; after first decrement the count
becomes either FFFFH or 9999D depending on BCD bit.
After the control word register has been programmed, the 8253
expects the count to be located into the counter as specified by the
RL bits of control word. If more than one counter is to be programmed
at one time, the software may be written to write a control word to
each counter and then load the count into each and counter or each
counter may be programmed completely with a control word and the
count value before initializing the other counter.

Modes of Operation:
Each of the three counters of 8253 can be programmed to operate in
six different modes of operation to produce the desired output. Each
timer requires a clock input. The counters are negative edge triggered
down counter, i.e., whenever there is HIGH to LOW transition at the
CLK input, the count value is decremented by 1. The down counting
is controlled by the gate. The output pin of the timer may be used to
generate different signals, e.g., an interrupt request signal in the
interrupt related modes.

Counter Loading:
In general, the counter register (or counting element) is not
loaded from input register (or input element) until the value written is
followed by a rising edge and a following edge of the clock input to
the counter as shown in figure below. In some of the modes, the
following edge of the clock input transfers the count value from input
element to counting element.
 CLK

4 3 2 1 0
WR N=4

Fig.10.5 Counter Loading

Mode-0: Interrupt on Terminal Count

The output of the timer/counter goes low whenever a timer is
programmed in mode 0. This is the only mode in which the normal
output of the timer is low. In rest of the modes, the normal output of
the timer is high. After the count value is loaded into the timer, the
output of the counter will remain low. If the gate is low the counting is
disabled. Once the gate is made HIGH, the 16-bit count value is
transferred from input element to counting element after one rising
and falling edge of the clock signal. The counter starts down counting
on subsequent clock pulses. The output remains low until count value
reaches 0. When the count value becomes zero, we say terminal
count has reached. The output will go high and remains high. This
LOW to HIGH transition at the output pin may be used to interrupt the
processor and to tell the processor that the desired delay is over. The
processor can take necessary action at this moment by transferring
control to an interrupt service subroutine. The output will not be
changed until the selected counter is reloaded with the mode word or
a new count value is loaded. After the counter has reached zero it will
continue to count down internally from 0000H to FFFFH to FFFEH
and so on but will not change the output signal.
 If the GATE is made 0 in this mode, the counter is disabled.
However, the count stops counting if GATE goes low during counting
and the current count value is freezed. Counting resumes from the
frozen value, when GATE is made high again. The count is
decrement at every HIGH to LOW transition till it becomes zero.
Therefore, the counter basically counts N clock pulses or N+1
transition of the clock.

CLK

4
WR N=4

GATE

OUT 4 3 2 1 0
T.C.

GATE

4 3 3 3 2 1 0
OUT
T.C.

Fig.10.6 Timing Waveforms of Timer in Mode-0

The count value may be changed at any instant even when the
counting operation is going on. Loading a new count value essentially
restart the counter with this new value. Note that if the counter value
to be loaded is of 8-bits, the effect of loading the new count value is
immediate, i.e., as soon as the new count value is loaded into input
element, it will be transferred to counting element and counting
begins with new initial count value. If the count value to be loaded is
of 16-bits, the counter stops counting after the first byte is loaded and
resumes counting only after the second byte is loaded.