Data Sheet: Hfbr-57E0Lz/Alz/Pz/Apz
Data Sheet: Hfbr-57E0Lz/Alz/Pz/Apz
Data Sheet: Hfbr-57E0Lz/Alz/Pz/Apz
Data Sheet
Description Features
The HFBR-57E0 Small Form Factor Pluggable LC trans- x RoHS compliant
ceivers provide the system designer with a product to x Full compliance with ATM Forum UNI SONET OC-3
implement a range of solutions for multimode fiber Fast multimode fiber physical layer specification
Ethernet and SONET OC-3 (SDH STM-1) physical layers for x Full compliance with the optical performance require-
ATM and other services. ments of the FDDI PMD Standard
This transceiver operates at a nominal wavelength of x Full compliance with the optical performance require-
1300 nm with an LC fiber connector interface with an ments of 100Base-FX version of IEEE802.3u
external connector shield (HFBR-57E0). x Industry standard Small Form Pluggable (SFP) pack-
age
Transmitter Section x LC duplex connector optical interface
The transmitter section of the HFBR-57E0 utilizes a 1300 x Operates with 62.5/125 m and 50/125 m multimode
nm InGaAsP LED. This LED is packaged in the optical fiber
subassembly portion of the transmitter section. It is x Single +3.3 V power supply
driven by a custom silicon IC which converts differential x +3.3 V TTL LOS output
PECL logic signals, ECL referenced (shifted) to a +3.3 V
x Receiver outputs are squelch enabled
supply, into an analog LED drive current.
x Manufactured in an ISO 9001 certified facility
Receiver Section x Temperature range:
The receiver section of the HFBR-57E0 utilizes an InGaAs 0 C to +70 C HFBR-57E0LZ/PZ:
PIN photodiode coupled to a custom silicon transimped- -40 C to +85 C HFBR-57E0ALZ/APZ:
ance preamplifier IC. It is packaged in the optical subas- x Bail de-latch option
sembly portion of the receiver.
This PIN/preamplifier combination is coupled to a custom Applications
quantizer IC which provides the final pulse shaping for
the logic output and the Loss of Signal (LOS) function. x OC-3 SFP transceivers are designed for ATM LAN and
The data output is differential. The data output is PECL WAN applications such as:
compatible, ECL referenced (shifted) to a +3.3 V power ATM switches and routers
supply. This circuit also includes a loss of signal (LOS) SONET/SDH switch infrastructure
detection circuit which provides an open collector logic x Multimode fiber ATM backbone links
high output in the absence of a usable input optical sig- x Fast Ethernet
nal. The LOS output is +3.3 V TTL.
Loss of Signal
20 V EE T 1 V EE T
The Loss of Signal (LOS) output indicates that the optical
input signal to the receiver does not meet the minimum 19 TD- 2 NC**
detectablelevel for FDDI and OC-3 compliant signals. 18 TD+ 3 Tx Disable
When LOS is high it indicates loss of signal. When LOS is
17 V EE T 4 MOD-DEF(2)
low it indicates normal operation. The LOS thresholds are
set to indicate a definite optical fault has occurred (e.g., 16 V CC T 5 MOD-DEF(1)
disconnected or broken fiber connection to receiver, 15 V CC R 6 MOD-DEF(0)
failed transmitter).
14 V EE R 7 NC
TRANSMITTER
TX Disable
MOD-DEF2
EEPROM MOD-DEF1
MOD-DEF0
2
Serial Identification (EEPROM) Electrostatic Discharge (ESD)
The HFBR-57E0 complies with the industry standard There are two conditions in which immunity to ESD
MSA that defines the serial identification protocol. This damage is important. Table 1 documents our immunity
protocol uses the 2-wire serial CMOS E2PROM protocol to both of these conditions. The first condition is during
of the ATMEL AT24C01A or equivalent. The contents of handling of the transceiver prior to insertion into the
the HFBR-57E0 serial ID memory are defined in Table 3 as transceiver port. To protect the transceiver, it is important
specified in the SFP MSA. to use normal ESD handling precautions.
Functional Data I/O These precautions include using grounded wrist straps,
workbenches, and floor mats in ESD controlled areas.
The HFBR-57E0 fiberoptic transceiver is designed to ac- The ESD sensitivity of the HFBR-57E0 is compatible with
cept industry standard differential signals. In order to re- typical industry production environments. The second
duce the number of passive components required on the condition is static discharges to the exterior of the host
customers board, Avago has included the functionality equipment chassis after installation. To the extent that the
of the transmitter bias resistors and coupling capacitors duplex LC optical interface is exposed to the outside of
within the fiberoptic module. The transceiver is compat- the host equipment chassis, it may be subject to system-
ible with an ac-coupled configuration and is internally level ESD requirements. The ESD performance of the
terminated. Figure 5 depicts the functional diagram of HFBR-57E0 exceeds typical industry standards.
the HFBR-57E0.
Immunity
Regulatory Compliance
Equipment hosting the HFBR-57E0 modules will be sub-
See Table 1 for transceiver Regulatory Compliance perfor- jected to radio-frequency electro magnetic fields in some
mance. The overall equipment design will determine the environments. These transceivers have good immunity to
certification level. The transceiver performance is offered such fields due to their shielded design.
as a figure of merit to assist the designer.
3
Electromagnetic Interference (EMI) Ordering Information
Most equipment designs utilizing these high-speed trans- The HFBR-57E0 1300 nm product is available for produc-
ceivers from Avago will be required to meet the require- tion orders through the Avago Component Field Sales
ments of FCC in the United States, CENELEC EN55022 Offices and Authorized Distributors worldwide.
(CISPR 22) in Europe and VCCI in Japan.
For technical information regarding this product, please
The metal housing and shielded design of the HFBR-57E0 visit the Avago website at www.avagotech.com.
minimize the EMI challenge facing the host equipment
Use the quick search feature to search for this part num-
designer. These transceivers provide superior EMI perfor-
ber. You may also contact the Avago Products Customer
mance. This greatly assists the designer in the manage-
Response Centre.
ment of the overall system EMI performance.
Applications Support Materials
Eye Safety
Contact your local Avago Component Field Sales Office
These transceivers provide Class 1 eye safety by design.
for information on how to obtain PCB layouts and evalu-
Avago has tested the transceiver design for compliance
ation boards for the transceivers.
with the requirements listed in Table 1 under normal
operating conditions and under a single fault condition. 200
3.0
Flammability 180
tr/f TRANSMITTER
Shipping Container 120
2.5 OUTPUT OPTICAL RISE/
FALL TIMES ns
3.0
The transceiver is packaged in a shipping container de-
100
signed to protect it from mechanical and ESD damage 1260 1280 1300 1320 1340 1360
0
-3 -2 -1 0 1 2 3
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1. T A = +25 C
2. V CC = 3.3 V dc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 13 AND 14 APPLY.
Figure 4. Relative Input Optical Power vs. Eye Sampling Time Position
4
1 H
3.3 V
10 F 0.1 F 1 H 0.1 F
3.3 V
Vc c T HFBR-57E0
4.7 K to 10 K
Tx Dis
3.3 V
82 82
0.1 F
50 TD+
SO+
LED DRIVER
& SAFETY
SO 50 TD CIRCUITRY
TX GND 0.1 F
130 130
SerDes 4.7 K to 10 K VccR
PROTOCOL 0.1 3.3 V
10 F F 130 130
IC
0.1 F
50 RD+
SI+
AMPLIFICATION
SI 50 RD &
QUANTIZATION
Rx_LOS 0.1 F
Rx_LOS
RX GND
82 82
MOD_DEF2
GPIO(X)
MOD_DEF1 EEPROM
GPIO(X)
MOD_DEF0
GP14
4.7 K to 4.7 K to 4.7 K to
10 K 10 K 10 K
3.3 V
1 H
V CC T
0.1 F
1 H
V CC R 3.3 V
0.1 F 10 F 0.1 F 10 F
Note: Inductors must have less than 1 ohm series resistance per MSA.
5
Table 2. Pin Description
Pin Name Function/Description MSA Notes
1 VEET Transmitter Ground
2 NC NC 1
3 Tx Disable Transmitter Disable- Module disables on high or open
4 MOD-DEF2 Module Definition 2 - Two Wire Serial ID Interface 2
5 MOD-DEF1 Module Definition 1 - Two Wire Serial ID Interface 2
6 MOD-DEF0 Module Definition 0 - grounded in module 2
7 NC NC
8 LOS Loss of Signal - high indicates loss of signal 3
9 VEER Receiver Ground
10 VEER Receiver Ground
11 VEER Receiver Ground
12 RD- Inverse Received Data Out 4
13 RD+ Received Data Out 4
14 VEER Receiver Ground
15 VCCR Receiver Power -3.3 V 10% 5
16 VCCT Transmitter Power -3.3 V 10% 5
17 VEET Transmitter Ground
18 TD+ Transmitter Data In 6
19 TD- Inverse Transmitter Data In 6
20 VEET Transmitter Ground
Notes:
1. Pin 2 connected to internal ground.
2. Mod-Def 0, 1, 2. are the module definition pins. They should be pulled up with a 4.7 K - 10 K: resistor on the host board to a supply less than
VCCT +0.3 V or VCCR +0.3 V.
Mod-Def 0 is grounded by the module to indicate that the module is present.
Mod-Def 1 is clock line of two wire serial interface for optional serial ID.
Mod-Def 2 is data line of two wire serial interface for optional serial ID.
3. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7 - 10 K:resistor on the host board to a
supply < VCCT, R +0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined
by the standard in use). Low indicates normal operation. In the low state, the output will be pulled to <0.8 V.
4. RD-/+: These are the differential receiver outputs. They are ac coupled 100 :differential lines which should be terminated with 100 : dif-
ferential at the SERDES. The ac coupling is done inside the module and is thus not required on the host board. The voltage swing on these
lines will be between 400 and 2000 mV differential (200 - 1000 mV single ended) when properly terminated.
5. VCCR and VCCT are the receiver and transmitter power supplies. They are defined as 2.97 - 3.63 V at the SFP connector pin. The maximum
supply current is 230 mA and the associated in-rush current will typically be no more than 30 mA above steady state after 500 nanoseconds.
6. TD-/+: These are the differential transmitter inputs. They are ac coupled differential lines with 100 : differential termination inside the module.
The ac coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 400 - 2000
mV (200 - 1000 mV single ended), though it is recommended that values between 400 and 1200 mV differential (200 - 600 mV single ended)
be used for best EMI performance. These levels are compatible with CML and LVPECL voltage swings.
6
Table 3. EEPROM Serial ID Memory Contents
Add Hex ASCII Add Hex ASCII Add Hex ASCII Add Hex ASCII
0 03 33 20 63 Note 3 95 Note 3
1 04 34 20 64 00 96 Note 5
2 07 35 20 65 12 97 Note 5
3 00 36 00 66 00 98 Note 5
4 00 37 00 67 00 99 Note 5
5 01, Note 6 38 17 68 Note 1 100 Note 5
6 20, Note 6 39 6A 69 Note 1 101 Note 5
7 00 40 48 H 70 Note 1 102 Note 5
8 00 41 46 F 71 Note 1 103 Note 5
9 00 42 42 B 72 Note 1 104 Note 5
10 00 43 52 R 73 Note 1 105 Note 5
11 03, Note 7 44 2D - 74 Note 1 106 Note 5
12 02, Note 8 45 35 5 75 Note 1 107 Note 5
13 00 46 37 7 76 Note 1 108 Note 5
14 00 47 45 E 77 Note 1 109 Note 5
15 00 48 30 0 78 Note 1 110 Note 5
16 C8 49 41, Note 4 A 79 Note 1 111 Note 5
17 C8 50 50, Note 4 P 80 Note 1 112 Note 5
18 00 51 5A, Note 4 Z 81 Note 1 113 Note 5
19 00 52 20, Note 4 82 Note 1 114 Note 5
20 41 A 53 20, Note 4 83 Note 1 115 Note 5
21 56 V 54 20 84 Note 2 116 Note 5
22 41 A 55 20 85 Note 2 117 Note 5
23 47 G 56 30 0 86 Note 2 118 Note 5
24 4F O 57 30 0 87 Note 2 119 Note 5
25 20 58 30 0 88 Note 2 120 Note 5
26 20 59 30 0 89 Note 2 121 Note 5
27 20 60 05 90 Note 2 122 Note 5
28 20 61 1E 91 Note 2 123 Note 5
29 20 62 00 92 00 124 Note 5
30 20 93 00 125 Note 5
31 20 94 00 126 Note 5
32 20 127 Note 5
7
AVAGO HFBR-57E0xxZ
YYWW
Country of Origin
13.80.1 13.40.1
[0.5410.004] [0.5280.004]
13.00.2
8.50.1
[0.5120.008]
[0.3350.004]
TX RX
AREA
FOR
PROCESS
PLUG
DIMENSIONS ARE IN MILLIMETERS (INCHES)
6.6
[0.261]
13.50
[0.53]
14.8MAX. UNCOMPRESSED
[0.583]
Figure 7. Module Drawing
8
X
Y
34.5
10
3x
10x 1.05 0.01 7.2 7.1
0.1 L X A S 2.5 0.85 0.05
16.25
MIN. PITCH 1 0.1 S X Y
2.5
B A 1
PCB
EDGE 3.68
5.68 20
PIN 1
8.58 2x 1.7 8.48
11.08 11.93
16.25 9.6
14.25
REF .
4.8
11
10
SEE DETAIL 1
2.0 9x 0.95 0.05
11x 11x 2.0 0.1 L X A S
26.8 5 2
3 10
3x
41.3
42.3
5
3.2
0.9 20x 0.5 0.03
0.06 L A S B S
PIN 1 20 LEGEND
10.93 10.53 1. PADS AND VIAS ARE CHASSIS GROUND
11.93
9.6
0.8 2. THROUGH HOLES, PLATING OPTIONAL
TYP.
11 3. HATCHED AREA DENOTES COMPONENT
10 AND TRACE KEEPOUT (EXCEPT
CHASSIS GROUND)
4. AREA DENOTES COMPONENT
KEEPOUT (TRACES ALLOWED)
4
2 0.005 TYP. DIMENSIONS ARE IN MILLIMETERS
2x 1.55 0.05
0.06 L A S B S
0.1 L A S B S DETAIL 1
9
1.70.9
[.07.04]
3.50.3
[.14.01]
41.730.5
PCB
[1.64.02]
AREA
BEZEL FOR
PROCESS
PLUG
15MAX
.59
CAGE
ASSEMBLY
15.250.1
[.600.004] 10.40.1
12.4REF
[.410.004]
.49
10REF
1.15REF
9.8MAX .39
.05 TO PCB
.39 16.250.1MIN PITCH
BELOW PCB
0.40.1 [.640.004]
[.020.004]
BELOW PCB
MSA-SPECIFIED BEZEL
10
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each
parameter in isolation, all other parameters having values within the recommended operating conditions. It should
not be assumed that limiting values of more than one parameter can be applied to the product at the same time.
Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter Symbol Minimum Typical Maximum Units Notes
Storage Temperature TS -40 +100 C
Supply Voltage VCC -0.5 3.63 V
Data Input Voltage VI -0.5 VCC V
Differential Input Voltage (p-p) VD 2.4 V 1
Output Current IO 50 mA
11
Notes:
1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protec-
tion circuit.
2. The data outputs are terminated with 50: .
The Loss of Signal output is terminated with 50 : connected to a pull-up resistor of 4.7 K: tied to VCC.
3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant
current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and con-
ducted or emitted to neighboring circuitry.
4. This is the receiver supply current measured in mA.
5a. The power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current.
5b. The power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus the sum of the products
of the output voltages and currents.
6a. Differential Output Voltage is internally ac coupled. The Loss of Signal low and high voltages are measured with load condition as mentioned
in note 2.
6b. Data and Data-bar outputs are squelched at LOS assert level. When the received light drops below LOS assert point, it will force receiver data
and data-bar to go to steady PECL levels High and Low respectively.
7. The data output rise and fall times are measured between 20% and 80% levels.
Notes:
8. These optical power values are measured with the following conditions:
The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wave-
length LEDs. The actual degradation observed in Avagos 1300 nm LED products is < 1 dB, as specified in this data sheet. Over the specified
operating voltage and temperature ranges. With 25 MBd (12.5 MHz square-wave), input signal.
At the end of one meter of noted optical fiber with cladding modes removed. The average power value can be converted to a peak power
value by adding 3 dB. Higher output optical power transmitters are available on special request. Please consult with your local Avago sales
representative for further details.
9. The relationship between Full Width Half Maximum and RMS values for Spectral Width is derived from the assumption of a Gaussian shaped
spectrum which results in a 2.35 X RMS = FWHM relationship.
10. The optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input
signal. The ANSI T1E1.2 committee has designated the possibility of defining an eye pattern mask for the transmitter optical output as an item
for further study. Avago will incorporate this requirement into the specifications for these products if it is defined. The HFBR-57E0 products
typically comply with the template requirements of CCITT (now ITU-T) G.957 Section 3.2.5, Figure 2 for the STM- 1 rate, excluding the optical
receiver filter normally associated with single mode fiber measurements which is the likely source for the ANSI T1E1.2 committee to follow in
this matter.
12
Notes:
11a. Systematic Jitter contributed by the transmitter is defined as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic
Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square-wave), 223- 1 psuedorandom data pattern input signal.
11b. Duty Cycle Distortion contributed by the transmitter is measured at the 50% threshold of the optical output signal using an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal.
11c. Data Dependent Jitter contributed by the transmitter is specified with the FDDI test pattern described in FDDI PMD Annex A.5.
12a. Random Jitter contributed by the transmitter is specified with a 155.52 MBd (77.5 MHz square-wave) input signal.
12b. Random Jitter contributed by the transmitter is specified with an IDLE Line State, 125 MBd (62.5 MHz square-wave) input signal. See Applica-
tion Information - Transceiver Jitter Performance Section of this data sheet for further details.
Notes:
13a. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal character-
istics are present per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to
the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal
to 1 x 10-10.
- At the Beginning of Life (BOL)
- Over the specified operating temperature and voltage ranges
- Input is a 155.52 MBd, 223-1 PRBS data pattern with 72 1 s and 72 0s inserted per the CCITT (now ITU-T) recommendation G.958 Appendix
I.
- Receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. The actual test data window time-width
is set to simulate the effect of worst case optical input jitter based on the transmitter jitter values from the specification tables. The test
window time-width is 3.32 ns.
- Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave, input signal to simulate any cross-talk present between the transmitter
and receiver sections of the transceiver.
13
13b. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are
present per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum
level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal to 2.5 x 10-10.
At the Beginning of Life (BOL)
Over the specified operating temperature and voltage ranges
Input symbol pattern is the FDDI test pattern defined in FDDI PMD Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle base-line
wander effect of 50 kHz. This sequence causes a near worst case condition for inter-symbol interference.
Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum allowed
eye-opening presented to the FDDI PHY PM_Data indication input (PHY input) per the example in FDDI PMD Annex E. This minimum window
time-width of 2.13 ns is based upon the worst case FDDI PMD Active Input Interface optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns)
and RJ (0.76 ns) presented to the receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter condition requires exacting control over DCD, DDJ and RJ jitter components that
is difficult to implement with production test equipment. The receiver can be equivalently tested to the worst case FDDI PMD input jitter condi-
tions and meet the minimum output data window time-width of 2.13 ns. This is accomplished by using a nearly ideal input optical signal (no DCD,
insignificant DDJ and RJ) and measuring for a wider window time-width of 4.6 ns. This is possible due to the cumulative effect of jitter components
through their superposition (DCD and DDJ are directly additive and RJ components are rms additive). Specifically, when a nearly ideal input optical
test signal is used and the maximum receiver peak-to-peak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum
window time-width becomes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window time-width of 4.6 ns guarantees
the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Avago receiver.
Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present between
the transmitter and receiver sections of the transceiver.
14a. All conditions of Note 13a apply except that the measurement is made at the center of the symbol with no window time- width.
14b. All conditions of Note 13b apply except that the measurement is made at the center of the symbol with no window time-width.
15a. Systematic Jitter contributed by the receiver is defined as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is
measured at 50% threshold using a 155.52 MBd (77.5 MHz square- wave), 223-1 psuedorandom data pattern input signal.
15b Duty Cycle Distortion contributed by the receiver is measured at the 50% threshold of the electrical output signal using an IDLE Line State,
125 MBd (62.5 MHz square-wave), input signal. The input optical power level is -20 dBm average.
15c. Data Dependent Jitter contributed by the receiver is specified with the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The input
optical power level is -20 dBm average.
16a. Random Jitter contributed by the receiver is specified with a 155.52 MBd (77.5 MHz square- wave) input signal.
16b. Random Jitter contributed by the receiver is specified with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. The input optical
power level is at maximum PIN MIN (W). See Application Information - Transceiver Jitter Section for further information.
17. This value is measured during the transition from low to high levels of input optical power.
18. This value is measured during the transition from high to low levels of input optical power. At Loss of Signal assert, the receiver outputs Data
Out and Data Out Bar go to steady PECL levels High and Low respectively.
19. The Loss of Signal output shall be de-asserted within 100 s after a step increase of the Input Optical Power.
20. Loss of Signal output shall be asserted within 350 s after a step decrease in the Input Optical Power. At Loss of Signal Assert, the receiver
outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively.
21. The HFBR-57E0 transceiver complies with the requirements for the trade-offs between center wavelength, spectral width, and rise/fall times
shown in Figure 3. This figure is derived from the FDDI PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the description in
ANSI T1E1.2 Revision 3. The interpretation of this figure is that values of Center Wavelength and Spectral Width must lie along the appropriate
Optical Rise/Fall Time curve.
14
Ordering Information
1300 nm LED (Operating Case Temperature 0 to +70 C)
HFBR-57E0LZ Standard de-latch
HFBR-57E0PZ Bail de-latch
Handling Precaution
The HFBR-57E0xxZ is a pluggable module and is NOT designed for aqueous wash, IR reflow or wave soldering pro-
cesses.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0456EN
AV02-2810EN - Januaray 20, 2011