HDL PROGRAMMING

VERILOG VHDL
D FLIP FLOP:
module dflipflop(q,d,clk,reset); library ieee;
output q; use ieee.std_logic_1164.all;
input d,clk,reset; entity dff is
reg q; port(d,clk:in bit;q:inout bit:='0';qb:out bit:='1');
always @(posedge clk ) end dff;
if (reset) architecture behaviour of dff is
q= 1'b0; begin
else process(clk,d)
q=d; begin
endmodule if(clk='1' and clk'event)then
q<=d;
end if;
end process;
qb<=not q;
end behaviour;

JK FLIP FLOP:
library ieee;
module jjjjjjj(j, k, clk, q); use ieee.std_logic_1164.all;
input j, k, clk; entity jk is
output q; port(clk,j,k:in std_logic;q:inout
reg q; std_logic;qb:out std_logic);
always @(posedge clk) end jk;
case({j,k}) architecture behaviour of jk is
{1'b0,1'b0}:q=q; begin
{1'b0,1'b1}:q=1'b0; process(clk,j,k)
{1'b1,1'b0}:q=1'b1; begin
{1'b1,1'b1}:q=~q; if(clk='1' and clk'event)then
endcase if(j='0' and k='0')then
endmodule q<=q;
end if;
elsif(j='0' and k='1')then
q<='0';
elsif(j='1' and k='0')then
q<='1';
elsif(j='1' and k='1')then
q<=not q;
end if;
end process;qb<=not q;end behaviour;
T FLIP FLOP:
module tfftff(t,clk,reset,q); library IEEE;
input t,clk,reset; use IEEE.STD_LOGIC_1164.ALL;
output q; entity T_FF is
reg q; port( T: in std_logic;
always@(posedge clk) Clock: in std_logic;
if(reset) Q: out std_logic);
begin end T_FF;
q=1'b0; architecture Behavioral of T_FF is
end signal tmp: std_logic;
else begin
begin process (Clock)
q=~t; begin
end if Clock'event and Clock='1' then
endmodule if T='0' then
tmp <= tmp;
elsif T='1' then
tmp <= not (tmp);
end if;
end if;
end process;
Q <= tmp;
end Behavioral;

SR FLIPFLOP:

module SR_flipflop(q,q1,r,s,clk); library ieee;

output q,q1; use ieee. std_logic_1164.all;
input r,s,clk; use ieee. std_logic_arith.all;
reg q,q1; use ieee. std_logic_unsigned.all;
initial entity SR_FF is
begin PORT( S,R,CLOCK: in std_logic;
q=1'b0; q1=1'b1; Q, QBAR: out std_logic);
end end SR_FF;
always @(posedge clk) Architecture behavioral of SR_FF is
begin begin
case({s,r}) PROCESS(CLOCK)
{1'b0,1'b0}: begin q=q; q1=q1; end variable tmp: std_logic;
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end begin
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end if(CLOCK='1' and CLOCK'EVENT) then
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end if(S='0' and R='0')then
endcase tmp:=tmp;
end elsif(S='1' and R='1')then
endmodule tmp:='Z';
elsif(S='0' and R='1')then
 tmp:='0';
else
tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;

SERIAL IN SERIAL OUT

module SISOO(in,q,clk,rst); library ieee;

input in; use ieee.std_logic_1164.all;
input clk,rst; use ieee.std_logic_arith.all;
output q; entity siso is
reg q,w1,w2,w3; port(s,clk:in bit;
always@(posedge clk,posedge rst) qo:out bit);
if(rst) end siso;
q=1'b0; architecture siso_pgm of siso is
else signal q1,q2,q3:bit;
begin component dff1 is
w1=in; port(d,clk:in bit;
w2=w1; q:out bit);
w3=w2; end component;
q=w3; begin
end d1:dff1 port map(s,clk,q1);
endmodule d2:dff1 port map(q1,clk,q2);
d3:dff1 port map(q2,clk,q3);
d4:dff1 port map(q3,clk,qo);
end siso_pgm;
entity dff1 is
port(d,clk:in bit;
q:out bit);
end dff1;
architecture dff_pgm of dff1 is
begin
process(d,clk)
begin
if(clk='0' and clk'event)then
q<=d;
end if;
end process;
end dff_pgm
SERIAL IN PARALLEL OUT :
module sipo( din ,clk ,reset ,dout );
output [3:0] dout ; library ieee;
wire [3:0] dout ; use ieee.std_logic_1164.all;
input din ; entity sipo is
wire din ; port(clk:in bit;s:in bit;
input clk ; q:inout bit_vector(3 downto 0));
wire clk ; end sipo;
input reset ; architecture sipo_pgm of sipo is
wire reset ; component dff1 is
reg [3:0]s; port(d,clk:in bit;
always @ (posedge (clk)) q:out bit);
begin end component;
if (reset) begin
s = 0; d1:dff1 port map(s,clk,q(3));
else begin d2:dff1 port map(q(3),clk,q(2));
s[3] = din; d3:dff1 port map(q(2),clk,q(1));
s[2] = s[3]; d4:dff1 port map(q(1),clk,q(0));
s[1] = s[2]; end sipo_pgm;
s[0] = s[1]; entity dff1 is
end port(d,clk:in bit;
end q:out bit);
assign dout = s; end dff1;
endmodule architecture dff_pgm of dff1 is
begin
process(d,clk)
begin
if(clk='1' and clk'event)then
q<=d;
end if;
end process;
end dff_pgm;

PARELLEL IN PARELLEL OUT:

module pppiiiooo(sout,sin,clk); library ieee;
output [3:0]sout; use ieee.std_logic_1164.all;
input [3:0]sin; entity pipo is
input clk; port(clk:in bit;
dflipflop u1(sout[0],sin[0],clk); s:in bit_vector(3 downto 0);
dflipflop u2(sout[1],sin[1],clk); q:inout bit_vector(3 downto 0));
dflipflop u3(sout[2],sin[2],clk); end pipo;
dflipflop u4(sout[3],sin[3],clk); architecture pipo_pgm of pipo is
endmodule component dff1 is
port(d,clk:in bit;
module dflipflop(q,d,clk,reset); q:out bit);
output q; end component;
input d,clk,reset; begin
reg q; d1:dff1 port map(s(0),clk,q(0));
always @(posedge clk ) d2:dff1 port map(s(1),clk,q(1));
if (reset) d3:dff1 port map(s(2),clk,q(2));
q= 1'b0; d4:dff1 port map(s(3),clk,q(3));
else end pipo_pgm;
q=d; entity dff1 is
endmodule port(d,clk:in bit;
q:out bit);
end dff1;
architecture dff_pgm of dff1 is
begin
process(d,clk)
begin
if(clk='1' and clk'event)then
q<=d;
end if;
end process;
end dff_pgm;

PARALLEL IN SERIAL OUT:

module pppiiissssii(clk,rst,a,out); library ieee;
input clk,rst; use ieee.std_logic_1164.all;
input [3:0]a; use ieee.std_logic_arith.all;
output out; entity piso is
reg out; port(a:in bit_vector(3 downto 0);
reg [3:0]temp; s,clk:bit;
always@(posedge clk,posedge rst) y:out bit);
begin end piso;
if(rst==1'b1) architecture piso_pgm of piso is
begin signal q0,x,b,c,q1,d,e,f,q2,g,h,i,sb:bit;
out=1'b0; component dff1 is
temp=a; port(d,clk:in bit;
end q:out bit);
else end component;
begin begin
out=temp[0]; sb<=not (s);
temp=temp>>1'b1; d1:dff1 port map(a(0),clk,q0);
end x<=s and q0;
end b<=(sb and a(1));
endmodule c<=x or b;
d2:dff1 port map(c,clk,q1);
 d<=q1 and s;
e<=(sb and a(2));
f<=d or e;
d3:dff1 port map(f,clk,q2);
g<=q2 and s;
h<=(sb and a(3));
i<=g or h;
d4:dff1 port map(i,clk,y);
end piso_pgm;
entity dff1 is
port(d,clk:in bit;
q:out bit);
end dff1;
architecture dff_pgm of dff1 is
begin
process(d,clk)
begin
if(clk='0' and clk'event)then
q<=d;
end if;
end process;
end dff_pgm;

UPDOWN COUNTER: library IEEE;

module uodown(out,x,clk,data,reset ); use IEEE.STD_LOGIC_1164.ALL;
input [3:0]data; use IEEE.STD_LOGIC_ARITH.ALL;
input x,clk,reset; use IEEE.STD_LOGIC_UNSIGNED.ALL;
output[3:0]out;
reg[3:0]out; entity Counter_VHDL is
always@(posedge clk) port( Number: in std_logic_vector(0 to 3);
if(reset==1) Clock: in std_logic;
out=3'b000; Load: in std_logic;
else if(x==1) Reset: in std_logic;
out=out+1; Direction: in std_logic;
else Output: out std_logic_vector(0 to 3) );
out=out-1; end Counter_VHDL;
endmodule
architecture Behavioral of Counter_VHDL is
signal temp: std_logic_vector(0 to 3);
begin
process(Clock,Reset)
begin
if Reset='1' then
temp <= "0000";
elsif ( Clock'event and Clock='1') then
 if Load='1' then
temp <= Number;
elsif (Load='0' and Direction='0') then
temp <= temp + 1;
elsif (Load='0' and Direction='1') then
temp <= temp - 1;
end if;
end if;
end process;
Output <= temp;
end Behavioral;

UPCOUNTER
library ieee;
module counter (C, ALOAD, D, Q); use ieee.std_logic_1164.all;
input C, ALOAD; use ieee.std_logic_unsigned.all;
input [3:0] D; entity vhdl_binary_counter is
output [3:0] Q; port(C, CLR : in std_logic;
reg [3:0] tmp; Q : out std_logic_vector(3 downto 0));
end vhdl_binary_counter;
always @(posedge C or posedge ALOAD) architecture bhv of vhdl_binary_counter is
begin signal tmp: std_logic_vector(3 downto 0);
if (ALOAD) begin
tmp = D; process (C, CLR)
else begin
tmp = tmp + 1'b1; if (CLR=1) then
end tmp <= "0000";
assign Q = tmp; elsif (Cevent and C=1) then
endmodule tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end bhv;
DOWN COUNTER library ieee;
use ieee.std_logic_1164.all;
module counter (C, S, Q); use ieee.std_logic_unsigned.all;
input C, S;
output [3:0] Q; entity counter is
reg [3:0] tmp; port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
always @(posedge C) end counter;
begin architecture archi of counter is
if (S) signal tmp: std_logic_vector(3 downto 0);
tmp = 4'b1111; begin
else process (C)
tmp = tmp - 1'b1; begin
end if (C'event and C='1') then
assign Q = tmp; if (S='1') then
endmodule tmp <= "1111";
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;