Chapter 7

Digital System Design

Figure 7.1. Tri-state driver.
Figure 7.2. A digital system with k registers.
Figure 7.3. Details for connecting registers to a bus.
Figure 7.4. Using multiplexers to implement a bus.
Figure 7.5. Code for an n-bit register of the type in Figure 7.2.
 module trin (Y, E, F);
parameter n = 8;
input [n-1:0] Y;
input E;
output wire [n-1:0] F;

assign F = E ? Y : 'bz;

endmodule

Figure 7.6. Code for an n-bit tri-state module.

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Figure 7.7. A digital system like the one in Figure 7.2.

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Figure 7.8. Using multiplexers to implement a bus.

Figure 7.9. A digital system that implements a simple processor.
Table 7.1. Operations performed in the processor.
 T0 T 1 T 2 T3

y0 y1 y2 y3
2-to-4 decoder
w1 w0 En

Q1 Q0
Clock
Up-counter
Clear Reset

Figure 7.10. A part of the control circuit for the processor.

 I0 I1 I2 I3 X 0 X1 X2 X3 Y0 Y1 Y2 Y3

y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3

2-to-4 decoder 2-to-4 decoder 2-to-4 decoder

w1 w0 En w1 w0 En w1 w0 En

1 1 1

Clock
Function Register
FR in

f1 f0 Rx 1 Rx 0 Ry 1 Ry 0

Function

Figure 7.11. The function register and decoders.

Table 7.2. Control signals asserted in each operation/time step.
 module upcount (Clear, Clock, Q);
input Clear, Clock;
output reg [1:0] Q;

always @(posedge Clock)

if (Clear)
Q <= 0;
else
Q <= Q + 1;

endmodule

Figure 7.12. A two-bit up-counter with synchronous reset.

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Figure 7.13. Code for the processor.

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Figure 7.14. Alternative code for the processor.

Figure 7.15. Timing simulation for the Verilog code in Figure 7.14.
 B = 0;
while A 0 do
if a 0 = 1 then
B = B + 1;
end if;
Right-shift A ;
end while;

Figure 7.16 Pseudo-code for the bit counter.

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Figure 7.17. ASM chart for the pseudo-code in Figure 7.16.

Figure 7.18. Datapath for the ASM chart in Figure 7.17.
 Reset

S1
LB

0
0 1
s s

1
S2 S3
EA Done

1
EB z

0
a0

Figure 7.19. ASM chart for the bit counter control circuit.
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Figure 7.20. Verilog code for the bit-counting circuit.

Figure 7.21. Simulation results for the bit-counting circuit.
 Decimal Binary
13 110 1 Multiplicand
11 1 0 1 1 Multiplier
13 1101
13 1 101
143 00 00
110 1
1 0 001111 Product

(a) Manual method

P = 0;
for i = 0 to n 1 do
if bi = 1 then
P = P+ A;
end if;
Left-shift A ;
end for;

(b) Pseudo-code

Figure 7.22. An algorithm for multiplication.

Figure 7.23. ASM chart for the multiplier.
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Figure 7.24. Datapath circuit for the multiplier.

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Figure 7.25. ASM chart for the multiplier control circuit.

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Figure 7.26. Verilog code for the multiplier circuit.

Figure 7.27. Simulation results for the multiplier circuit.
 15 00001111 Q
9 140 B 1001 100 01100 A
9 1001
50 10 001
45 10 01
5 10000
1001
1110
(a) An example using decimal numbers 1001
101 R

(b) Using binary numbers

R = 0;
for i = 0 to n 1 do
Left-shift R ||A ;
if R B then
qi = 1 ;
R = R B ;
else
qi = 0 ;
end if;
end for;

(c) Pseudo-code

Figure 7.28. An algorithm for division.

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Figure 7.29. ASM chart for the divider.

 0
n LA DataA EB DataB
Rsel 1 0
n n

LR L L
Left-shift w Left-shift E
ER E EA E Register
register register

n n n
an 1 B
A

EQ E Left-shift w cout + cin 1

register

n n

Clock
Q R

Figure 7.30. Datapath circuit for the divider.

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Figure 7.31. ASM chart for the divider control circuit.

 B 1001 10001100 A

Clock cycle R rr 0 A/ Q

Load A, B 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0
0 Shift left 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0
1 Shift left, Q 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0
2 Shift left, Q 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0
3 Shift left, Q 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
4 Shift left, Q 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0
5 Subtract, Q 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1
6 Subtract, Q 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1
7 Subtract, Q 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1
8 Subtract, Q 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1

Figure 7.32. An example of division using n = 8 clock cycles.

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Figure 7.33. ASM chart for the enhanced divider control circuit.
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Figure 7.34. Datapath circuit for the enhanced divider.

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Figure 7.35. Verilog code for the divider circuit.

Figure 7.36. Simulation results for the divider circuit.
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Figure 7.37. An algorithm for finding the mean of k numbers.

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Figure 7.38. Datapath circuit for the mean operation.

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Figure 7.39. ASM chart for the mean operation control circuit.
 for i = 0 to k 2 do
A = Ri ;
for j = i + 1 to k 1 do
B = Rj ;
if B < A then
Ri = B ;
Rj = A ;
A = Ri ;
end if ;
end for;
end for;

Figure 7.40. Pseudo-code for the sort operation.

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Figure 7.41. ASM chart for the sort operation.

 DataIn
ABmux n

0 1 WrInit
n RData

Rin0 E Rin1 E Rin2 E Rin3 E

R0 R1 R2 R3

0 1 2 3 Imux

ABData

Ain E Bin E Rd

Clock n

DataOut
1 0 Bout <
A B

BltA

Figure 7.42. A part of the datapath circuit for the sort operation.
 0
2
2

LI L R LJ L R
EI E Counter EJ E Counter
Q Q
Ci Cj
Clock 2
= k2 zi
2

Csel 0 1
= k1 zj
Cmux
2
2
RAdd

Int 0 1

Imux 2 y0 Rin0
w0, w1 y1 Rin1
y2 Rin2
WrInit
En y3 Rin3
Wr
2-to-4 decoder

Figure 7.43. A part of the datapath circuit for the sort operation.
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Figure 7.44. ASM chart for the control circuit.

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Figure 7.45. Verilog code for the sorting circuit.

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Figure 7.46. Simulation results for the sort operation.

 ff ff

ff ff

ff ff

ff ff

Clock

ff ff

ff ff

ff ff

ff ff

Figure 7.47. An H tree clock distribution network.

 t Data

Chip package pin

Data

A
D Q Out

B
Clock

t Clock t od

Figure 10.48. A flip-flop in an integrated circuit.

Clock
3ns
Data
4.5ns
A
1.5ns
B

Figure 7.49. Flip-flop timing in a chip.

 Data D Q D Q Data
(asynchronous) (synchronous)

Clock Q Q

Figure 7.50. Asynchronous inputs.

 VDD

R
VDD
S
Data
R

Data

(a) Single-pole single-throw switch VDD

(b) Single-pole double-throw switch with a basic SR latch

Figure 7.51. Switch debouncing circuit.

 Q = 0;
R = A;
while ((R B) > 0) do
R = R B ;
Q = Q+ 1;
end while ;

Figure P7.1. Pseudo-code for integer division.

 5V

4 8
Ra
Clock 3 7
(output) 555
Rb
Timer
2 6
C1
1 5

0.01 F

Figure P7.2. The 555 programmable timer chip.