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9D57106c ASIC Design

The document appears to be an exam for a course on ASIC design. It lists 8 questions covering various topics in ASIC design including standard cell vs full custom ASICs, EDGA design flow, programmable logic devices, gate-array cell design, design methodologies/tools, using transistors as resistors, VHDL code for an adder, Xilinx and Altera design tools, boundary scan testing, automatic test pattern generation, floor planning, routing system partition, FPGA partitioning, and special routing circuit extraction. Students are instructed to answer any 5 of the 8 questions.

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34 views1 page

9D57106c ASIC Design

The document appears to be an exam for a course on ASIC design. It lists 8 questions covering various topics in ASIC design including standard cell vs full custom ASICs, EDGA design flow, programmable logic devices, gate-array cell design, design methodologies/tools, using transistors as resistors, VHDL code for an adder, Xilinx and Altera design tools, boundary scan testing, automatic test pattern generation, floor planning, routing system partition, FPGA partitioning, and special routing circuit extraction. Students are instructed to answer any 5 of the 8 questions.

Uploaded by

subbu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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www.jntuworld.com www.android.jntuworld.com www.jwjobs.

net

Code: 9D57106c

M.Tech - I Semester Regular & Supplementary Examinations, April/May 2013


ASIC DESIGN
(Common to VLSIS, VLSISD, VLSI and VLSID)
Time: 3 hours Max Marks: 60
Answer any FIVE questions
All questions carry equal marks
*****
1 (a) Differentiate between the standard cell based ASICs and full custom ASIC.
(b) Give design of standard cell with proper sizing for two input NOR gate and respective
layout diagram.

2 (a)
(b)
Explain the EDGA design flow with each level in the design.
With a diagram explain programmable logic devices (PLDs) ASIC.

L D
3

4 (a)
(b)
Explain about gate-array cell design. R
Explain different design methodologies and design tools related to ASIC design.

O
Explain how transistor can be use as resistor with proper characteristics.

5 (a)
(b)
W
Write a VHDL code for An 8-bit ripple-carry adder.

U
Write features of XILINX and ALTERA EPGA design tools.

6 (a)
(b)
T
Describe in detail about boundary scan test.
Explain automatic test pattern generation.

N
J
7 Discuss the following related to ASIC construction:
(a) Floor planning.
(b) Routing system partition.

8 (a) Explain partitioning methods and global routing related to FPGA partitioning.
(b) Write short note on special routing circuit extraction.

*****

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