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ASic Design

Standard-cell based ASICs use predefined logic cells arranged in a regular structure. There are two main types of ASICs - full-custom ASICs which offer highest performance but require more design time and cost, and standard-cell ASICs which use predefined cells and have lower design time and cost. The ASIC design flow involves logical design steps like synthesis followed by physical design steps like placement and routing.

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Manpreet Singh
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234 views14 pages

ASic Design

Standard-cell based ASICs use predefined logic cells arranged in a regular structure. There are two main types of ASICs - full-custom ASICs which offer highest performance but require more design time and cost, and standard-cell ASICs which use predefined cells and have lower design time and cost. The ASIC design flow involves logical design steps like synthesis followed by physical design steps like placement and routing.

Uploaded by

Manpreet Singh
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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NTRODUCTION TO ASICs

Key concepts: The difference between full-custom and semicustom


ASICs • The difference between standard-cell, gate-array, an
programmable ASICs • ASIC design flow • ASIC cell library

ASIC (“a-sick”) is an Application-Specific Integrated Circuit


rigin of ASICs: the standard parts , initially used to design
microelectronic systems , were gradually replaced with a combination
lue logic , custom ICs , dynamic random-access memory ( DRAM
nd static RAM ( SRAM )
pplication-specific standard products ( ASSPs ) are a cross betwe
andard parts and ASICs
Types of ASICs
Full-Custom ASICs
Full-custom offers the highest performance and lowest part cost (smallest die size) with
he
disadvantages of increased design time, complexity, design expense, and highest risk
Examples of full-custom ICs or ASICs are requirements for high-voltage (automobile),
analog/digital (communications), or sensors and actuators

tandard-Cell–Based ASICs

A cell based ASIC die with a single


cell area together with four fixed
blocks
Design flow

ASIC design flow. Steps 1–4 are logical design , and


steps 5–9 are physical design
Full custom design and ASICs

n Full custom design


u high performance and high design cost

u examples: PC and workstation CPU

n ASICs
u low design cost and compromised performance

u examples: an I/O circuit or a special DSP chip


ASIC hardware architectures

n pre-design cells and functional blocks


n uniformed circuits and devices
n uniformed interconnect structures
n programmable interconnects
Cell-based ASIC ( CBIC —“sea-bick”)

Standard cells
Possibly megacells , megafunctions , full-custom blocks , system
level macros
( Slms ), fixed blocks , cores , or functional standard blocks ( fsbs
)
All mask layers are customized—transistors and interconnect
Custom blocks can be embedded
Manufacturing lead time is about eight weeks
Gate-array–based ASICs

A gate array, masked gate array, MGA, or pre-diffused array uses


macros ( books ) to
reduce turnaround time and comprises a base array made from a base
cell or primitive
cell
Types of gate array – based ASIC:
Channeled gate arrays
Channel less gate arrays
Structured gate arrays
Channeled gate array

A channeled gate array


• Only the interconnect is customized
• The interconnect uses predefined spaces between
rows of base
cells
• Manufacturing lead time is between two days and
two weeks
Channelless gate array

channelless gate array ( channel-


channel-free gate array , sea-
sea-of-
of-gates array , or SOG
array)
• Only some (the top few) mask layers are customized—
customized—the interconnect
• Manufacturing lead time is between two days and two weeks
Structured gate array

An embedded gate array or structured gate array ( masterslice or masterimage )


• Only the interconnect is customized
• Custom blocks (the same for each design) can be embedded
• Manufacturing lead time is between two days and two weeks
Programmable logic devices

Programmable logic device ( PLD )


No customized mask layers or logic cells
Fast design turnaround
A single large block of programmable interconnect
A matrix of logic macro cells that usually consist of programmable
programmable array logic
followed
by a flip-
flip-flop or latch
Field-programmable gate arrays

Field-programmable gate array ( FPGA ) or complex PLD


None of the mask layers are customized
A method for programming the basic logic cells and the interconnect
interconnect
The core is a regular array of programmable basic logic cells that can implement
combinational as well as sequential logic (flip-
(flip-flops)
A matrix of programmable interconnect surrounds the basic logic
logic cells
Programmable I/O cells surround the core
Design turnaround is a few hours
Design entry . using a hardware description language ( VHDL ) or
Schematic entry
Logic synthesis . produces a netlist —logic cells and their connections
System partitioning . divide a large system into functional blocks
Prelayout simulation . check to see if the design functions correctly
Floorplanning . arrange the blocks of the netlist on the chip
Placement . decide the locations of cells in a block
Routing . make the connections between cells and blocks
Extraction . determine the resistance and capacitance of the interconnect
Postlayout simulation . check to see the design still works with the added
Loads of the interconnect
ASIC cell libraries

Design kit from the ASIC vendor


Usually a phantom library —the cells are empty boxes, or phantoms , you hand
off your design to the ASIC vendor and they perform phantom instantiation
(Synopsys CBA)

Asic-vendor library from a library vendor


Involves a buy-
buy-or-
or-build decision
You need a qualified cell library (qualified by the ASIC foundry
customer-owned tooling ( COT ,
If you own the masks (the tooling ) you have a customer-
pronounced “see-
see-oh-
oh-tee”
tee”) solution (which is becoming very popular)

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