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Gate Level Minimization2

§ Don't care conditions represent unspecified minterms in a Boolean function. They are represented by X in a K-map table and provide degrees of freedom for optimizing logic circuits. § An example is given of simplifying a Boolean function F(w,x,y,z) that has don't care conditions represented by Σ(0,2,5). § Don't care conditions play an important role in optimizing logic circuits by allowing functionally equivalent networks to be derived.

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55 views

Gate Level Minimization2

§ Don't care conditions represent unspecified minterms in a Boolean function. They are represented by X in a K-map table and provide degrees of freedom for optimizing logic circuits. § An example is given of simplifying a Boolean function F(w,x,y,z) that has don't care conditions represented by Σ(0,2,5). § Don't care conditions play an important role in optimizing logic circuits by allowing functionally equivalent networks to be derived.

Uploaded by

rajeshshisodiya
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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DON’T CARE CONDITIONS

§ Functions that have unspecified output for some input combinations


are called incompletely specified functions.
§ Unspecified minterms of a functions are called ‘don’t care’
conditions. We simply don’t care whether the value of 0 or 1 is
assigned to F for a particular minterm.
§ Don’t care conditions are represented by X in the K-Map table.

Ø Don’t care conditions play a central role in the specification


and optimization of logic circuits as they represent the degrees
of freedom of transforming a network into a functionally
equivalent one.

DON’T CARE CONDITIONS


Example: Simplify the Boolean function
F (w, x, y, z ) = Σ(1,3,7,11,15), dc( w, x, y, z) = Σ (0,2,5)

1
Implementing Logic Circuits with NAND
Example: F ( x, y, z ) = Σ(1,2,3,4,5,7)

F = ( F ' )' = (( xy'+ x ' y + z)' )'


F = xy'+ x' y + z = (( xy' )' ⋅ ( x ' y )' ⋅ ( z ' ))'

INVERT-OR NAND

NAND-OR gates 2-level NAND gates

Implementing Logic Circuits with NAND

2
Multi-Level Gate Implementation

AND-OR-INVERT Gate Implementation

3
OR-AND-INVERT Gate Implementation

EXCLUSIVE-OR FUNCTION
x ⊕ y = xy'+ x' y

( xy )' = ( x' + y' )

x ⊕ y = xy'+ x' y

4
Verilog Hardware Descriptive Language
• Verilog is language that describes the hardware of digital systems
in textual form.
• It can be used to represent logic diagrams, Boolean expressions,
and other more complex digital circuits.
• There are two applications of HDL processing: simulation and
synthesis.

1. Logic simulation: representation of the structure and behavior


of a digital system. A simulator interprets the HDL code and produces
an output that predicts the behavior of the hardware before it’s actually
fabricated.

2. Logic synthesis: process of deriving a list of components and their


interconnections from the system model described in HDL. This
process produces a database with instructions on how to fabricate
a piece of hardware.

SynaptiCAD
C:\SynaptiCad\Examples_Book\Book_Tutorials

Or you can go directly to the VeriLogger Tutorial:


Basic Verilog Simulation

5
//HDL Example 3-1

//Description of the simple circuit of Fig. 3-37


module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y; port list
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule

Circuit with delay in HDL


//HDL Example 3-2
//---------------------------------
//Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule

6
Stimulus to a design: test bench

//HDL Example 3-3


//----------------------
//Stimulus for simple circuit
module stimcrct;
reg A,B,C;
wire x,y;
circuit_with_delay cwd(A,B,C,x,y);
initial
begin
A = 1'b0; B = 1'b0; C = 1'b0;
#100
A = 1'b1; B = 1'b1; C = 1'b1;
#100 $finish;
end
endmodule

Simulation Output

7
Boolean Algebra in Verilog HDL
x = A + BC + B' D
y = B' C + BC ' D'

//HDL Example
//------------------------------
//Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D);
input A,B,C,D;
output x,y;
assign x = A | (B & C) | (~B & D);
assign y = (~B & C) | (B & ~C & ~D);
endmodule

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