UNIT II SPECIAL PURPOSE PROGRAMMABLE PERIPHERALS AND THEIR INTERFACING (9)

Programmable peripheral interface (8255) - 8251A USART - 8279 keyboard and display controller 8259
programmable Interrupt controller - 8257 DMA controller - 8254 programmable interval timer
Interfacing A/D Converter - D/A Converters.

Programmable peripheral interface (8255)

A PPI is a multiport device. The port may be programmed in a verity of ways as
required by the programmer. The device is very useful for interfacing peripheral devices.
It has three, 8-bit port.

Port A
Port B
Port C
Port C is further subdivided into two, 4-bit ports.
Port C upper
Port C lower
Each port can be programmed either as an input port or as an output port,by setting proper bits in
the control word.
This control word is written into a control word register (CWR).
CONTROL GROUPS OF 8255:
The 24 lines of I/O port is divided into 2 groups.
Group A
Group B
Each group contains one 8-bit port & a 4-bit port.
Group A Group B
Port A Port B
Port C upper Port C lower
The control word initialises the ports.

Mode of operation of 8255:

There are 2 basic modes of operation of 8255.
BSR Mode ( Bit Set Reset mode )
I/O Mode ( Input / Output mode )
BSR Mode:
In this mode, any of the 8-bits of Port C can be set or reset depending on bit B0 of the control
word. The bit to set or reset is selected by bit select flag B3, B2, B1 of the CWR.
I/O Mode:
In this mode,the 8255 works as programmable I/O ports.
There are three modes of operation of 8255 under I/O mode.
i.e.
Mode 0
Mode 1
Mode 2

Mode 0 Simple input / output

Mode 1 Strobed input / output
Mode 2 Bidirectional input / output
All these modes can be selected by programming a register internal to 8255 known as control
word register (CWR), which has two formats one for BSR mode and another for I/O mode.
Mode 0:
It is also known as basic Input / Output mode.
This mode provide simple Input / Output capability using each of the three ports.

Features of Mode 0:--

Two, 8-bit ports i.e. port A and port B & two,4-bit ports i.e. port C upper and port C
lower are avaliable. The two 4-bit ports of port C can be combinedly used as a 3 rd 8-
bit port.
Any port can be used as an input or output port.
Output ports are latched. But, input ports are not latched.
A maximum of 4 ports are avaliable. So that 16 I/O configurations are possible.
0 0 1 B1
0 1 0 B2
0 1 1 B3
1 0 0 B4
1 0 1 B5
1 1 0 B6
1 1 1 B7

Mode 1 :
This mode is also called strobed I/O mode.

In this mode port C is used for generating hand shake.

Signals to control the input or output action of port A or port B.

Features of Mode 1:
Two groups i.e. group A and group B are avaliable for strobe data transfer. Each groups
contains one 8-bit data I/O port, one 4-bit control port.
The 8-bit data port can be either used as input or output port.
Both the inputs and outputs are latched. Out of 8-bit port C i.e. PC0 to PC2 are used to
generate control signals for port B and PC3 to PC5 are used to generate control signals
for port A. The line PC6 and PC7 may be used as independent data lines.

Mode 2:
It is known as strobe bidirectional I/O mode.
Here only port A is available. In this mode 8255 acts as a bidirectional 8-bit port with
handshakes signal.

Features of mode 2:
Here only port A is available.
The 8-bit port A is bidirectional and additionally a 5-bit control port C is available.
Input and outputs are both latched.

Three I/O lines are available at port C i.e. PC0 to PC2.

The 5-bit control port C i.e. PC3 to PC7 is used for generating handshake signals for
8-bit data transfer on port A.

8251A USART

FEATURES OF 8251A (USART)

8251A is an universal synchronous & asynchronous communication

controller
supports standard asynchronous protocol with
5 to 8 bit character format
Odd, even or no parity generation & detection
Baud rate from DC to 19.2kbaud
False rate bit detection
Automatic break detect and handling
Has built in baud rate generator
Supports standard synchronous protocol with
5 to 8 bit character format
Internal or external character synchronization
Automatic sync insertion
Baud rate from dc to 64kbaud
Allows full duplex transmission & reception
Provides double buffering of data both in transmission section & in receiver
section
Provides error detection logic, which detects parity, overrun & framing errors
Has modern control logic, which supports basic data set control signals
Provides separate clock inputs for receiver & transmitter sections thus providing an
option of fixing different baud rates for transmitter & receiver section
Features

The 8251 is a programmable chip designed for synchronous and asynchronous serial data
communication

The INTEL 8251 is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter

(USART) designed for data communications

The 8251 is used as a peripheral device and is programmed by the CPU to operate using virtually any
serial data transmission technique

The USART accepts data characters from the CPU in parallel format and then converts them into a
continuous serial data stream for transmission

Simultaneously, it can receive serial data streams and convert them into parallel data character for
the CPU

The USART will signal the CPU whenever it can accept a new character for transmission or whenever it
has received a character for the CPU Description
The block diagram includes five section

Read/write Control Logic

Transmitter

Receiver

Data Bus Buffer and

Modem Control

Read/Write Control Logic

The control logic interfaces the chip with the processor, determines the functions of the chip according
to the control word in its register, and monitors the data flow

Transmitter

The transmitter section converts a parallel word received from the processor into serial bits and
transmits them over the TxD line to a peripheral

Receiver

receives serial bits from a peripheral, converts them into a parallel word, and transfers the word to the
P

Modem Control The modem control is used to establish data communication through modems over
telephone lines

Data Buffer

Control Register
Status Register

8279 keyboard and display controller

INTEL 8279 MICROPROCESSOR - KEYBOARD/DISPLAY CONTROLLER

The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088
microprocessor based system.

The important features of 8279 are,

Simultaneous keyboard and display operations.

Scanned keyboard mode. Scanned sensor mode.

8-character keyboard FIFO. 1 6-character display.

Right or left entry 1 6-byte display RAM.

Programmable scan timing.

Block diagram of 8279:

 The four major sections of 8279 are keyboard, scan, display and CPU interface.

Keyboard section:

The keyboard section consists of eight return lines RL0 RL7 that can be used to form the columns of a
keyboard matrix.

It has two additional input : shift and control/strobe. The keys are automatically debounced.

The two operating modes of keyboard section are 2-key lockout and N-key rollover.

In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO.

The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control
key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in
FIFO. The format of key code entry in FIFO for scan keyboard mode is,

In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the
condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.
Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3.

The output lines can be used either as a single group of eight lines or as two groups of four lines, in
conjunction with the scan lines for a multiplexed display.

The output lines are connected to the anodes through driver transistor in case of common cathode 7-
segment LEDs. The cathodes are connected to scan lines through driver transistors.

The display can be blanked by BD (low) line.

 The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of
the display RAM.

Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3.

In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

In encoded scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output.

The scan lines are common for keyboard and display.

The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a
multiplexed display, to turn ON/OFF.

CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor.

This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU.

It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register
of8279.

The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input
clock by an internal prescaler.

The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.
8259 programmable Interrupt controller