ience Birla Institute of Technology & S 1 Semester 2016-17 MEL G626 VLSI Test and Testability Test-1 (Closed Book) MM:20 Duration: 50 Min Date: 27/09/2016 Qi: (i) Why is it not possible to verify functionality of a chip exhaustively? Explain with suitable example. (1M) (ii) Explain the meaning of defect level 237.700 ppm am) (iii) What are the non-HDL assertions? Describe its types. aM) (iv) Explain the functional verification test coverage in brief aM) (v) Explain the any two advantages of bootstrapping in the verification process. aM) (vi) Explain the advantage of using emulation in the verification process. (aM) Q2: What are the possible ways in which stimulus can be generated for simulation based verification. Write an algorithm for stimulus generation ata single port of the Calculator 2. (3M) Q3: For a ‘calculator 2° use parameter biasing to pre-generated random test cases for 100 stimuli as per following requirements: (i) legal commands 90% of the time and illegal commands 10% of the time. (ii) Where any legal command such as add, sub, shift lefi and shift right are equally generated. (iii) For each port these command should be equally generated. (iv) The delay between command should be *0 cycle” for 50% command and *1 cycle” for remaining 50% commands. Write the template ‘file and randomization control parameters. @M) Q4: What are the differences between a golden vector test bench and cycle accurate reference model test bench verification environment? Describe the merits and demerits of both the self-checking test benches. (3M) QS: Explain the dynamic mapping mechanism to support vertical naming issues? QM) Q6: Explain the benefits of separation of HDL domain and test bench domain. Also using a suitable diagram explain the control flow interaction between HDL model and test-bench model in a separated C/C++ test bench. ° @M)Birla Institute of Technology & Science I Semester 2016-17 | G626 VLSI Test and Testability ‘Test 2 (Open Book) MM:20 Duration: 50 Min Date: 27/10/2016 MEI QI: Write a System Verilog program for a flip flop usi .Q' is zero and if clr=0 it performs a usual flip flop (positive edge tri Slogic’ data type such that if clr=1, the output ggered) operation. GM) Q2: Write a System Verilog program to generate a three dimensional array such that for any element [i] [] [k] should hold a value i+}+k. The code must also print this three dimensional array such that each row displays all ‘k’ values corresponding to each [i] [j] indices as shown below: # (O}[0]: ~ (Olt: fou}: -- - - (0)(3} ~ = # [10]: ~ OLY: ORE - ~ [BE # (2)[0]: ~ - (2) [2][2}: -- ~ PIB): Also write ‘itj+k? values for each elements. 6M) Q3: Write a System Verilog program using task such that a single call of same task should print all the values shown in the following initial block of same program. initial begin 5; #100 #10 #10a 10; aM Q4: The Full Adder test bench module (FA_test) and Full Adder module (FA) are sharing a common interface (a, b, cin, sum, cout). Write the interface FA_xyz using logic data type and top module which is described using this interface and these two modules. (3M) Q5: Write a system Verilog program in which a class declaration includes ‘int’ type declaration for Variable ‘i? and variable *j’ and task declaration which displays these two variables together. Now write a program using this class and assign and display (i) i=10, j=100 and ({i) i=20, j=200. (3M) Q6: (i) Ina system Verilog declaration “bit [7:0] [3:0] x" and “x= 32°habed_4567;" write the value of x[3] ? (ii) In the system Verilog task declaration ‘task mytask3(a,b, output logic [15:0] u, v;’ write the direction and size of ab and v? @M)Birla Institute of Technology & Science TP Semester 2016-17 MEL G626 VLSI Test and Testability Comprehensive Examination (Closed Book) MM:35 Date: 07/12/2016 (AN) Instructions: Attempt at parts of a question together Qk: ‘Time: 3 Hrs CAWrite the result displayed after running the following system verilog program. module abel); initial begin int d (], xya{]. J: inc tS]. x18) anew foreach db) d [i}> 100%); wrt; foreach (xyz{j]) yz (ile d )"2: Sdisplay (“op",a)s Saisplay 6p" Ay2): denew{l0] (), tend Sdisplay ("0"): iqinsent23), Stisplay 6p" tqdelete(S), Stisplay ("%".; tq push_front(7) ‘display ("26p"ta): (®) Write itany error in the following system verilog program else write ts output after running the code class A; inj: static task inert); ins Sdisplay("j is a"; eis endclass (Gi) Write the three basic operations for a semaphore? {i List the several ‘structural coverage models used for simulation based verification. (iv) Write the types of “Golden Vector Testbench’ pop_back; Sdisplay ("Yd") _tquuniqueds Sdisplay ("6p") end endmodule oom program main ; Acobj_ls Aobj_2; tial besin obj, 0bj_2 = new); ‘obj_.iner() bj_2.inen() end cendprogram @m a «aM aMfault equivalent collapsing and ult equivalent om 02: For the cireuit shown in Fig 1, (i) mark all faults (ii) remove faults usi compute the collapse ratio, (ii) remove faults using fault dominance collapsing (including fa collapsing) and compute the collapse ratio. age Q3: For the citeuit shown in Fig. 2, explain ifthe test vector the faults S-a0 at‘c’ and Seal at. Write the minimum size of vector required and indicate all the steps. (2)M aI, b=I using the parallel fault simulation can detect use the ‘fault table computing’ method to find all the test vectors required to test QM {Q4: For the circuit shown in Fi the circuit, Show all the steps. A aaa] pS ae Cm QS: (A) For the circuit shown in Fig. 4, use D-algorithm to detect SA0 fault at node ‘a!? Use implication procedure using primitive D-cube of failure (PDFC), propagation D-cubes (PDC), singular cover (SC), D-intersection to show values @M at each note in every steps.ae | eee Fie 4 ie nh anode g shoal ioc, GM (QS: (B) For the circuit shown in Fig.S apply PODEM to detect stuc 2 _td— s-a-1 a ee gs b e eer = Fig. 5 6, compute SCOAP combinational controllability and observability measures for resented asthe sum of appropriate controllability «@ (6: For the circuit shown in Fig. al fines. Assuming that the testability of a stuck-at fault ean be re and observability, find the set of most difficult to test fault INO OQUTO INt CC0,CC1)CO Fig. 6a {(A) Determine the test sequence forthe stuck at One (SA) fault on the indicated line of the circuit as shown in Fig. @M Input (1) te }—_———» Output (0) +—— eet. Fig.7 (B) A scan chain having number of scan flops 20 is used to test 10 combinational vector. Calculate the number of lock periods required to complete the test if (assume scan registers are already tested) (aM) 8: (A) Write the ypanion matrix forthe following LFSR circuit. em a ae e [ RESET Xp x, Xo (B) Describe Indempotent coupling fault with proper state diagram and name a Test which can detect this fault ‘What is the complexity ofthe algorithm in terms of»? @M)