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Lab 2

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116 views10 pages

Lab 2

vlsi labsheet

Uploaded by

IrfanKhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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\Department of Electrical & Electronic Engineering

Bangladesh University of Engineering & Technology


EEE458 VLSI II Laboratory
Lab. 2:
Full Custom Layout design of a 2 input NAND Gate

Learning Objective:

To create a layout view of the basic two input NAND circuit from scratch

2-1. Setting up the Virtuoso Layout Suite L

The VLSI design process goes through the following steps:


Schematic Design Schematic level Simulation Layout creation Design Rule Check
active device and parasitic Extraction Layout level Simulation

The tool for layout creation is called Virtuoso Layout Suite L. Before working with Layout editor
you need to set the design layers. These information are stored in the display.drf file.

After the preparation is done invoke the Layout Suite L Editor from the CIW by executing
File New Cell View. The new file form appears and fill it as shown in the figure below.

The Layers window is the one you will use to choose the different layers of the IC design.

ABM H Rashid, Dept. of EEE BUET1 8/03/2017


The LSW window is divided in three main categories which are: layer color, layer name and layer
purpose. The detailed is described in the table below:
Color Matches the color in the Editing window. Each layer has its own color and pattern.
Eachlayer has two colors associated with it; a fill color and an outline color.
Name What is the type of layer (Newll, Oxide, Poly, Metal1, etc)
Purpose In gpdk090 the only purpose classification isdrawing&slot
Drawing isused in layout, slot is used to create a whole for metal stress relief

Before start layout, you need to set the layout configuration. Execute the following in the Virtuoso
Layout Editor: Options Display. Configure the form as shown in the figure below:

ABM H Rashid, Dept. of EEE BUET2 8/03/2017


2-1. Building the layout of the CMOS 2 input NAND gate

Now we are going to build the layout of the NAND gate. A NAND gate has 2 PMOS transistors in
parallel and 2 NMOS transistors in series. We will create NMOS and PMOS regions sequentially.

As seen from the layer diagram the NMOS consists of Oxide, Nimp, Cont and Poly layers. Study
the rules of these layers.

ABM H Rashid, Dept. of EEE BUET3 8/03/2017


Poly

Oxide

Cont

Metal1

Nimp

Fig: Series NMOS layout

The rules related to the NMOS region can be summarised as follows:


Contact size: 0.06umX 0.06 um (Fixed)
Poly width Minimum: 0.045 um
Minimum contact on active area to gate spacing : 0.05 um
Minimum active area to contact enclosure : 0.03 um
Minimum poly to contact enclosure : 0.02 um
Minimum Poly gate space: 0.06 um
Minimum N-channel/P-Channel gate extension beyond Active Area : 0.1 um
Minimum N+ Implant/P+ Implant to Active Area enclosure : 0.07 um
Minimum Metal 1 width: 0.06 um
Maximum Metal 1 width: 6.0 um
Minimum Metal 1 to Metal 1 spacing: 0.06 um
Minimum Metal 1 to Contact enclosure: 0.00 um
Minimum Metal 1 to Contact enclosure two opposite side of the contact: 0.06 um

Now we start building the NMOS region layout. Look at the Layers window and find the current
drawing layer and follow the procedure described below:

1. To create the active area of the NMOS, left click the Cont layer and make it the current
drawing layer. In the Layout editor window execute Create Shape Rectangle.
2. Draw the contact (0.06u x 0.06u) and the surrounding Metal1 (0.12u x 0.12u) layer. We will
use copies of this one. So keep it untouched, and whenever required make a copy of it.
3. Select the Poly layer and draw the poly gate rectangle (0.05u x 0.3u). Make a copy of it at a
distance of 0.06u. Maintain a distance between contact and poly gate of 0.6u.
4. Select the Oxide layer and draw oxide surrounding the contact (0.44u x 0.12u).
5. Select Nimp layer and draw a rectangle around the oxide (0.62u x 0.3u).

The PMOS transistor consists of Oxide, Poly, Pimp, Cont and Nwell layer. Study the rules of these
layers.

ABM H Rashid, Dept. of EEE BUET4 8/03/2017


Poly

Oxide

Cont

Metal1

Pimp

Nwell

Fig: Parallel PMOS layout


The rules related to PMOS are same as NMOS except the there is an additional layer the Nwell,
whose rules are as follows:
Minimum Nwell width: 0.3 um
Minimum Nwell spacing to Nwell (same potential): 0.3 um
Minimum Nwell spacing to Nwell (different potential):0.6 um
Minimum Nwell spacing to N+ active area: 0.16 um
Minimum Nwell spacing to P+ active area: 0.16 um
Minimum Nwell enclosure to P+ active area: 0.06 um
Minimum Nwellenclousere to N+ active area: 0.06 um
Minimum N+ Active Area to N+Active Area spacing:0.08 um
Minimum P+ Active Area to P+Active Area spacing:0.08 um
Minimum N+ Active Area to P+ Active Area Spacing: 0.10 um

Now we start building the PMOS region layout. Look at the Layers window and find the current
drawing layer.

6. We build the PMOS region layout the same way as NMOS region just replace Nimp by
Pimp layer. Note: Oxide dimension is now 0.52 u x 0.12u& Pimp dimension is now
0.72u x 0.3u.

7. Additionally, select Nwell and draw nwell region around the Pimp region.

8. Next we restrict our space to a constant height so that other circuit layouts could be added
without modifying ours. We can do this by drawing two Metal2 layers at 5um apart. These
will work as Vdd and Gnd bus. This is shown in the following figure:

ABM H Rashid, Dept. of EEE BUET5 8/03/2017


9. Next we construct 6 12um x 12 um Metal1 box to emulate IO Pads.

10. Finally, define Metal1 pins for Input and Output pins.In the layout editor window execute
the following :Create Pin. Make sure that you are selecting the Metal1 in LSW.
11. To create the VddGnd Ain and Bin input pins fill in Create shape pin Form as shown
below and place a small rectangle on the desired pads in the same sequence.
12. In a similar way create Out pin (select I/O type output).

ABM H Rashid, Dept. of EEE BUET6 8/03/2017


13. Now place PMOS region and NMOS region as shown earlier and right click the mouse then
click Create ->Wires to create interconnects between poly gates, contacts, Vdd and Gnd as
the image shown below. You need to click Create ->Viato create connections between
Metal1 and Metal2 at Vdd and Gnd.

ABM H Rashid, Dept. of EEE BUET7 8/03/2017


14. Next we need to bias the p-substrate and n-well by creating Pimp and Nimp layer
respectively over those regions and providing oxide and contact. Finally connecting them
with Gnd and Vdd respectively. After this step your layout should look like the following
figure. Note that minimum oxide area must be 0.035u and hence a dimension of 0.13u x
0.12u would be suitable for providing the biasing.

15. Finally we need to create Metal2 to Metal1 Via and connect Vdd and Gnd bus with IO Pads.
Furthermore we need to create Contacts for connecting the poly gates to the different IO
Pads by Metal1 layer. Additionally, we need to connect the output node Metal1 layer to
another IO Pad. After all the connections the layout should look like the following figure.
At the end of these steps click File ->Save.

ABM H Rashid, Dept. of EEE BUET8 8/03/2017


Zoomed View

Overall View

ABM H Rashid, Dept. of EEE BUET9 8/03/2017


Report

Follow standard template of EEE 458 lab report and include the following also:

1. Show the print out of the layout. Measure its size. Could you achieve minimum sized
layout?
2. What types of error did you received? What are the meanings of the error?
3. Describe some good practices for 2 input NAND gate layout.

ABM H Rashid, Dept. of EEE BUET108/03/2017

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