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Building Blocks of Processor Systems
MEM ORY
INPUT-OUTPUT
EC1362 Microprocessor & CONTRO L
Microcontroller
DATAPATH
CPU
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Processor System Architecture Bus and CPU
Bus: A shared group of wires used for communicating
The typical processor system consists of: signals among devices
CPU (central processing unit) address bus: the device and the location within the
ALU (arithmetic-logic unit) device that is being accessed
Control Logic data bus: the data value being communicated
Registers, etc control bus: describes the action on the address and data
Memory buses
Input / Output interfaces
CPU: Core of the processor, where instructions are executed
Interconnections between these units:
High-level language: a = b + c
Address Bus Assembly language: add r1 r2 r3
Data Bus Machine language: 0001001010111010101
Control Bus
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Memory and I/O 8085 Microprocessor Architecture
Memory: Where instructions (programs) and data are stored
Organized in arrays of locations (addresses), each storing Now we will examine these components more closely
one byte (8 bits) in general by using the Intel 8085 microprocessor architecture
A read operation to a particular location always returns the as an example:
last value stored in that location
I/O devices: Enable system to interact with the world
Device interface (a.k.a. controller or adapter) hardware
connects actual device to bus
The CPU views the I/O device registers just like
memory that can be accessed over the bus. However,
I/O registers are connected to external wires, device
control logic, etc.
Reads may not return last value written
Writes may have side effects
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The 8085 Bus Structure The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU Micro Processing Unit) Address Bus
communicates with the other units using a 16-bit address
bus, an 8-bit data bus and a control bus. Consists of 16 address lines: A0 A15
Operates in unidirectional mode: The address
bits are always sent from the MPU to peripheral
devices, not reverse.
16 address lines are capable of addressing a
total of 216 = 65,536 (64k) memory locations.
Address locations: 0000 (hex) FFFF (hex)
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The 8085 Bus Structure The 8085: CPU Internal Structure
Data Bus
The internal architecture of the 8085 CPU is
Consists of 8 data lines: D0 D7 capable of performing the following operations:
Operates in bidirectional mode: The data bits are
Store 8-bit data (Registers, Accumulator)
sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU. Perform arithmetic and logic operations (ALU)
Data range: 00 (hex) FF (hex) Test for conditions (IF / THEN)
Control Bus Sequence the execution of instructions
Consists of various lines carrying the control Store temporary data in RAM during execution
signals such as read / write enable, flag bits.
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The 8085: CPU Internal Structure The 8085: Registers
Simplified block diagram
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The 8085: CPU Internal Structure The 8085: CPU Internal Structure
Registers Flag Bits
Six general purpose 8-bit registers: B, C, D, E, H, L Indicate the result of condition tests.
They can also be combined as register pairs to Carry, Zero, Sign, Parity, etc.
perform 16-bit operations: BC, DE, HL
Conditional operations (IF / THEN) are executed
Registers are programmable (data load, move, etc.) based on the condition of these flag bits.
Accumulator Program Counter (PC)
Single 8-bit register that is part of the ALU ! Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Used for arithmetic / logic operations the result is
always stored in the accumulator. Stack Pointer (SP)
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Example: Memory Read Operation Example: Instruction Fetch Operation
All instructions (program steps) are stored in memory.
To run a program, the individual instructions must
be read from the memory in sequence, and executed.
Program counter puts the 16-bit memory address of the
instruction on the address bus
Control unit sends the Memory Read Enable signal to
access the memory
The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
Instruction is decoded and executed
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Example: Instruction Fetch Operation Example: Instruction Fetch Operation
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8085 Functional Block Diagram
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