0576.MSP430 Programming Via The Bootstrap Loader
0576.MSP430 Programming Via The Bootstrap Loader
User's Guide
List of Figures
1-1. Standard RESET Sequence ............................................................................................... 6
1-2. BSL Entry Sequence at Shared JTAG Pins ............................................................................. 6
1-3. BSL Entry Sequence at Dedicated JTAG Pins.......................................................................... 7
3-1. Basic Protocol - Byte Level ACK ........................................................................................ 23
3-2. Byte Level ACK ............................................................................................................ 24
4-1. Bootstrap Loader Interface Schematic ................................................................................. 31
6-1. Universal BSL Interface PCB Layout, Top ............................................................................. 48
6-2. Universal BSL Interface PCB Layout, Bottom ......................................................................... 48
6-3. Universal BSL Interface Component Placement ...................................................................... 49
6-4. Universal BSL Interface Component Placement ...................................................................... 50
List of Tables
2-1. Data Frame of BSL Commands ......................................................................................... 11
2-2. Recommendations for MSP430F149 [MSP430F449] (TA = 25C, VCC = 3.0 V, fmax = 6.7 MHz) ................ 15
2-3. Recommendations for MSP430F2131 (TA = 25C, VCC = 3.0 V, fmax = 6.7 MHz) .................................. 15
3-1. UART Protocol Interface .................................................................................................. 21
3-2. UART Error Messages .................................................................................................... 22
3-3. BSL Core Command Wrapper for I2C .................................................................................. 24
3-4. USB Peripheral Interface ................................................................................................. 25
3-5. BSL Core Commands ..................................................................................................... 25
3-6. BSL Core Responses ..................................................................................................... 28
3-7. BSL Core Messages ...................................................................................................... 29
4-1. Serial-Port Signals and Pin Assignments .............................................................................. 32
4-2. RS-232 Levels ............................................................................................................. 32
4-3. Pin Assignment of Target Connector ................................................................................... 33
4-4. Universal BSL Interface Parts List...................................................................................... 34
5-1. BSL Version 1.10 on F13x, F14x(1) (excluding Rev AA), F11x, and F11x1 ...................................... 35
5-2. BSL Version 1.30 on F41x, F11x, and F11x1 ......................................................................... 36
5-3. BSL Version 1.40 on F12x ............................................................................................... 37
5-4. BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, F(G)43x, F415, F417 ....................... 38
5-5. BSL Version 1.61 on F16x, F161x, F42x0, F13x rev AA, F14x(1) rev AA, F47x, FG47x........................ 39
5-6. BSL Version 2.02 and 2.13 on F21xx, F22xx, F23xx, F24xx, F261x ............................................... 40
5-7. BSL Version 2.02 and 2.03 on G2xx3, G2xx4, G2xx5, TCH5E ..................................................... 41
5-8. BSL Version 2.12 and 2.13 on FG46xx, F471xx ...................................................................... 42
The MSP430 BSL enables users to communicate with embedded memory in the MSP430
microcontroller during the prototyping phase, final production, and in service. Both the programmable
memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the
bootstrap loader with programs found in some digital signal processors (DSPs) that automatically load
program code (and data) from external memory to the internal memory of the DSP. These programs are
often referred to as bootstrap loaders as well.
To use the bootstrap loader, a specific BSL entry sequence must be applied. An added sequence of
commands initiates the desired function. A boot-loading session can be exited by continuing operation at a
defined user program address or by the reset condition.
If the device is secured by disabling JTAG, it is still possible to use the BSL. Access to the MSP430
memory through the BSL is protected against misuse by a user-defined password.
1.2 Introduction
This bootstrap loader provides a method to program the flash memory during MSP430 project
development and updates. It can be activated by a utility that sends commands using the UART protocol.
The BSL enables the user to control the activity of the MSP430 and to exchange data using a personal
computer or other device.
To avoid accidental overwriting of the BSL code, this code is stored in a secure memory location, either
ROM or specially protected flash. To prevent unwanted source readout, any BSL command that directly or
indirectly allows data reading is password protected.
To invoke the bootstrap loader, a BSL entry sequence must be applied to dedicated pins. After that, a
synchronization character, followed by the data frame of a specific command, initiates the desired
function.
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Standard RESET and BSL Entry Sequence www.ti.com
RST/NMI
(DTR)
TEST
(RTS)
User Program Starts
The BSL program execution starts when the TEST pin has received a minimum of two positive transitions
and if TEST is high while RST/NMI rises from low to high (BSL entry method, see Figure 1-2). This level
transition triggering improves BSL startup reliability.
RST/NMI
(DTR)
TEST
(RTS)
Bootstrap Loader Starts
NOTE: The recommended minimum time for pin states is 250 ns. See the device-specific errata for
any differences, because some 5xx and 6xx device revisions require specific entry
sequences.
The TEST signal is normally used to switch the port pins between their application function and the JTAG
function. In devices with BSL functionality, the TEST and RST/NMI pins are also used to invoke the BSL.
To invoke the BSL, the RST/NMI pin must be configured as RST and must be kept low while pulling the
TEST pin high and while applying the next two edges (falling, rising) on the TEST pin. The BSL is started
after the TEST pin is held low for more than 100 s and then the RST/NMI pin is released (see Figure 1-
2).
The BSL is not started by the BSL RESET vector if:
There are fewer than two positive edges at the TEST pin while RST/NMI is low.
TEST is low when RST/NMI rises from low to high.
JTAG has control over the MSP430 resources.
Supply voltage, VCC, drops below its threshold, and a power-on reset (POR) is executed.
RST/NMI pin is configured for NMI functionality (NMI bit is set).
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RST/NMI
(DTR)
TCK
(RTS)
Bootstrap Loader Starts
NOTE: The recommended minimum time for pin states is 250 ns. See the device-specific errata for
any differences, because some 5xx and 6xx device revisions have specific entry sequence
requirements.
NOTE: Applying baud rates other than 9600 baud at initialization results in communication problems
or violates the flash memory write timing specification. The flash memory may be extensively
stressed or may react with unreliable program or erase operations.
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Chapter 2
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NOTE: The synchronization character is not part of the Data Frame described in Section 2.4.
2.2 Commands
Two categories of commands are available: commands that require a password and commands that do
not require a password. The password protection safeguards every command that potentially allows direct
or indirect data access.
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NOTE: If control over the UART protocol is lost, either by line faults or by violating the data frame
conventions, the only way to recover is to rerun the BSL entry sequence to initiate another
BSL session.
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Table 2-1. Data Frame of BSL Commands (1) (2) (3) (4) (5) (6)
Received
BSL HDR CMD L1 L2 AL AH LL LH D1 D2Dn CKL CKH ACK
Command
RX data block 80 12 n n AL AH n4 0 D1 D2 Dn4 CKL CKH ACK
RX password 80 10 24 24 xx xx xx xx D1 D2 D20 CKL CKH ACK
Erase segment 80 16 04 04 AL AH 02 A5 CKL CKH ACK
Erase main or info 80 16 04 04 AL AH 04 A5 CKL CKH ACK
Mass erase 80 18 04 04 xx xx 06 A5 CKL CKH ACK
Erase check 80 1C 04 04 AL AH LL LH CKL CKH ACK
Change baud rate 80 20 04 04 D1 D2 D3 xx CKL CKH ACK
Set mem offset 80 21 04 04 xx xx AL AH CKL CKH ACK
Load PC 80 1A 04 04 AL AH xx xx CKL CKH ACK
TX data block 80 14 04 04 AL AH n 0 CKL CKH
BSL responds 80 xx n n D1 D2 ... ... ... Dn CKL CKH
TX BSL version 80 1E 04 04 xx xx xx xx CKL CKH
BSL responds 80 xx 10 10 D1 D2 ... ... D10 CKL CKH
(1)
All numbers are bytes in hexadecimal notation.
(2)
ACK is sent back by the BSL.
(3)
The synchronization sequence is not part of the data frame.
(4)
The erase check and TX BSL version commands are members of the standard command set in BSLs V1.50 or higher but
excluding 2.x BSLs.
(5)
The change baud rate command is not a member of the standard command set (it is available in V1.60 or higher or in loadable
BL_150S_14x.txt).
(6)
Abbreviations:
HDR: Header. Any value between 80h and 8Fh (normally 80h).
CMD: Command identification
L1, L2: Number of bytes consisting of AL through Dn. Restrictions: L1 = L2, L1 < 255, L1 even
AL, AH: Block start address or erase (check) address or jump address LO or HI byte
LL, LH: Number of pure data bytes (250 max) or erase information LO or HI byte or block length of erase check (FFFFh max)
D1 Dn: Data bytes
CKL, CKH: 16-bit checksum LO or HI byte
xx: Can be any data
: No character (data byte) received or transmitted
ACK: The acknowledge character returned by the BSL. Can be either DATA_ACK = 90h: Frame was received correctly,
command was executed successfully, or DATA_NAK = A0h: Frame not valid (for example, wrong checksum, L1 L2), command
is not defined, is not allowed, or was executed unsuccessfully.
n: Number of bytes consisting of AL through Dn
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2.4.2 Checksum
The 16-bit (2-byte) checksum is calculated over all received or transmitted bytes B1 to Bn in the data
frame, except the checksum bytes themselves, by XORing words (two successive bytes) and inverting the
result.
This means that B1 is always the HDR byte and Bn is the last data byte just before the CKL byte.
Formula
CHECKSUM = INV [ (B1 + 256 B2) XOR (B3 + 256 B4) XOR XOR (Bn1 + 256 Bn) ]
or
CKL = INV [ B1 XOR B3 XOR XOR Bn1 ]
CKH = INV [ B2 XOR B4 XOR XOR Bn ]
TO BSL: 80
(Synchronization character sent to the BSL)
FROM BSL: 90
(Acknowledge from BSL)
TO BSL: 80 14 04 04 00 0F 0E 00 75 E0
(Send Command to read memory from 0x0F00, length 0x000E)
FROM BSL: 80 00 0E 0E F2 13 40 40 00 00 00 00 00 00 02 01 01 01 C0 A2
(Returned values from BSL)
2.4.4.1 General
Following the header byte HDR (80h) and the command identification CMD, the frame length bytes L1 and
L2 (which must be equal) hold the number of bytes following L2, excluding the checksum bytes CKL and
CKH.
Bytes AL, AH, LL, LH, D1...Dn are command-specific. However, the checksum bytes CKL (low byte) and
CKH (high byte) are mandatory.
If the data frame has been received correctly and the command execution was successful, an
acknowledge character DATA_ACK = 90h is sent back by the BSL. Incorrectly received data frames,
unsuccessful operations, and commands that are locked or not defined are confirmed with a DATA_NAK =
A0h.
NOTE: BSL versions lower than V1.30 support only byte-access operations. Therefore, the
peripheral module addresses at 0100h to 01FFh cannot be accessed correctly, because they
are word-oriented. In version V1.30 and higher, addresses 0000h to 00FFh are accessed in
byte mode; all others are accessed in word mode.
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The following data bytes are succeeded by the checksum bytes CKL (low byte) and CKH (high byte). If
the receipt and programming of the appropriate data block was successful, an acknowledge character
DATA_ACK is sent back by the BSL. Otherwise, the BSL confirms with a DATA_NAK.
NOTE: BSL versions V1.40 and higher support online verification inside the MSP430 for addresses
0200h to FFFFh, which reduces programming and verification time by 50%. Online
verification means that the data is immediately verified with the data that is written into the
flash without transmitting it again. In case of an error, the loadable bootstrap loader
BL_150S_14x.txt additionally stores the first incorrectly written location address+3 into the
error address buffer in the RAM at address 0200h (021Eh for F14x devices).
2.4.4.3 RX Password
The receive password command is used to unlock the password-protected commands, which perform
reading, writing, or segment-erasing memory access. It is not password protected.
Neither start address nor block length information is necessary, because the 32-byte password is always
located at addresses FFE0h to FFFFh. Data bytes D1 to D20h hold the password information starting with
D1 at address FFE0h.
If the receipt and verification of the password is correct, a positive acknowledge DATA_ACK is sent back
by the BSL, and the password-protected commands become unlocked. Otherwise the BSL confirms with a
DATA_NAK.
After the protected commands become unlocked, they remain unlocked until another BSL entry is initiated.
NOTE: BSL versions V2.01 and higher support automatic clearing of the LOCKA bit protecting
information flash memory. When the BSL is entered from a reset condition, LOCKA is
cleared by the BSL to mass erase the flash, including information memory. When the BSL is
entered in-application, user software should ensure that LOCKA is written as 1 prior to
initiating the BSL. Otherwise, information flash is not erased during a BSL mass erase.
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When applying LL = 0x04 and LH = 0xA5, a mass erasure of only the main memory is performed. Indeed,
this command must be executed a minimum of 12 times to achieve a total erasure time of >200 ms. No
subsequent erase check of the entire main memory is done. Use the erase check command additionally.
Check the device data sheet for more information on the cumulative (mass) erase time that must be met
and the number of erase cycles required.
NOTE: This command is not a member of the standard command set. It is implemented in BSL
version V1.60 and higher or in the loadable bootstrap loader BL_150S_14x.txt.
D1: F1xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)
F2xx: Basic clock module control register DCOCTL (DCO.2 to DCO.0)
F4xx: FLL+ system clock control register SCFI0 (D, FN_8 to FN_2)
D2: F1xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)
F2xx: basic clock module control register BCSCTL1 (XT2Off, Rsel.2 to Rsel.0)
F4xx: FLL+ system clock control register SCFI1 (NDCO)
D3 0: 9600 Baud
1: 19200 Baud
2: 38400 Baud
After receiving the data frame, an acknowledge character DATA_ACK is sent back, and the BSL becomes
prepared for the selected baud rate. It is recommended for the BSL communication program to wait
approximately 10 ms between baud rate alteration and succeeding data transmission to give the BSL
clock system time for stabilization.
NOTE: The highest achievable baud rate depends on various system and environment parameters
like supply voltage, temperature range, and minimum and maximum processor frequency.
See the device-specific data sheet.
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NOTE: This command is implemented on BSL versions V1.60 or higher or available in the loadable
bootstrap loader BL_150S_14x.txt.
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2.4.4.10 Load PC
The load program counter command directs the program counter (register R0) to any location within the
entire address range. It is password protected.
After receiving the data frame, an acknowledge character (DATA_ACK) is sent back by the BSL. Then the
selected address is moved into the program counter. The program flow continues operation there, and the
BSL session is terminated.
Be aware that the password protection is not active at this time.
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www.ti.com Exiting the BSL
NOTE: The user must take care of password update after modifying the interrupt vectors and
initiating another BSL session. It is also strongly recommended to initialize unused interrupt
vectors to increase data security.
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NOTE: A warm start does not modify the stack pointer. Additionally, the status register for the BSL is
not cleared, which could cause a warm started BSL to come up in an unlocked state. Warm
start possibility exists only for highly specialized instances where it is absolutely mandatory
that a running application be returned to after a BSL session without resetting the device. In
almost all cases, it is better to start the BSL from user code by calling the cold start vector.
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Chapter 3
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3.2.1 Wrapper
The default BSL430 programmed in each non-USB MSP430F5xx device communicates using a UART
peripheral interface (PI). The UART protocol interface has the format shown in Table 3-1. All numbers are
in hexadecimal format.
3.2.2 Abbreviations
CKL, CKH
CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command
section only. The CRC is computed using the MSP430F5xx CRC module specification (see the CRC
chapter of the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208) for implementation
details).
NL, NH
Number of bytes in BSL core data packet, broken into high and low bytes.
ACK
Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not
imply the BSL core data is a correct command or that it was executed correctly. ACK signifies only that
the packet was formatted as expected and had a correct checksum.
NOTE: If the PI encounters an error at any stage of receiving the packet, it immediately responds
with the appropriate error message.
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3.2.3 Messages
The peripheral interface section of the BSL430 software parses the wrapper section of the BSL data
packet. If there are errors with the data transmission, an error message is sent immediately. An ACK is
sent after all data has been successfully received and does not mean that the command has been
correctly executed (or even that the command was valid) but, rather, that the data packet was formatted
correctly and passed on to the BSL core software for interpretation.
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Sent by master
Sent by slave
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Sent by master
Sent by slave
The high-level acknowledge indicates that the checksum of the BSL core command obtained is correct
and as expected. In some cases, this ACK may indicate the command was properly executed. This is
the first byte of RDATA. If this is NAK (other than 0x00), it indicates that a proper command was not
received and the master should consider that command transmission as a failure. If this is ACK (0x00),
it indicates that the transmission or reception of the command was correct with the right checksum and
that the data which follows is the response, if any, from the slave. The slave may keep the CLK line
low if it needs time to process before it responds to the command.
3.3.4 Wrapper
The wrapper for the BSL data packet integrates the common UART BSL Core Command packet, but adds
Length, Checksum, and Acknowledge to be used within I2C communication (see Table 3-3).
CKL, CKH
CRC checksum high and low bytes. The checksum is computed on bytes in BSL core command
section only.
NL, NH
Number of bytes in BSL core data packet, broken into high and low bytes.
ACK
Sent by the BSL after the packet is received to acknowledge receiving the data correctly. This does not
imply that the BSL core data is a correct command or that it was executed correctly. ACK signifies only
that the packet was formatted as expected and had a correct checksum.
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3.4.1 Wrapper
The Peripheral Interface for the USB Bootstrap loader has the wrapper format shown in Table 3-4. There
are no interface specific commands or replies for the USB BSL. The only variable byte, NL, should
describe the number of bytes contained in the BSL Core Command packet.
NOTE: See Section 5.5 for using the following commands with the BSL in the MSP430F5438 (non-A
version).
NOTE: BSLs that are programmed in Flash and that communicate by USB contain only a subset of
the commands shown in Table 3-5. These commands can be used to load in a full BSL into
RAM for Flash programming. The commands in this subset are RX DATA BLOCK FAST, RX
PASSWORD, and LOAD PC.
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3.5.1 Abbreviations
No data required. No delay should be given, and any subsequently required data should be sent as the
immediate next byte.
AL, AM, AH
Address bytes. The low, middle, and upper bytes, respectively, of an address.
D1 ... Dn
Data bytes 1 through n (Note: n must be 4 less than the BSL buffer size.)
Length
A byte containing a value from 1 to 255 describing the number of bytes to be transmitted or used in a
CRC. In the case of multiple length bytes, they are combined together as described to form a larger
value describing the number of required bytes.
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3.7.1 Abbreviations
CMD
A required field used to distinguish between a message from the BSL and a data transmission from the
BSL.
MSG
A byte containing a response from the BSL core describing the result of the requested action. This can
either be an error code or an acknowledgment of a successful operation. It should be noted, in cases
where the BSL is required to respond with data (for example, memory, version, CRC, or buffer size),
no successful operation reply occurs, and the BSL core immediately sends the data.
D1, Dx
Data bytes containing the requested data.
DL, DH
Data low and high bytes, respectively, of a requested 16-bit CRC value.
NL, NH
Data bytes describing the length of the buffer size in bytes. To manage sizes above 255, the size is
broken up into a low byte and a high byte.
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Chapter 4
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This chapter describes simple and low-cost hardware and software solutions to access the bootstrap
loader functions of the MSP430 flash devices through the serial port (RS-232) of a PC.
TL062D
TL062D
The inverters are powered by the operational amplifier IC3A. This amplifier permits adjusting the provided
logic level to the requirements of the connected target application. A voltage applied to pin 8 of the BSL
target connector (VCC_IN) overrides the default 3-V level provided from IC1 and the 100-k series
resistor R11. Thus, the output voltage of the operational amplifier is pulled to the applied voltage VCC_IN.
Depending on the overvoltage protection of the device family selected, the excess voltage is either
conducted to VCC (as in the TI '74HC14) or to GND (as in the TI '74AHC14). If the protection diode
conducts to VCC, the operational amplifier IC3A needs to compensate for the overvoltage. Therefore, the
'74AHC14 device, which conducts to ground (GND), is recommended.
To avoid excessive power dissipation and damage of the protection diodes, series resistors (R1, R2, and
R3) are used to limit the input current.
An operational amplifier (IC3B) is used to generate RS-232 levels out of CMOS levels. The level at the
positive input is set to VCC/2 (1.5 V nominal). If the level at the negative input rises above this level, the
output is pulled to the negative supply of the operational amplifier (mark). If the level drops below VCC/2,
the output is pulled to the positive rail (space).
The positive supply of the operational amplifier is the same as the input to the voltage regulator. A
separate capacitor (C5) is used to generate the negative-supply voltage. This capacitor is charged by the
receiving signal of the bootstrap loader hardware (pin 3 on SUB-D connector J2).
During an asynchronous serial communication, the combination of stop bit and start bit is used to
synchronize sender and receiver. After the transmission of a data byte, the stop bit forces the transmission
line into a defined state, which is usually a logic 1 or, in RS-232 terms, a mark. This means that the
transmission-line voltage is negative when there is no transmission and the capacitor can be charged.
Diodes are used to prevent discharge of the capacitor during transmission.
In very rare circumstances, the data sent to the bootstrap loader interface might hold too many zeros, so
that the capacitor C5 required for the negative supply is discharged, causing a malfunction of the
interface. (A possible workaround is to send the data in smaller chunks.) But under normal operating
conditions, even data containing all zeros does not cause problems.
Table 5-1. BSL Version 1.10 on F13x, F14x(1) (excluding Rev AA), F11x, and F11x1
F13x F11x (obsolete)
Device
F14x(1) up to Rev N F11x1 (obsolete)
BSL Version 1.10
Cold start 0C00h
BSL vector address
Warm start
Chip ID address 0FF0h
Chip ID data F149h F112h
BSL version address 0FFAh
BSL version data 0110h
Mass erase time, nominal (ms) 17.2 (1)
Read and write access at 0000h to FFFFh Byte
Verification during write (online) No
SP critical 021Ah
Stack pointer initialization
SP not critical Unchanged
Resources Used by BSL
Transmit pin (TX), Receive pin (RX) P1.1, P2.2
RAM stack used 0200h to 0219h
Working registers R5 to R9
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
mov #00h, &CCTL0
bic.b #02h, &P1SEL
bic.b #04h, &P2SEL
Preparation for software call bic.b #32h, &IE1
mov.b #00h, &BCSCTL2
mov #00h, SR
br &0C00h
Comment 1 Load PATCH.TXT to eliminate ROM bug (see Section 5.2 and
Workaround mandatory Section 2.5).
Comment 2 Load BL_150S_14x.txt to get all features of V1.60 plus valid
Optional for F148, F149 only: Use loadable BSL erase segment command (see Section 2.5).
(>1 KB RAM required)
Comment 3 Load BS_150S_14x.txt to get some features of V1.60 (see
Optional for F1x4 to F1x9: Use small loadable BSL Section 2.5).
(<512B RAM required)
(1)
To reach the required mass erase time as specified in the data sheet, the mass erase command must be executed several
times.
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Table 5-4. BSL Version 1.60 on F11x2, F12x2, F43x, F44x, FE42x, FW42x, F(G)43x, F415, F417
FE42x,
F1122, F1222, F43x, FW42x,
Device F(G)43x
F1132 F1232 F44x F415,
F417
BSL Version 1.60
Cold start 0C00h
BSL vector address
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data 1132h 1232h F449h F427h F439h
BSL version address 0FFAh
BSL version data 0160h
Mass erase time, nominal (ms) 206.4
0000h to 00FFh Byte
Read and write access at
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase check command Yes (error address 0200h)
Erase segment command With erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Cold start 0220h
Stack pointer initialization
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1 P1.0
Receive pin (RX) P2.2 P1.1
RAM stack used 0200h to 021Fh
Working registers R5 to R12
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2 mov.b #00h, &FLLCTL1
Preparation for software call mov #00h, SR br &0C00h
br &0C00h
Erase segment Addresses 1000h to 11FFh are verified coherently (three segments). Also use
Comment
command erase check command.
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Table 5-5. BSL Version 1.61 on F16x, F161x, F42x0, F13x rev AA, F14x(1) rev AA, F47x, FG47x
F149
Device F16x F161x F42x0 F41x2 F47197 FG47x
Rev AA
BSL Version 1.61
Cold start 0C00h
BSL vector address
Warm start 0C02h
Chip ID address 0FF0h
Chip ID data 0F169h 0F16Ch F149h F427h 4152h F47Fh 0F479h
BSL version address 0FFAh
BSL version data 0161h
Mass erase time, nominal (ms) 206.4
0000h to 00FFh Byte
Read and write access at
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase check command Yes (error address 0200h)
Erase segment command With erasure verification (error address 0200h)
TX identification command Yes
Change baud rate command Yes
Cold start 0220h
Stack pointer initialization
Warm start Unchanged
Resources Used by BSL
Transmit pin (TX) P1.1 P1.0
Receive pin (RX) P2.2 P1.1
RAM stack used 0200h to 021Fh
Working registers R5 to R14
System clock, affected controls BCSCTL1, DCOCTL SCFI0, SCFI1, SCFQCTL
Timer_A, affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2 mov.b #00h, &FLLCTL1
Preparation for software call mov #00h, SR br &0C00h
br &0C00h
Erase segment Addresses 1000h to 11FFh are verified coherently (three segments). Also use erase
Comment
command check command.
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Table 5-6. BSL Version 2.02 and 2.13 on F21xx, F22xx, F23xx, F24xx, F261x
Device F21xx F22xx F23xx F24x F261x
BSL Version 2.02 2.13
Cold Start 0C00h
BSL Vector Address
Warm Start 0C02h (1)
Chip ID Address 0FF0h
Chip ID Data F213h F227h F237h F249h F26Fh
BSL Version Address 0FFAh
BSL Version Data 0202h 0213h
0000h to 00FFh Byte
Read and Write Access at
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase Check Command Yes (error address 0200h)
Erase Segment Command With erasure verification (error address 0200h)
TX Identification command Yes
Change baud rate command Yes
Cold Start 0220h 0224h
Stack Pointer Initialization
Warm Start Unchanged
Resources Used by BSL
Transmit Pin (TX) P1.1
Receive Pin (RX) P2.2
RAM Stack Used 0200h to 021Fh 0200h to 0223h
Working Registers R5 to R14 R4 to R15
SCFI0, SCFI1,
System clock, affected controls BCSCTL1, DCOCTL
SCFQCTL
Timer_A, Affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2
Preparation for software call mov #00h, SR
br &0C00h
Erase Segment Addresses 1000h to 11FFh are verified coherently (five segments). Also use erase
Comment
Command check command.
(1)
The LOCK and LOCKA bits must be cleared by the user application before entering the BSL:
mov.w #FWKEY+LOCKA,&FCTL3
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Table 5-7. BSL Version 2.02 and 2.03 on G2xx3, G2xx4, G2xx5, TCH5E (1)
Device G2xx4 G2xx5 G2xx3 TCH5E
BSL Version 2.02 2.03
Cold Start 0C00h
BSL Vector Address
Warm Start 0C02h (2)
Chip ID Address 0FF0h
Chip ID Data F227h 2955h 2553h 255Ch
BSL Version Address 0FFAh
BSL Version Data 0202h 0203h
0000h to 00FFh Byte
Read and Write Access at
0100h to FFFEh Word
Verification during write (online) For addresses 0200h to FFFEh
Erase Check Command Yes (error address 0200h)
Erase Segment Command With erasure verification (error address 0200h)
TX Identification command Yes
Change baud rate command Yes
Cold Start 0220h
Stack Pointer Initialization
Warm Start Unchanged
Resources Used by BSL
Transmit Pin (TX) P1.1 P1.1
Receive Pin (RX) P2.2 P1.5
RAM Stack Used 0200h to 021Fh
Working Registers R5 to R14
System clock, affected controls BCSCTL1, DCOCTL
Timer_A, Affected controls TACTL, TAR, CCTL0, CCR0
mov.b #00h, &BCSCTL2
Preparation for software call mov #00h, SR
br &0C00h
Erase Segment Addresses 1000h to 11FFh are verified coherently (five segments). Also
Comment
Command use erase check command.
(1)
Not all Value Line devices contain a BSL; see device-specific data sheet.
(2)
The LOCK and LOCKA bits must be cleared by the user application before entering the BSL:
mov.w #FWKEY+LOCKA,&FCTL3
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Chapter 6
SLAU319F July 2010 Revised September 2013
unitop.wmf@
unibottom.wmf@
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60,00 mm
3,5 mm
Figure 6-3. Universal BSL Interface Component Placement
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60,0 mm
TL062D
3,5 mm
Figure 6-4. Universal BSL Interface Component Placement
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www.ti.com Revision History
Revision History
Changed the paragraph that follows the note after Figure 1-2 ..................................................................... 6
Added Section 3.3 ...................................................................................................................... 23
Added "Reserved numbers" starting at 0x90 and 0xB0 ........................................................................... 29
Changed the order of subsections in Chapter 5 .................................................................................... 35
Added FG47xx to Table 5-5 ........................................................................................................... 39
Changed all tables in Section 5.5 ..................................................................................................... 44
Added table for MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 ............................................. 45
Added Section 5.6 ...................................................................................................................... 47
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
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