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List of Experiments

The document describes experiments conducted using VHDL to design and implement an arithmetic logic unit (ALU) using an FPGA. It includes the VHDL code for a behavioral model of an ALU. The code defines functions for addition and subtraction of 2-bit vectors. It also contains a process with a case statement that defines the output F for different 3-bit control signals, performing operations like addition, subtraction, AND, OR, and XOR on the 2 4-bit inputs p and q. The result is that the VHDL code is successfully simulated and synthesized to implement the ALU on an FPGA.

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57 views6 pages

List of Experiments

The document describes experiments conducted using VHDL to design and implement an arithmetic logic unit (ALU) using an FPGA. It includes the VHDL code for a behavioral model of an ALU. The code defines functions for addition and subtraction of 2-bit vectors. It also contains a process with a case statement that defines the output F for different 3-bit control signals, performing operations like addition, subtraction, AND, OR, and XOR on the 2 4-bit inputs p and q. The result is that the VHDL code is successfully simulated and synthesized to implement the ALU on an FPGA.

Uploaded by

FLOWER
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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List Of Experiments :

1. Simulation of NMOS and CMOS circuits using


SPICE.
2. Implementation of periodogram and multistage
multirate systems using MATLAB.
3. System design using 16- bit Microprocessor.
4. System design using PIC Microcontroller.
5. Modeling of Sequential Digital system using
VHDL.
6. Modeling of Sequential Digital system using
Verilog.
7. Design and Implementation of ALU using FPGA.
Design and Implementation of ALU using FPGA.
Design and Implementation of ALU using FPGA.
Aim: Write VHDL programs for ALU. Apparatus used: XILINX 8.1 Software
installed in a PC.

Theory:

Program: Behavior Model of ALU:

Library IEEE; Use ieee.std_logic_1164_all;

Use ieee.std_logic_arith_all;

Entity ALU_2 is Port (p, q: in bit_vector (3 down to 0); s: in bit_vector (2 down


to 0); f: in bit_vector (3 down to 0)); End ALU_2;

Architecture ALU_2_beh of ALU_2 is

Function of + Function

add (a, b: bit_vector (2 down to 0)

Return bit_vector is

Variable cout: bit;

Variable cin: bit;

Variable sum: bit_vector (2 down to 0);


Begin For i: in 0 to 2 loop Sum (i): a (i) XOR b (i) XOR Cin;

Cout: = (a (i) and b (i)) OR (b (i) and Cin) OR (Cin And a (i));

Cin: = Cout

End loop;

Return sum;

End +

--function of subtraction of 2 bit array

Function -(a, b: bit_vector (3 down to 0)

Return bit_vector is Variable cout: bit;

Variable Cin: bit=0;

Variable diff (i): bit_vector (3 down to 0);

Begin

For I in 0 to 3 loop

Cout: = ((not a (i) and b (i)) or ((b (i) and cin) or ((not a (i) and cin)) ;

Diff (i):= a (i) xor b (i) xor cin;

Cin: = cout;

End loop; Return diff (i);

End -;

Begin

Process (p, q, and s)

Begin

Case s is When 000=>

F<= 0000;

When 001 =>


F =q-p;

When 010=>

F =p-q;

When 001=>

F =p+q;

When 100=>

F =p and q;

When 101=>

F<= p xor q;

When 110=>

F<=p or q:

When 111 =>

F<= 1111;

End case;

End process;

End ALU_Beh;

Result: All the VHDL codes of ALU is simulated & synthesized.

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