Lecture-5

Development of Memory Chip:

Let us consider a memory of 16 words, each of 8 bits is to be
stored. 16 words can be stored in 16 memory locations, each having
a unique 4 bit memory address (0000 to 1111) and each location
being capable of containing 8 bits of data.
To set up this memory system using ICs, 16 bit flip-flop
registers are required. To identify the correct address a 4 line-16 line
decoder can be used to decode the 4 bit location address to select
the appropriate data register (1 to 16) for input/output. Figure shows
the circuit used to implement the memory system.
 The 74LS374s are octal D flip flops with three state of outputs.
To store data in them, 8 bits of data are put on the D0 to D7 data
inputs via the data bus. Then the low to high edge on the clock input
will cause the data a D0 to D7 to be latched into each flip-flop. the
stored value in the D flip-flopis observed at the outputs Q0 to Q7 by
making the output enable pin low
To select the appropriate memory location, a 4 bit address is
input to 74154 (4 Line to 16 Line decoder), which outputs a low pulse
on one of the output lines when the is pulsed low. The timing
of setting up the address bus, data bus and pulsing the line
is critical. The following figure shows standard timing diagram bus
driven devices. Rather than showing all four address lines and all
data lines, they are grouped and X is used to show where any or all
of the lines are allowed to change digital levels.
 The address and the data lines must be set up some time (ts)
before the low to high edge of . In other words the address
and the data lines must be valid some period of time (ts) before the
low to high edge of in order for the74374 to interpret them
correctly.
When the line is pulsed, the decoder outputs a low
pulse on one of its 16 outputs which clocks the appropriate memory
location to receive data from the data bus. After the propagation
delay, (tp) the data output at Q0 to Q7 will be the new data just
entered into the D flip-flop. Then the tp will include the propagation
delay of decoder and of the D flip-flop.
In the figure all the three state outputs are continuously enabled
so that their Q outputs always active. To reduce the number of lines
the 8 outputs Q0 to Q7 of all 16 memory locations back to the data
bus. The enables of the 16 memory locations have to be
individually selected at the appropriate time to avoid a conflict on the
data bus, called bus contention. Bus contention occurs when two or
more devices are trying to send their digital levels to the shared data
bus at the same time. To individually select each group of Q outputs,
the grounds on the enables would be removed and instead be
connected to the output of another 74154 1 of 16 decoder.
 Commercially available memory chips combine all the decoding
and the storage elements in a single package.

MEMORY:
If a memory stores N- words of information each word being of
m bits, we say it is a Nxm memory. e.g. 8x4 memory means there are
8 words 4 each word containing 4- bit of information (called nibble). 8
words are stored at 8-memory locations and these memory locations
are clearly identified by addresses. Addresses are formulated by bit
combinations available in wires known as address lines. To identify 8
memory locations we require 3 address lines designed A2A1A0. The
memory locations identify and the corresponding content stored is
shown in table.
A2 A1 A0 Decimal Memory Contents of the
Equivalent Location memory location
0 0 0 0 0 M(0)
0 0 1 1 1 M(1)
 0 1 0 2 2 M(2)
0 1 1 3 2 M(3)
1 0 0 4 3 M(4)
1 0 1 5 5 M(5)
1 1 0 6 6 M(6)
1 1 1 7 7 M(7)

M(0) is the content of memory location 0. It has 4 bits here. M(1) is

the content of memory location 1 and so on. It can also be shown
us.

AB--- address bus.

The three address lines A2 A1 A0 together is known as address

bus. It is a unidirectional bus. The microprocessor always sends the
addresses.
In general, a Nxm memory shall have K address lines
designated Ak-1 Ak-2 Ak-3 A2A1A0, such that K is the smallest
integer satisfying the inequality 2k N. e.g. 200x8 memory shall have
200 memory locations 8 bit of information. To identify 200 memory
locations we require a minimum of K= 8 lines designated A7 A6 A5 A4
A3 A2 A1 A0. However K = 8 address lines can identify a total of 256
memory location starting from (0000 0000)2 to (1111 1111)2 or 00H to
FFH. but we are using only 200 memory locations and rest locations
are redundant. The 200 memory location shall be identified starting
from (0000 0000)2 to (1110 0111)2 or 00H to E7H. The other
combinations 1110 1000 B to 1111 1111 B or E8 H to FF h are not
used in this memory & are redundant addresses.
Since it is too tiring & boring to use binary numbers for identifying the
addresses we normally make use of hexadecimal number notation.
E.g. 200 memory location are identified starting from (00)H to (C7)H
,(C0)H to(FF)H are redundant memory locations. Using 10 address
lines designated A9A8A7..A2A1A0, we can directly address 210 =
1024 memory locations. This is conventionally known as 1K memory
locations.
The capacity of a memory is specified terms of the maximum
number of words the memory can store. In general, if the memory
has an R bit address and each word is of length m, then the memory
has a capacity of 2R*m bits, organized as 2K words each of m bits. If
R=10, then the memory can store 1024 words or 1K words. In most
of the 8 bit p the ps has 16 address lines. Therefore it can address
directly
216 memory locations = 20 x 210 memory locations
= 64 K memory locations
= 65536.
Thus, 8-bit microprocessor provides a maximum of 216 or 64 K
memory addresses ranging from 0000 to FFFFH.
Lecture-6
Characteristics of Memory:
An important characteristic of a memory is whether it is volatile
or non volatile. The contents of volatile memory are lost if the power
is turned off. On the other hand, a non volatile memory retains its
contents after the power is switched off. The best known non volatile
memory is magnetic core.
In the broad sense, a Cs memory system can be logically
divided into three groups:
1) Processor memory
2) Primary or main memory
3) Secondary memory
Processor memory refers to a set of P registers. These
registers hold temporary results when a computation is progress.
There is no speed disparity between these registers and the P
because they are fabricated on the same chip using the same
technology.
Primary memory is the external memory to store both program
and data. The P can access their memories directly. In earlier days,
the primary memory was designed using magnetic cores. In modern
Ps, MOS technology is employed in the primary memory design.
Usually, the size of primary memory is much larger than the
processor memory and its operating speed is slower than that the
processor registers by a factor of 25 or 30.
Secondary memory refers to the storage medium compositing
slow devices such as hard disks and floppies. These devices are
used to hold large data and huge program that are not needed by the
processor frequently. Sometimes, secondary memories are also
referred to as auxiliary or back up storage.
In order to design an efficient memory system, the following
characteristics of memory must be known.
The most important factor of a memory system is its cost,
expressed in dollars per bit. A good design implies a very low cost
per bit.
There are two parameters that will indicate the speed with
which information can be transferred in and out of a memory.
1) Access time, tA
2) Cycle time, tC
The access time tA is defined as the average time taken to read
a unit of information from the memory. Sometimes the access time is
also referred to as read access time. Similarly, one can define write
access time. Usually, the write access time will be equal to read
access time. The cycle time tC of a memory unit is defined as the
average time lapse between two successive read operations.
The reciprocal of access time is called the access rate (rA=1/tA),
which is expressed in bits per second. Similarly, the reciprocal of
cycle time is referred to as date transfer rate or bandwidth also
expressed in bits per second.
The third important characteristic of memory unit is its access
mode. The access mode refers to the manner in which information
can be accessed from the memory. There are two major access
modes. They are the random access mode and sequential access
modes. In random access mode, any memory location access time is
independent of the location from which the date is read. In sequential
access mode, the memory is accessed strictly in a sequential
manner. In this mode, the access time depends on the location in
which data is stored. They are also referred as serial access
memories. A bipolar memory and magnetic tape are typical example
for random & serial access memories.
Random access memories than its sequential access memory
2nd order to active a compromise. Some memories combine both
access modes and called semi-random memories. A typical example
is magnetic access whit one read/write head for each track. This
arrangement permits any track to be accessed. At random however.
Access within a track must be made in a serial fashion.

Classification of Memory:
In general, semiconductor memories can be clarified in two
main groups random access memories (RAM) and sequential access
memories (SAM).
RAM can be classified in three main groups as shown below.

ROMS:
The type of memory means the content of an address location
can only be read and cannot be written into. The contents of the
memory location are not destroyed whether the power is ON or OFF.
Such a memory is known as non volatile memory. ROMs are used to
store data on permanent basis. They are random access memories
and this makes them very useful for the storage of computer
operating systems, software language computers, look-up tables and
programs for dedicated microprocessor applications. ROMs can only
be read are not written into.

MASK ROMs:
Mask ROMs are programmed by a masking operation
performed on the chip during the manufacturing process. The
contents of a ROM are decided by the manufacture. These contents
are permanently stored in a ROM at the time of manufacturing. The
contents of MROMs cannot be changed by the user. Most desktop
computers use MROMs to contain there operating system and for
execution fixed procedures, such as decoding the keyboard and the
generation of characters for the CRT.

PROMs:
If user needs relatively few ROMs, there is a variation, which
cost more per devices but allows the user to in rest the information.
To avoid the high one-time cost of producing custom mask ROMs, IC
manufacturing provides user programmable ROMs. This device is
called programmable Read only memory. Using special equipments,
called PROM programmers, user can program a PROM- once.
Subsequently one can read the information out of PROM as often as
one wish, but one can never write into it again. Therefore once the
PROM is programmed with correct information it can be used as a
ROM only in microcomputer. If one needs to change or correct the
information stored in the PROM, one must pull it out, throw it away
and replace is with a fresh unused PROM, writing the new on
corrected information into this in used devices. The PROM will hold
its contents indefinitely.

These PROMs are provided with fusible links which are burned
during the programming. Once the data are permanently stored in the
PROMs, it can be read again and again by just accessing the correct
memory location.

EPROMs:
If a mistake is done in programming ROM and PROMs, the
correction cannot be made. The solution of this problem is erasable
PROM (EPROM). An EPROM is an erasable PROM. The contents
are erased by ultra violet light. Therefore, they are also called
UVEPROM. The user can not erase the content of a single memory
location, the entire contents are erased.
EPROMs can be reprogrammed using EPROM programmer.
Once programmed, it can be used as ROM in microcomputer. Later,
if one needs to correct the information stored, it is taken out from the
system, erase the program written, write new program into it and use
it.
The EPROM is erased by exposing an open window in the IC to
an ultraviolet light source for a specified length of time, typical erase
time vary between two and 30 minutes, the EPROM programmed and
providing proper addresses.
An EPROM also holds the information indefinitely once it has
been programmed. One can read the contents of an EPROM as often
as one like.

RMMs:
They are read mostly memories, since they have much slower
write time then read time, there memories are usually suited for
operation where mostly reading rather than, sorting will be performed.

E2PROMs:
E2PROM are electrically erasable PROM. They need not to be
removed from a microcomputer board for erasing. Erasing &
programming E2PROM is much easier as the ultraviolet sources are
not required. The stored information can be erased by applying a high
voltage of about 21V, a singly byte or the entire chip can be erased
in10 mille sec. This is faster than UV erasing and it can be done
easily while the chip is still in circuit, It is also known as EAPROM
(electrically alterable PROM). One can write into at any time without
erasing prior contents. The problems with EAROM are that
electronically they are relatively difficult to use also, they slowly lose
their information.
One application of the E2PROM is in the tuner of a morden TV
set. The E2PROM remember (i) the channel, you were watching
when your tuned off the set (2) the volume setting of the audio
amplifier.
RWMS:
In this type of memory one can either read the contents of an
addressed location in a MEMORY READ operation or one can write a
m bit of data in the addressed memory location in a MEMORY
WRITE operation. It is a volatile memory. It is normally known as
RANDOM ACCESS MEMORY (RAM). The content of RWM shall be
destroyed when the power is OFF. During of MEMORY REALD
operation the content of the addressed location is not destroyed. It is
only read onto the external data bus. During a MEMORY WRITE
operation, however, the original content of the addressed location is
destroyed and the new content takes it placed which is just now
written.
Read/write memories are used for temporary storage of data
and program instruction in a up based septum there are also RAMs,
RWMs are generally called RAMs, RAMMs a specific terms it tells
that the data can be read on written to any memory location,
RAM is classified as either static on dynamic, static RAMs
(SRAMs) flip flops as basic storage elements; whereas the dynamic
RAMs (DRAMs) use internal capacitor as basic storage elements,
additional refresh circuitry is needed to maintain the charge on the
internal capacitor of a dynamic RAM; they have more packing
density, there it has more storage capacity per unit area team a
static RAM, the cast per bit of dynamic RAMs is also much less than
that of the static RAMs.
Non-volatile RAM:
A Non-volatile RAM combines a static RAM and E2PROM into
the same chip. Such a device operates as a normal RAM. If power
supply fails the entire content of RAM are stored in E2PROM by a
single signal . A signal can transfer data from
E2PROM back into the RAM. E.g. x2201 is a non-volatile RAM of 1K
bit. The transfer time is 4msec.
Lecture-7
The symbolic diagram of a static RAM and ROM are shown below:

= Chip selection to control input.

= output enables signals.
Both the control signals are active low (in general) but they may
be active high, when the chip is selected then only addressed
memory location data is available on data lines provided is active.

= Chip selection to control input.

= output enables signal
= write enable signal
These are representative signal. These signals may be LOW or HIGH
for other ROMs. For READ operation, first address is placed and then
make = LOW, the output is available. Under WRITE operation
may be HIGH or LOW but is active LOW. Under READ operation
is ACTIVE LOW but must be HIGH.
All these memories are random access memories. In RAM any
memory location can be accessed in a random fashion without regard
to another location. The access time is same for each memory
locations.
INTEL 2716 EPROM:
This is an Ultra Violet Erasable Programmable ROM {UVEPROM}.
The pin connection & logic symbolism is shown in fig. (a) and (b)
respectively. It is a 2Kx8 ROM. It has 2048 memory. It has 11
address lines. While programming Vpp must be held at 25 volts. It this
chip is used in a microcomputer after programming this voltage must
be held at +5V.

Figure (a)
The pin details are given below:
GND = +5V and Ground
- address lines
data lines
Programming voltage
= output enables (to enable the output data buffer)
/PROG= dual function pin. While programming HIGH pulse is
applied at this pin and during read operation the chip is selected
enabled by making pin low.

When it is completely erased then each bit must be 1. If we want to

store 0 we write 0 there. Before programming each address stores
FFH but to store any data at the addressed location a 50ms pulse is
given to the PROG.

For programming 2716 is connected as shown in figure and following

operations are done in sequence:
1. Apply 25V dc to pin no 21(Vpp).
2. Keep the (output enable bar) high (+5v).
3. Establish the address at the address bus.
4. Established the desired data to be stored at the addressed
location on then data bus.
5. A positive TTL pulse of 50msec duration is applied to the pin
no. 18 ( /PROM).

The waveforms during programming are shown in figure below:

The above procedure is repeated for all location to programme all the
2K memory location. One can programme 2716 partly as required. All
the above actions are carried out in separate unit known as EPROM
programmer. It requires only 100sec to programme all the memory
locations.
Once the programme is written down in memory chip, it cannot be
erased. If we want to change it we put it in UV eraser and erase it and
then programme it again.

Once the chip is programmed, it can be used to read data again

as again. When the two inputs and are in their normal state
(HIGH) the output is tri-stated. Now one can only perform a
MEMORY READ operation from this device. The following is the
procedure for a MEMORY READ operation.
1. Establish the addresses of the memory location to be read on
the address bus.
2. Make the signal ACTIVE LOW.
3. Apply a control signal to terminal i.e. make the
ACTIVE LOW.
 is normally HIGH by the microprocessor and to read date low
is generated. This is known as MEMORY READ operation. The
waveforms during read operation are shown in figure below:

The wave forms of the chip show that the data out puts became valid
after a delay for setting up the addresses on enable the chip on
inability the output whichever is completed last.

INTEL 6116 RAM:

It is 2Kx8 memory. It is a static RWM (2Kx8). This is pin by pin
compatible with 2716 ROM. The pin connection is shown in fig.(a)
and the logic symbolism is shown in fig.(b).
Fig (a)

Fig (b)
The truth table for control signals are as follows:
Operation REMARKS
The data available on the data bus shall
0 0 X WRITE be written on the addressed location. The
original contents are lost. The new labes
it place
The content of the addressed location is
0 1 0 READ READ on to the output data line 0-00. The
content other addressed location is not
destroyed.
No
0 1 1 operation Output is Tri state.
*tri stated
No
1 * * operation Output is Tri state.
tri stated

The two chips 2716 and 6116 are pin by pin compatible and can be
used in place of other. The pin by pin compatibility of 6116 with 2716
has a advantage. In the initial stage of a programme development we
fix up 6116 in the 24 pin socket provided on the microcomputer and
develop the programme. After a lot of effort we are ready with a
permanent programme. Once the programme is completely tested
and satisfactory then using a PROM programmer the programme can
be transferred to 2716 ROM for permanent storage. Thereafter, 2716
can be put directly to the same socket occupied by 6116. A simple
jumper should be provided for pin no 21. This is shown in figure
below.
Lecture-8
Dynamic RAM chip:
A dynamic RAM comprises storage cells that may be thought of
eclectically as capacitors there are many thousands of these
capacitors, or storage cells on a dynamic RAM chip, each all is
capable of storing one bit of information.
The capacitor that makes this storage cell is not ideal. That is,
change placed on this capacitor will leak off given enough time. In a
DRAM, the change on the capacitor represents the stored data.
Therefore, the data stored in the cell can be lost. A more accurate
model of the storage cell is a capacitor in parallel with a resistor.

To keep the stored information in a cap cell, DRAM is refreshed

again & again. In a dynamic RAM, the storage wills are organized in a
matrix form. Fig shows, the organization of 16cells in a matrix of
4rows & 4 columns. Each cell in a matrix has a unique position
specified by the intersection of a row& a column.
 Using Row & Column, any cell can be uniquely identified.
External signal lines are used to indicate which storage cell in the
internal matrix is to be accessed. These lines are called row address
lines & column address lines.

Due to the way in which DRAMS are fabricated, the storage

capacitor is not capable of providing large Q/P current to an external
load. Therefore a circuit called sense amplifier is placed at the output
of the storage cap to increase the Q/P current drive capability of the
cell.
 Solid state switch S, is fabricated in the DRA chip to isolate the
storage cell from all circuit external to that cell S1 is closed when
the row address & etc. address corresponding to the storage cell are
selected upon clearing s1, the change stored on the capacitor flame
through s1 & RL. Current flawing through RL causes a voltage drop
arose RL, the voltage developed across RL is increased by the sense
amplifier to a lever suitable for during an external load (which is
usually TTL),
 When S1 is closed, current flews thought r1 and change on the
capture is lost, this type of read is called destructive read operation
the data should not disappear in read operation. A latch is used to
refresh the stored data as shown in fig;

4116 dynamic RAM chip:

4116 is a161kv dynamic RAM, the chip has 16,384 storage
cells in its matrix from and as commonly referred to as a 16kk X 1 bit
DRAM, there are 16k unique memory location, storage cell A block
diagram of the chip is shown below;
Storage cell matrix block:
There are 16,384 storage cell in the 4116 organized in a cell
contains a storage cap & an.ssw which isolates the cap from the rest
of the incant in DRAM.

Address latch block:

Seven address lives A1-AO are input to this block, after proper
time, an address is latched in the address latch block, the output of
this block is input to both the how decode & the col multiplexer block.
Row address Recorder block:
The block have seven input line &128 output lines, seven
output line represent one now of the storage matrix cell.
Sense address Decoder block:
The output of the col of cells in the storage matrix are tied
together on a single line celled a bit line; there are 128 bit line in the
matrix and 128 sense amplifier.

Data latch block:

After data is read from a now of cells, it is mitten into the
latches in this block.
Column Multiplexer block:
Only are of 128 line input to this block is switched through to
the DOUT output lines the seven address signals input to the DRAM,
chip determine which one is selected.
Time block:
The sequence of events that take place within the DRAM is
determined by this block also provides control signal to most of the
other block the DRAM.
Pin out of 4116:
A6-A0: The up accesses are memory cell by outputting the row&
column address on these seven lines.

: When the up has output the col address on the A5-A0 lines, the
line is assented internally.

: When is asserted, the read add on AR-AO line is latched

internally.

DIN: Data is stored in the cap cell by making this line o or 1. After
the row & ecol address are latched internally, the up writer to the cell
by places data on this line.

DOUT: Data is read from the RAM chip their line, after the row & col,
address are latched internally, the selected cell entreats are output to
the line.

Lecture-9
Intel 8085 Microprocessor
It is a 40-pin DIP(Dual in package) chip, base on NMOS technology,
on a single chip of silicon. It requires a single +5v supply between
Vcc at pin no 40 and GND at pin no 20. It can address directly 216
memory locations or 6536 memory locations or 64k memory locations
using 16 address line (A15-A0).
Pin no 28 to 21 gives as the higher order 8 bits of the address (A15-
A8).these 8- address lines are uni-directional tri-state address lines
these address lines becomes tri-state under three conditions namely.
(a) During DMA (direct memory access )operation
(b) When a HALT instruction is executed
(c) When is being RESET.
A15-A8 at pin no 19 to pin no 12 pin no 19 to pin no 12, marked A7-
A0 is used for dual purpose. The during it operation shall move
from one state to the other. There are ten (10) different states for the

(1) RESET STATE (TRESET) can be in TRESET state for an

integral multiple clock cycle.
(2) WAIT STATE (TWAIT) can be in this state for an integral no
of clock cycle. The duration being determined by an external
control signal input marked READY.
(3) HOLD STATE (T HOLD) depends upon the external control
signal input HOLD.
(4) HALT STATE (THALT) enter there state when an ILT
instruction is executed by it remains in this state till such time
when an external signal dictated by the use asked the to
perform further duties.
(5) The other states, the can be IN are marked T1,T2,T3,T4,T5 &
T6 states each of them states are of one clock period duration
each of there states clearly identifies the predetermined timing
 slots T1,T2,T3,T4,T5 & T6 perform specific very well defined
activities during these states.

Pin Configuration of Intel 8085A Microprocessor:

Pin no 19 to pin no 12 shall be utilize by the to sent lower order
bits of the 816 bit of information during T1 timing slots and therefore,
the same 8-points shall be utilized as bi-directional data bus (BDB)
for data transfer operation in the subsequent timing slots T2 & T3
Hence these pins are designated AD7 to AD6
These 8- lines are also tri-state line they will be tri-stated during T4,
T5 & T6 states. They will also be tri-stated during DMA operation and
when a HALT instruction is executed. These lines will also be tri-
stated for a very-short duration of time (few neon sec) between T1 &
T2 states.
ADDRESS LATCH ENABLE (ALE) AT PIN NO 30
it is a single pulse issued every T1 state of the as shown on
fig-2.since the lower order 8-bits of the address information A7 to A0 is
available at pin no 19 to 12, when ALE pulse exists at pin no 30. We
can use these information to latch the lower order bits of the address
externally using (say) an 8212 register latch once save on an external
latch the lower order address A7 to A0 shall be available at the output
of the register latch for the subsequent states T2, T3, T4, T5 & T6,
while pin no 19 to 12 can then be utilized by the for bi-directional
operation.
The manner of utilization of pins 19 to 12 is known as time
multiplexed mode of operation.
De multiplexing the Address bus AD1 AD0:
The 8085 A uses a multiplexed address-data bus. This is due to
limited number of pins on the 8085A-IC. Low-order 8-bits of the
memory address (or I/O address) appear on the AD bus during the
first clock cycle. (T1 state of an m/c cycle) It then becomes the data
bus during the second and third clock cycles (T2 and T3 states). ALE,
address latch enable signal occurring during the T1 state of a m/c
cycle is used to latch the address into the on-chip latch of certain
peripherals such as 8155/8156/8355/8755A. These chips ALE input
pin is connected to the ALE output pin of the 8085 A, thus allowing a
direct interface with the 8085 A. Thus IC chips internally de multiplex
the AD bus using the ALE signal. Since a majority of peripheral
devices do not have the internal multiplexing facility, there is external
hardware necessity for it.
Fig. shows a schematic that uses a latch and the ALE signal to
de multiplex the bus. The bus AD1-AD0 is connected as the input to
the latch 74LS373. The ALE signal is connected to the enable (G) pin
of the latch, and the output control (OC) signal of the latch is
grounded. When ALE goes high during the T1 state of a m/c cycle, the
latch is transparent in the output of the latch changes according to the
input. The CPU is putting lower-order bits of address during this time.
When the ALE goes LOW, the address bits get latched on the output
and remain so until the next ALE signal.

Read & Write Control signals at pin no 32 & pin no 31 &

The BDB at pin no 19 to 12 are used for bi-directional data transfer

operation T2 & T3 states when the BDB is inputting the information
from the external world into the , we say that is in READ MODE
and operation is READ operation. When the is outputting 8-bit of
information to the external world through BDB we have a WRITE
operation is in OUTPUT MODE or WRITE MODE. To tell the
external world that is in WRITE MODE. Issues a control signal
output at pin no 31 it is normally HIGH & becomes active & LOW.
It goes LOW during T2 state and goes HIGH again during T3 state of
the. This is shown is fig.3
When the BDB is in the input mode for READ operation, the
control signal. Output goes Low during T2 state and goes HIGH
during T3 state. Note that the normal state of is HIGH. Also note
that for obvious reasons & are not made active LOW
simultaneously. Note further whenever, the BDB is made to be in the
INPUT MODE by the , it issues the control signal output by
making it active LOW as described and it is for the user to beep the
appropriate 8-bit data either from the memory or from a peripheral
device at this appropriate time similarly during a WRITE operation
first send the desired address in the address lines during T1 states.
Thereafter, if places the desired 8-bit data on the BDB which is na in
the output mode and then issues the control signal output as
described. It is for the user to take appropriate action externally by it
interfacing circuitry so that the data so placed goes to the appropriate
device.
IO/ at pin no 34
O/ is an output tri-state control signal. It is active both way
whenever the address issued by the on the address lines refers to
the memory then the makes IO/ LOW throughout T1,T2,T3,T4,T5
& T6 states to indicate the external world that the address so sent
belongs to the memory and data on the BDB refers to the memory.
Whenever the address in the address lines. Refers to an I/O device
the makes IO/ control signal output HIGH to tell the external
world that the address in the address lines refer to I/O device and the
data in the BDB refers to an I/O device.
Note that IO/ signal is LOW or HIGH as the case may be
throughout six timing slots T1,T2,T3,T4,T5 & T6 states. It is for the user
to make use of the facilities give to develop proper interfacing
circuitry.
Lecture-10
READY at PIN NO 35
this is a control signal input. There are many peripheral devices
which are slow in operation can be to the speed eg. The occurs
time of a memory interfaced with a may be much larger than the
clock period of the Thus is a need for telling the that the device
so addressed by the is not ready for data transfer operation. The
device, selected should have the ability to generate a control signal
output READY which shall be LOW of the device is not ready for data
transfer operation and goes HIGH when the device is READY for
data transfer operation.
This idea is summarized in fig-4 considering memory as the external
device.

The sent the address during T1 state of the to address the

memory and then issues appropriate RD or WR signal during T2
 state either to read the memory or write into the memory Having
issued the appropriate or signal during T2 states the
monitors. READY control signal input if the READY control signal
input LOW the knows that the device addressed is not ready
for data transfer operation and therefore goes to WAIT state
(TW). Once in WAIT state, the does not do any other work
except monitoring control signal as long as READY signal is
LOW, remains in WAIT state when the READY signal goes
HIGH realized that the device addressed is ready for data
transfer operation and comes out of the WAIT state and goes into
T3 state. The partial state dig describing the above process is
shown in fig.5.

The appropriate control signal output or shall remain LOW

throughout the TW state and goes HIGH when the comes out of
the WAIT state and goes to T3 state the corresponding timing signals
are shown below. In fig-6.
 at pin no.36

It is an input control signal normally HIGH and active LOW. It is used

to RESET the to its initial state. The initial state of the shall be
described later. During power ON the must be RESET. The
necessary circutary for resetting the is shown in fig-7. Initially the
capacitor is discharged therefore to start with when the power is first
ON, control signal is LOW. Therefore the will be RESET
to its initial state. Depending upon the time constant RC the voltage
across the capacitor experientially increases to 5 volts. When the
voltage across the capacitor reaches to 2.4 volts, control
signal goes to logical 1. Comes out of the RESET state and
straight away goes to T1 state. The time duration to reach around 2.4
volts from the instant of switching the supply is around 4 to 5 CLK
cycles. If this duration is not maintain the resetting action of the is
not guaranteed and therefore, RC combination should be selected
accordingly.
The diode D in fig-7 is to provide for the discharge path for the
capacitor charge voltage. Whenever the power supply is finally put
OFF the push bottom switch provided in fig-7 can be used to RESET
the to its initial state as and when necessary during the functioning
of the The partial state diagram when Control signal is
active is shown-in fig -8
RESET OUT at PIN NO 3 It is normally LOW, when
control signal is HIGH. Reset out goes active HIGH as long as
is active LOW. This RESET OUT control signal is provided
for the user to use it RESET all the peripheral devices to their initial
states.
It is normally low signal output. It indicates 8085 A is being
RESET. When RESET IN control signal is low, RESET OUT goes
HIGH. It remains HIGH as long as RESET IN is active and LOW. This
output is used to reset other devices used in the microprocessor
system. The signal is synchronized with the system CLK and it
remains high for an integral no. of clock periods. After the RESET IN
goes HIGH, RESET OUT goes LOW, the microprocessor enters in
the T1 state and normal operation begins.

X1,X2, terminal at pin no.1& 2 and CLK (OUT) at pin no.37 :

Intel 8085A provi9des on chip crystal oscillator circuit which is
shown in fig-9.
A crystal has to be connected across X1& X2 to provide a crystal fq of
fc MH3. Because of the internal T-F/F the operating fq , clock is fc/2
(half the crystal fq). The , clock is also buffered and sent out through
pin no 37 to the outside world as clock (OUT) signal clock (OUT)
signal is used for synchronizing the operation. The data sheet of 8085
puts a lower limit, to the operating fq at 500 kH3. The max operating
fq limit fq for 8085 A-2 is 5MH3. Therefore, while using 8085A , a
crystal having a +q from 1MH3 up to 6.25 MH3 can be used; 10MH3
crystal has to be used for 8085A-2 . The 20pf capacitor on fig-9 is
necessary between X2 and ground if the crystal fq is less than 4 MH3
to provide for proper oscillation. It is not necessary for higher gq. The
data sheet also mentions 15pf. Sheet capacitors across X1&X2
internally.
A crystal is to be used across X1&X2 to get stable fq of oscillation if
stable fq of oscillation is not necessary in our application, then a L-C
network or a R-C network can be used as shown in fig 9(b) & 9 (c).
 The frequency of oscillation of fig 9(b) is given by
f=

The data sheet recommends as external capacitance of around. If a

large variation of fg can be tolerated in our application then fig-9(c)
can be used. Fig-9(c) is for 3MH3 oscillation. No other fq is
recommended using the connection if we have an external clock
whose fq is same and can be varied from 1MH3 to 6.25 MH3, then the
external clock can be connected as shown in fig-9(d).
If we have an external clock whose frequency is same and can
be varied from 1MHz to 6.25 MHz, the external clock may be
connected to x1 and x2 is left open. If the driving frequency is 8 MHz
to 12 MHz, stability of the clock generator will be improved by driving
x1 and x2 with a push pull force. To prevent self oscillations of the
8085, x2 should not be coupled back to x1 through the driving circuit.
In last two cases, pull up resistors are required to assure that the high
level voltage of the input is at least 4v and maximum low level voltage
of 0.8V.
Lecture-11
INTERRUPT CONTROL SIGNALS TRAP at pin no 6, RST 7.5 at
pin no 7,at pin no 6.5 at pin no 8, RST 5.5 at pin no 9, and INTR at
pin no 10 are interrupt control signal input provided for interrupting
the while it is executing the main programme. These interrupt
control signal input can be broadly divided in to two categories.
(a) Non maskable interrupts
(b) Maskable interrupts
Non maskable control signal input are those control signal input
which can interrupt the programming execution once the power is
ON. The maskable interrupts are those control signal inputs which
can be individually disabled or enabled as and when necessary, once
the power is on. The TRAP signal control input of INTEL 8085 is NMI
(non-maskable interrupts) signal.
The way these interrupt control signal input interrupt the can be
pictorially represented as shown in fig.10.

TRAP at pin no.6:

TRAP is a non maskable RESTART vectored interrupt. When
the power is ON, it is enabled and enable interrupt command is
required TRAP has the highest priority of any interrupt. It is both
raising edge and lends sensitive interrupt i.e. it becomes active at the
Lo-Hi edge but must stay high until it is sampled and recognized.
Whenever this interrupt is recognized, it forces the 8085 A to perform
a CALL (0024) H instruction, means when the current execution is
over, the PC is loaded with 0024 H so that the CPU starts executing
the program from 0024 H.

INTR at pin no.10:

This is the lowest priority interrupt request in the 8085 A
processor and is used as a general purpose interrupt. An input of
INTR=1 implies some external device has put up an interrupt and
wants the CPU to execute an appropriate service routine. The 8085 A
monitors the status of the INTR line by sampling it in the last but one
clock cycle of each instruction and during HOLD & HALT states. If the
interrupt structure of the 8085 A is enabled when INTR is sampled
high, the program counter (PC) will not be incremented and an
INTA=0 will be issued by the in response to INTR. It is now the
responsibility of the interrupting device to issue a RESTART or CALL
instruction so that the 8085 A can jump to the proper interrupt service
routine.
 The INTR is enabled by executing a EI instruction and is
disabled by executing a DI instruction. Disabled means INTR will not
be acknowledged. It is also disabled by RESET and immediately after
an interrupt is acknowledged.

INTA at pin no.11:

(Interrupt acknowledge) This is an active low control signal
output. When the acknowledges the interrupt than instead of RD
signal it issues INTA signal to tell the external world that it is in
interrupt acknowledge m/c cycle. Basically, it replaces RD control
signal output during INTA m/c cycle. INTA is normally high and
becomes active low during T2 timing slot of the and goes high
again during T3 state of the just like RD signal. During this period
RD signal is HIGH. It can be used to activate an 8259 A interrupt chip
or some other interrupt port.

RST 5.5, 6.5 & 7.5:

These are 8085 As maskable restored interrupts. They operate
exactly like INTR except for the following:
1. The RESTART instruction is automatically inserted by internal
logic. It does not have to be provided from outside. These
instructions are:
RST 5.5 CALL 0020 H
RST 6.5 CALL 0034 H
RST 7.5 CALL 0030 H
The address for any RST can be calculated multiplying the RST
number with 8 and converting it into hex.
 E.g. For RST 5.5 the address is 5.5x8 = 44D = 002C H
2. RST 7.5 is an edge (LO-Hi) sensitive interrupt unlike RST 6.5,
RST 5.5 and INTR which are lend (High) triggered.
3. These three interrupts can be individually masked or unmasked
using SIM instructions.
4. They have higher priority than INTR, among them RST 7.5 has
the highest priority and RST 5.5 has the lowest priority.
Like the INTR, whenever any of these interrupts is recognized it
disables all the interrupts. These interrupts can be enabled/disabled
using EI/DI instruction.
M7.5 (Mask 7.5) is a FLIP-FLOP, R7.5 (RESET 7.5) is a flip-
flop. It is normally RESET when the power is on. Only LOW to HIGH
transition of RST 7.5 will SET the FLIP-FLOP and stores in R7.5.
When M7.5 is RESET only then this signal can interrupt the . R7.5
provides a seat (MASK is said open when it is RESET). A common
chain (MASK ENABLE FLIP-FLOP) is provided for all the MASKS.
This MASK ENABLE must be SET for individually enabling or
disabling the MASK doors.
The pictorial representation shown in fig-10 is self-explanatory.
The following FLIP-FLOPs are internally provided in the interrupt
system of the .
1). INTE FLIP-FLOP
When this FLIP-FLOP is RESET, the entire interrupt system is
disabled except for TRAP & no other interrupt control signal can
interrupt the . When the INTE FLIP-FLOP is SET, the interrupt
system is enabled and the other interrupt control signal can be
selectively enabled or disabled.
When the power is ON for the first time goes LOW
and it RESET, the INTE FLIP-FLOP so that the entire interrupt
system is disabled as described above. Then the INTE FLIP-FLOP
can be SET or RESET using instructions.

2) INTA FLIP-FLOP (Interrupt acknowledge

This is used only for internal operation by the .when first the
power is ON this FLIP-FLOP will be RESET by the control
signal. Thereafter, whenever a valid interrupt is recognized by the
it always RESETs the INTE FLIP-FLOP and then SET, the INTA
FLIP-FLOP. Before further action thus, further interrupts shall not be
recognized, unless, user through instructions in the programme
desires further recognition of the interrupt. This statement shall be
elaborated further in the interrupt chapter.

MASK FLIP-FLOP (M5.5, M6.5, M7.5)

These Mask FLIP-FLOPs are used individually to MASK the
interrupts RST5.5, RST 6.5, RST7.5 (RST stands for RESTART).
When these FLIP-FLOPs are individually SET, then the
corresponding interrupt is masked and the interrupt control signal in
question can not interrupt the (see fig-10). These Mask FLIP-
FLOPs can be individually and selectively CLEAR to 0 through SIM
instruction (SET INTERRUPT MASK) provided a particular FLIP-
FLOP known as MASK ENABLE FLIP-FLOP is also SET (set fig-10)
MASK ENABLE FLIP-FLOP can be SET simultaneously using SIM
instruction.

R7.5 FLIP-FLOP
The RST 7.5 control signal input is a LOW to HIGH transition
active interrupt control signal input. The LOW to HIGH transition of
the signal is registered in R7.5 FLIP-FLOP. Whenever M7.5 FLIP-
FLOP is CLEAR, the output of R7.5 is sensed and recognized as an
interrupt by the R7.5 FLIP-FLOP can be CLEAR through the
same SIM instruction. It is for the user to make use of these facilities.

With the above explanation, we can write the logic expression for the
logic variable, VALID INT.
VALID INT = 0 when none of the interrupt control signal input are
interrupting the microprocessor and VALID INT = 1 when any of the
interrupt control signal is active. Thus
VALID INT= TRAP+ INTE [INTR+R7.5 + RST 6.5 + RST
5.5 ]

(Interrupt acknowledge bar) signal at pin no.11

This is an active LOW control signal output replaces control signal
at pin no 32 during INTA machine cycle. when INTR control signal
input at pin no 10interrupt the tells the outside world that it is in
INTA machine by issuing IO/ =1 and also S1=1, S0=1throughout the
machine cycle output is normally HIGH and becomes LOW
during T2 timing slot of the and goes high again during T3 state of
the just like signal (note that =1 during this cycle).

SID & SOD at PIN NO 5 & 4

SID stands for SERIAL INPUT DATA and SOD stands for
SERIAL OUTPUT DATA. These two pins are specially provided in
8085 for communicating with serial devices, like CRT, TTY,
PRINTERS etc. as and when needed uses SID, SOD lines for
transfer of data bit by bit along the same lines more about these lines
when we talked about the use of RIM & SIM instructions.

Status Signals S1 (33) and S0 (29):

These two outputs along with IO/M signal output identify the
type of the machine cycle being executed by the 8085 A. These
signals are issued (or become valid) at the beginning of the machine
cycle and remain stable throughout the machine cycle. The falling
edge of ALE may be used to catch the state of these lines. The seven
types of machine cycles are:
1. Opcode Fetch Machine Cycle (OFMC)
2. Memory Read Machine Cycle (MRMC)
3. Memory Write Machine Cycle (MWRMC)
4. I/O Read Machine Cycle (IORMC)
5. I/O Write Machine Cycle (IOWRMC)
6. Interrupt Acknowledge Machine Cycle (INTAMC)
7. Bus Idle Machine Cycle. (BIMC)
The tells the external world the type of m/c cycle it is IN by issuing
the status signals IO/ , and throughout the machine

cycle. The truth table is shown below:

Machine Status signal Control Signal
Cycle
IO/M S1 S0 RD WR INTA
OFMC 0 1 1 0 1 1
MRMC 0 1 0 0 1 1
MWRMC 0 0 1 1 0 1
IORMC 1 1 0 0 1 1
IOWRMC 1 0 1 1 0 1
INTAMC 1 1 1 1 1 0
BIMC
HALT X 0 0

These control signal are normally HIGH and becomes active LOW
during T2 state and goes back to HIGH during T3 state. In between T2
& T3 states any no of WAIT states Tw can be inserted.

HOLD at pin no 39 and HLDA at pin no 38:

HOLD is a control signal input and HLDA is a control signal output
these two (hold acknowledge) signals are used for hand shaped
control during DMA operation (Direct memory access). The use of
these control signals are depicted in the function diagram of fig-12
The device asking for DMA makes the HOLD signal HIGH the
which continually monitor the HOLD signal input during even m/c
cycle recognizes that an external device is requesting for a DMA,
complete the current m/c cycle in, thereafter, tri -states the address
bus & the BDB (Bi-directional data bus), enters in to a HOLD states.
THOLD also while entering the HOLD state it issues the HLDA control
signal at pin no 38 HIGH. The external device asking for DMA
monitors the HLDA control signal and knows that the has gone
into the HOLD state when HLDA is HIGH thereafter, the address bus
and the data bus which are tri state with respect to the are in the
exclusive control of external signal asking DMA. The DMA operation
between the external device and memory continues
The while in HOLD state continues to monitor the HOLD control
signal input as long as it is HIGH it remains in HOLD state. The
external device performing the DMA operation, after completing its
operation makes HOLD signal LOW to tell the that the DMA is
over which is continuously monitoring HOLD signal in HOLD state
recognizes the above fact & comes out of HOLD state and continues
the operation from there it has gone into HOLD state.
Lecture-12
INTERNAL ARCHITECTURE OF INTEL 8085: The Functional Block
Diagram Of 8085 Is Shown In Fig 16.

It consists of five essential blocks.

(1) ARITHMEDIC LOGIC SECTION

(2) REGISTER SECTION
(3) THE INTERRUPT CONTROL SECTION
(4) SERIAL I/O SECTION
(5) THE TIMING AND CONTROL UNIT
The description of each unit follows.

There is an internal bi directional bus of 8 bits. All the internal registers

which transfer data to the internal bus are tri state registers.

(1) ARITHMETIC LOGIC SECTION: This section consists of

(a) Accumulation(A)
(b) Temporarily Register (TR)
(c) A flag register (FR)
(d) An arithmetic logic unit (ALU)

(1) ACCUMULATION (A): It is a 8 bit tri state register accessible

to the user. Its tri state output is connected to the internal bus in
addition, it has a two state 8 bit output. The content of the
accumulator is always available at this two state output as the
accumulator can be manipulated through instruction. Its content
can be incremented its content can be decremented. Its content can
be transferred to memory location. The content of a memory
location can be transfers to the accumulator. All these can be done
through instructions. The result of an arithmetic operation carried
out by ALU shall also be stored back in the accumulator the result
of the operation, hence the name accumulator.
(2) TEMPORARILY REGISTER (TR): This is an 8 bit register not
accessible to the user. It is used by the p for internal operations.
The second operand as and when necessary shall be loaded into
this register by the p before the desired operation takes place in
the ALU. The register has 8 bits two state output. This shall be the
second operand to the ALU.
(3) ARITHMETIC LOGIC UNIT (ALU): ALU is a combination
logic block which performs the desired operation on the two
operands. One from the A and the other from the TR as the dictate
of the control signals. Generated by the timing & control unit. In
8085 p binary addition operation, binary subtraction operations
are the only arithmetic section possible. The result of only
arithmetic section possible. The results of the operation shall the
stored back in a accumulator when the instruction to be executed is
 subtraction operation, then the content of the TR shall subtracted
from the content of the accumulator and result shall be stored back
in the accumulator.
(4) FLAG REGISTER: Flag register is a bit register accessible to
the user through instruction each bit in the flag register has a
specific functions only of the bit are used as shown in fig 17.
D7
D0
S Z AC P CY

The three crossed bits are redundant bits and not used. They can be either 0
or 1. It is immaterial but normally forced to be zero. These five bits are
affected as a result of execution of an instruction. All instruction execution
do not affected the flags e.g. data transferring operation do not affect these
flags the arithmetic operation effect all these flags the meaning & the effect
of the fleegs are as follow;

CY CARRY FLAG BIT: this particular bit is SET if there is a carry from the
MSB position during an addition operation or if there is a borrow during the
subtraction operation, otherwise this flag is RESET.

P-PARITY FLAG BIT: The E flag is SET if the result of an operation

contains even nos of 1s otherwise it is RESET.

AC- AOXILIARY CARRY FLAG BIT: This bit is SET if there is a carry
from A3 bit to A4 bit of the accumulator during the process of executing
operation connected with an accumulator otherwise it is RESET. The AE
flag is useful for arithmetic & is used in a particular instruction known as
DAA (Decimal adjust accumulates).

Z-ZERO FLAG: Zero flag bit is SET if the result of an operation is zero,
otherwise it is RESET.

S-SIGN FLAG: This flag is SET if the MSB of the result is a 1 otherwise it
is RESET. As an example, let us consider the execution of the instruction
ADDB. ADD is the mnemonic for addition B is the second operand. The
first operand is known to exist as the content of the accumulator. The
meaning of the instruction is add the content of the B register to the content
of A register and store the result back in the accumulator, symbolically, we
write the macro RTL complemented.

(A) (A) + (B).

Let us suppose the contents of the A& B register are,

(A) = 9BH & (B) = A5H.before the execution of the instruction. It

mean content of (A) & (B) are,
A 1001 1011
B 1010 0101

A B 1 0100 0000 A
cy 1111 1111 AC

As a result of addition there is a carry from A3 will be A4 position in the

example and therefore, AC will be SET. Also there is a carry from the MSB
cut & therefore CY flag will also be SET soon after the execution of ADD B
instruction the accumulator certain (A) = (0100 0000)2 40 H and is not zero.
Therefore the Z flag is RESET to zero. Also the result certain only one 1
an add number. Therefore the parity pit will also be RESET to 0, therefore,
the sign flag shall be RESET to 0. Thus the flag register contains soon after
the execution instruction are 0001 0001 B = 11H.

As a second example, consider another instruction DCR C. DCR is the

mnemonic for decrement. C is the operand. This information means
decrement the content of the C register by 1 and store it back in the C
register, the MACRO RTL implemented is

C C 1 C C

Let us suppose C contains (C) =D2H before the execution of the instruction
after the instruction, C shall contains D1H and therefore in not zero.
Therefore the flag register will be affected as follows.
 S Z X AC X P X CY
FR = 1 0 0 0 010 0

On the other hand, if a contains 01H just before the execution if the
instruction, C shall contain 00H. Since the result of the operation is 0 the
zero flag shall now be SET to 1. Other flag will be affected in the normal
way.

These flag bits are utilized in many instructions for branding operations
during the execution of a programme normally one of these bits are tested
for TRUE or FALSE condition depending upon the condition the
programme branches. This is shown in fig 18.

REGISTER SECTION:

There are 6-8 bit register designed B, C, D, E, H, & L. all are accessible to
the user. In an instruction these six 8bit register along with the accumulator
A shall be identified by a 8 bit code designated either SSS or DDD.
Whenever SSS is used, it corresponds to service register. Whenever, DDD is
used, it corresponds to destination register. The code used as follows,

SSS or DDD
000 ----- B
001 ----- C
010 ----- D
011 ----- E
100 ----- H
101 ----- L
111 ----- A
Note in the above code 110 is not used. Whenever 110 is used for SSS or
DDD, it means a specific register pair (H,L), together to from 16 bit register
known as memory address register (MAR) or M- pointer.

As an example consider the instruction MOV V1, V2

This is an ALP statement, MOV is the mnemonic for move, and V1, v2 are
the operand register, in the statement, V2 is the source register and V1 is the
destination register. The meaning of the instruction is MOVE the contents of
v2 register into V1 register5. Symbolically this basic operation can be
described by a basic RTL statement (V1) ---- (V2).
This is a single byte instruction. The single byte being the operation code.
The arrangement of the op code single byte is shown in fig 19.

V1 code V2 code
0 1 D D D S S S
Fig 19 (a) gives the example of MOV A, H code for this statement is,

0 1 1 1 1 1 0 0
For move fig 19 (a).

The opcode is read is together 0111 1100 B = 7CH. when the instruction7CH
is executed content of H register shall be transferred to A register. Note
that content of H register is not destroyed. However, the original content of
A register is lost. Let us take another example for the use of code 110.

Consider the instruction MOV D, M

This is an ALP statement, M is the source of the operand and D is the

destination register. MOV is the mnemonic for move. The meaning of the
instruction is move the content of this memory location whose address is
available in (H, L) pair into the D register. This is a single byte instruction.
The operation code is 01010110 B = 56 B
 Figure 20

Whenever the instruction 56H is executed content of the memory location

whose address is available in (H,L) pair shall be loaded into the D register.
The content of the memory location is not destroyed. However, the content
of the memory location Y1 Y0 H whose address is X3 X2 X1 X0 H available
in (H,L) pair goes into the D register. The original content of D is lost. This
is illustrated in fig 20. The six general purpose register B, C, E, H, L can
also be combined together as register pairs are possible. (B,C) pair with
lower order 8 bits & B higher order 8 bits; (P,E) pair , E lower order 8 bits,
D higher order 8 bits, (H,L) pair with L- lower order 8 bits & H higher
order 8 bits. There is another register name stock pointer, (S,F) which is 16
bits register itself. Whenever an instruction refers to the register pair (B,C),
(D,E), (H,L), or (S,P) a 2 bit code RP is used to identify the register pairs (R
stands for the register pairs. (R stands for one bit & P stands for other bit)

RP
00 ----- (B, C)
01 ----- (D, E)
10 ----- (H, L)
11 ----- SP --------- (SPH, SPL)
Lecture-13
PROGRAM COUNTER:

This is a 16 bit register accessible to the user. It always contain the

address of the next instruction to be executed in a program
sequence. Thus the program counter keeps the track of the program
execution up to which it is complete.

Whenever necessary, the address information available in PC shall

be sent out through the address lines & BDB during T1 timing slot.
The higher order 8 bits PCH shall be sent out through A15 A8
address lines & the lower order 8 bits program counter shall be sent
out through AD7 AD0.lines during T1 states since the BDB contains
the lower order 8 bit address information during T1 state an ALE
pulse is also used by p.

The above statement can be symbolically stated through macro RTL

shown in the figure 22.

T1 :(AD7 ASD0 ) , A15 A8 PCH , ALE

T2 :RD 0, (PC) (PC) 1

Whenever the address information sent from the program counter to

the external world during T. state, then the PC shall be incremented
by 1 down the subsequence T2 state so that program counter points
to the next sequential byte. This also shown in fig.

Note: If the address information for PC has not been sent out during
T state to the external world, them the PC will not be incremented
using T2 state.

Whenever the address information is sent out from the program

counter to the address bus (external world) then the PC is
incremented by automatically during the subsequent T2 state so that
the PC points to the next sequential byte. If the data required
provides instruction is of two bytes or three bytes long or it may be
the next instruction to be fetched and executed. If instructions are
sequentially arranged in memory, this will guarantee that they will
also be executed sequentially. Sometimes, program execution
requires that non-sequential instructions executed e.g. JUMP or
CALL type instructions. This requires the program counter to be
loaded with an entirely new value. An 8-bit with a 16-bit program
counter requires two data moves to completely modify the contents of
the PC. If the address information from PC has not been sent out
during T1 state, the external worlds then PC will not be incremented
during T2 state.

When the is RESET, the CPU initializes the PC to 0000 H.

Therefore, the first instruction in the program should be at 0000 H in
the memory address space of the CPU.

STACK POINTER REGISTER:

The stack is a storage structure. It consists of number of

sequential and RAM locations in which a saves the internal
register contents during subroutine calls and interrupts so that they
will not be changed or destroyed by a subroutine.

8085 can address directly 64K memory locations. This is

known as directly addressable memory space starting from the
address 0000 H to FFFF H. this entire memory area is usually divided
by the user into program area, data area and stack area. It is for the
user to see that program area and data area do not overlap with that
of stack memory area. The size of the stack memory area depends
upon the application.
 E.g. the user for a particular process control operation may
decide to reserve memory space starting from 2600 to 2700 as the
stack memory space. This is shown in fig.

The stack pointer is a 16-bit register accessible to the user. It is

required to address a memory location in the stack. It contains the
address of the top of stack into which last data is written. Writing data
into a stack is called a PUSH operation and reading data from a stack
is called a POP operation. In the fig. shown 2700 H is known as the
bottom of the stack. There is an instruction in the instruction set to
initialize the stack pointer register to the bottom of the stack. This
instruction is LXI SP, BADR.

LXI is the numeric for Load immediate, BADR is a symbolic

name given to the 16-bit address which is to be loaded into the stack
pointer. The meaning of the instruction is to load the 16-bit of data
immediately available in the instruction itself into the stack point. In
this example, BADR equals 2700 H. when this instruction is executed
the situation is shown in fig. the stack pointer now points to the
bottom of the stack.

Now, let us suppose that while calling a subroutine it becomes

necessary to save the contents of (BC) reg pair and (DE) reg. pair as
they are used in the subroutine. The process of saving the content of
a reg. is known as push operation. The push operation is performed
at the beginning of a subroutine to save reg. contents and the
instruction for pushing the contents of the internal register is PUSH.
E.g. PUSH B. The meaning of the instruction is to push the contents
of BC reg. pain on to the stack so that it can be saved there till it is
restored. PUSH B operation affects the stack and stack pointer as
follows. Since the stack pointer always adds the address of the last
byte of data pushed onto the stack, therefore when PUSH B
instruction is executed, the stack pointer is decremented by 1 and the
contents of the B register are copied onto the stack at that address.
The stack pointer is decremented again, and the contents of the C
register are copied to that addr. Just after the execution of PUSH B,
the situation is shown in fig.
 Similarly, to store the contents of (D, E) pair PUSH D
instruction is used. The meaning of this instruction is push the
contents of the (D,E) pair onto the stack to save them there as shown
in fig. just after the execution.

Since the contents of (B, C) & (D, E) reg. pairs are stored at the
top of the stack, these registers are now available for further
computation in the subroutine. At a later stage of execution of the
program after utilizing B, C, D, E registers, there may be a need to
restore the original contents to the respective registers. E.g. at the
end of the subroutine, the data is restored to the proper register.

The restoration of the contents is a READ operation from the

stack and is known as POP operation. A POP register instruction
copies the stored data from the stack buck into the indicated register
pair. Just before the execution of POP instruction, let us say the
situation is as shown.
 Note that regs B, C & D, E have same different contents
because these registers are used in the subroutine.

To restore the contents of B, C reg pair POP B instruction is

used. Whenever their instruction is executed, the contents of the top
of the stack are read into the register (B, C) pair. To restore the
contents of the top of the stack is read into the (D, E) reg pair. The
question in which sequence these instructions are to be executed so
that the contents are restored properly. The obvious sequence in
POP D first & the POP B in the data must be popped off in the
reverse order from which it was pushed. This type of stack is called
last in first out (LIFO) memory.

Just after the execution of POP D & POP B instructions the

situation is as shown in fig.

When POP D is executed the data from the top of the stack is copied
to reg. E, data pointer is incremented by 1, then the next byte of the
saved data is copied from the stack to the reg. D, and SP is further
incremented by 1.

This is similar to previous one but now some data has been
stored in the stack area but these are irrelevant anyway. They will be
destroyed during the next PUSH operation on the stack.
From the above discussion, following points emerge:
1. The stack pointer always points to the top of the stack up to
which it is full with relevant data.
2. Storing or saving the data on stack is known as PUSH
operation.
3. The restoring or reading data from the stack onto certain
internal registers are known as POP instructions.
4. The stack operates on Last in first out basis.
5. The stack pointer can be initialized to the bottom of the stack
but bottom of the stack cannot be utilized to store any useful
data.
6. It is for the user to see that the program area does not overlap
with stack area.
Lecture-14
W-Z:
When a 3-byte instruction containing 2 byte address is to be
executed by the , the first byte is the (op-code) which is fetched
and then decoded by the decoder. Then two memories read m/c
cycles are executed to read the two byte address one in each m/c
cycle and placed in W-Z register. During instruction execution, (in
next m/c cycle), the addr in W-Z register pair is transferred to the
address latch to address memory or I/O for data transfer.
Interrupt Control Section:
Sometimes it is necessary to interrupt the execution of the main
program to answer a request from an I/O device. For instance, an I/O
device may send an interrupt signal to interrupt control unit to indicate
that data is ready for input. The temporarily stops what it is doing,
inputs the data and then returns to what it was doing.
Serial I/O Control:
Sometimes, I/O devices work with serial data rather than
parallel. In this case, the serial data stream from an input device must
be converted to 8-bit parallel data before the computer can use it.
Likewise the 8-bit data out of a computer must be converted to serial
form before a serial output device can use it.
The SID input is where serial data enters the 8085. The SOD
output is where the serial data leaves the 8085. Two instructions
known as SIM & RIM allow the user to perform the serial parallel
conversion needed for serial I/O device.
Timing and control section:
 The timing and control section supervise the complete
operation of the . The on chip clock oscillator which produces the
internal clock is a part of this section. The timing and control section
also has a state generator to generate 10 different states namely
state generator is a multi
mode counter. The next state of the state generator from the present
state is decided by the many control signals like READ, HALI, INTR,
HOLD etc in each states then section of generator many control
signals for executing the instruction fetched.
The operation of the is cyclic in natural. During the normal
operation from the ward Go, sequentially and executes one
instruction after another until a HALT instruction is executed. The
fetching and execution of a single instruction constitutes an
instruction cycle. The instruction cycle consists of one or more read
or write operation to memory or an I/O device each memory I/O
reference requires a mechanic cycle. In other words every time a byte
of data is more from CPU to I/O or memory or from memory I/O to
cpu , a machine cycle is required.
There are seven different kinds of m/c cycles in the 8085 A:
1. OPCODE FETCH
2. MEMORY READ
3. MEMORY WRITE
4. I/O READ
5. I/O WRITE
6. INTEROPT ACKNOLEDGE
7. BUS IDLE
 Three status signals IO/ generated at the beginning of
each m/c cycle (and generated during state of
the M/C cycle) identify each type of the m/c cycle the station signals
remain valid for the duration of the cycle. The instruction fetch portion
of an instruction cycle requires a machine cycle for each byte of the
instruction to be fetched since instruction consist of 1 to 8 bytes (1,2
or 3), the instruction fetch Is one to three machine cycles in duration.
The first m/c cycle in an instruction cycle is always an OPCODE
fetch m/c cycle which is always single by long and the 8 bits obtained
during an OPCODE FETCH are always interpreted as an OPCODE
of an instruction. Note that to fetch an instruction is to transfer an
entire instruction from memory to the necessitates an OPCODE
FETCH m/c cycle. However, one or two memory read m/c cycles are
also needed to complete the fetch for 2&3 byte instruction
respectively.
The number of m/c cycles required to execute the instruction
depends on the particular instruction. Some instruction require no
addition m/c cycles after the instruction fetch is complete, other
requires additional m/c cycles to write or read data to or from memory
or I/O devices from one to five. Around 50% of the instruction
requires only one m/c cycle for fetching and executing the instruction,
no instruction requires more than five m/c cycles M/C cycles like the
memory read or memory write may occur more than once a single
instruction cycle.

MC-1 MC- MC-3 MC- MC-5

 2 4
INSTRUCTION cycle
The shaded area may be required for executing the
instruction. The timing and control unit of automatically generates
the proper m/c cycles required for an instruction cycle from
information provided by the op-code.
Each m/c cycle contains a number of 320ns clock periods
when cryptal used is 6.25MHz. One clock period, i.e. the period
between two negative going transitions of that clock is called T state.
The various T-states are . Most of the m/c cycles
have 3 T states each ( only OPCODE FETCH MC has
either 4 or 6 states depending on the instruction. The first 3rd states of
the mc are identical to a MRMC, the additional T states in OFMC are
the T states required by the 8085 A to decode the op code and
decide what actions are needed in succeeding MCS.
The combined MCS along with T-states are shown in fig.
MC-1 MC-2 MC-3 MC-4 MC5

MC-i (i=2,3,4,5)
Thus one complete transition from state through the state
diagram and back to constitutes a complete m/c cycle the partial
state transition diagram is shown below assuming READY=1 is no
wait.
 The shaded portion above that these state may be neede in
same instructions. Instruction cycles for various 8085A instruction
required to execute an instruction will depend on the READY & HOLD
signal inputs.
For example consider the 3 byte instruction STA ADDR, STA stands
for store accumulator direct the meaning of the instruction is transfer
the content of the accumulator to an external memory location whose
address is specified in the instruction is ADDR since. The location
can be anywhere in the 64k memory space that the 8085A can
directly address, 16k are required for the address thus the STA
instruction contain 8bytes; a 1 byte op-code and 2-byte address. The
instruction is stored in the memory as follows.

OP CODE BYTE 1

LOWER ADDR 2

HIGHER ADDR 3
Three m/c cycles are required o fetch this
instruction. In MC-1 is op code fetch M/C ,the opcode is transferred
from memory to the instruction register during states and then
during state it is interpreted , at this point the cpu knows that it
must do more m/c cycles two RMC to fetch the complete instruction
in MC-2 the lower addresses transferred from the memory to the
temporary register Z. in MC-3 the third byte i.e. the higher address is
transferred from the memory to the temporary register W. when the
entire instruction is in the it is executed. Execution means a data
transfer from the to memory. The contents of the accumulators
are transferred to the memory location, whose address was
previously transferred to the by the proceeding two memory read
m/c cycles the address of the memory location to be written is
generated as follows the high order address byte is temp reg. W is
transferred to the address latch and the low order address byte in Z
reg. is transferred to address/data latch. The content of the A is then
placed on the data bus. This data transfer is affected by a MWRMC
thus 3 byte STA instruction has four m/c cycles in its instruction
cycles.
Mnemonic Instruction byte
STA op code OP CODE
FETCH
LO addr MRMC
Hi addr MRMC
MWRMC
 This STA has a total of 13 states. If the 8085A is operating at
325.5ns time, the STA instruction cycle is executed in 4.23 . This
time period is the instruction execution time, although it actually
includes both the instruction fetch and the execution time.
Lecture-15
MACHINE CYCLES

OPCODE FETCH machine cycle:

Fig. shows the 8085 instruction fetch timing diagram. The
instruction fetch cycle requires either four or six clock periods (T
states). The other m/c cycles that follow OFMC will need three clock
cycles.
The purpose of an OF is to read the contents of a memory
location containing the opcode addressed by the program counter
and to place it in the instruction register.
In the beginning of state , the 8085A puts a low on the
IO/ line of the system bus indicating a memory operation the 8085
sets on the system bus, indicating the memory
fetch operation this status information remains constant for the
duration of the m/c cycle. During state, the 16 bit address
of the memory location containing the op code is obtained
from the program counter pc and placed in the address and address
data latches the higher order 8 bits of the address appears on the
address bus remains constants until the end of the state
during state the data on the address bus is unspecified. The low
order 8 bits of the address is placed on the address/data bus,
at the beginning of this data however remains valid
only until the beginning of state at which time the addr/data bus is
floated (3 states) because this is time multiplexed bus and used on
the data bus during state. Therefore addr latch enable
(ALE) signal issued by the during is used to latch this lower
order addr in same external hardware 8212 on its falling edge the 16
bit addr select a particular memory location.
During state , at the beginning. The single goes low
indicating readf operation and the opcode to be fetched is placed on
the data bus, , by the addressed memory location. The
contents of (pc) is incremented be 1 during this state as during
state the pc has sent the addr to addr bus . the access memory
should be fast enough to output its data before goes high slower
memories can gain more time by pulling the READY signal of 8085
LOW this will introduce an integral no. of sate between
as long as READY is low on the ring edge of the
control signal in , the opcode obtaining from memory is
transferred to the micro process instruction register.
During data , the 8085 decodes the instruction and
determines whether to enter state or to enter state of the
next m/c cycle from the operation code the determines what other
m/c cycles if any must be execute to complete the instruction cycle
state when entered, are used for internal operations
necessitated by the instruction.
 The micro RTL flow for 4 data OFMC is shown below.
OFMC: status IO/ =0,

(PCL) , (PCH), ALE=

: (PC)+1, M(AB)
: , (IR)
: decodes the opcode and decides whether
states are required or next m/c cycle is executed. During T4 T6
states,
Fig below shows the timing diagram for a 6-state OFMC

Note: whenever the addr information is sent from the program

counter to the external world during state, then the pc is
incremented by 1 during the subsequent state so that pc points to
the next subsequent byte. However if the addr information from pc
has not been sent out during the state to the external until then pc
will not be incremented during state.

Memory READ m/c cycle:

It requires 3 states to the purpose of the memory
READ operation is to read the contents of a memory location
addressed by a and place the data in a register by a register pair,
the source of address issued during is not always the program
counter but may be any one of the several other register pairs in
the depending on the particular instruction of which the m/c cycle
is a part.
The 8085 uses m/c cycle MC1 to fetch and decode the instruction.
It then performs the memory read operation in MC2. E.g. in LXIH,
Addr.
The IO/ signal made low to indicate the external world that a
memory reference is required. Then made
indicating that memory READ operation is to be performed. During
the 8085 places the contents of high byte of the memory address
register, such as that contents of the (PCH) or (H) register on
lines and the contents of the low byte of the memory
address register such as contents of the (PCL) or (L) reg. On
lines . The 8085 sets ALE to HIGH, indicating the
beginning of MC-2 AS soon as ALE goes to low, the 8085 latches the
low byte of the address lines, since the same lines as going to be
used as data lines.
During state, the signal goes LOW indicating a READ
operation. If the addr sent and during state is from pc, then pc is
incremented by 1 otherwise not the external logic gets the data from
the memory location addressed by the memory address register such
as (H,L) pair and places the data on to data bus .
During state, signal goes high, this low to high signal
transfer the data from the data bus to internal register such as the
accumulator.
MRMC: status signals IO/ =0,
(PCL) , (PCH), ALE=
: (PC)+1, M(AB)
: , , (internal reg.)
Or
(PCL) , (PCH), ALE=
: M(AB)
: , , (internal reg.)
MEMORY WRITE MC:
It also requires only states the purpose of memory
write is to store the contents of any of the 8085 reg. such as the
accumulator into a memory location addressed by a register pair such
as HL.
The 8085 made IO/ =0 in the beginning of state to
indicate memory reference operation then it puts ,
indicates a memory write operation.
During state 8085 places the memory address register
high byte such as the contents of the H register on lines
and also places the MAR low byte such as the contents of the L-
register on lines . the 8085sets ALE to HIGH, indicating
the beginning of MWRMC. As soon as ALE goes to low, the 8085
latches the low byte of the address lines since the same lines are
going to be used as data lines. During state, goes low
indicating memory write operation It also places the contents of the
internal register say accumulator on data lines .
During state, goes high this low to high transition is
used to transfer the data from the data lines to the memory location
address by MAR such as HL reg. pair.
MWRMC: IO/ =0,
(L), (H), ALE=
: ( internal register)
: , M(AB)
I/O READ and I/O WRITE M/C cycle:
These are identical to MRMC & MWRMC respectively except
that appropriate status signals are issued at the beginning of
state. IO/ signal goes high at the beginning to indicate I/O device
reference is needed in case of I/O mapped input/output device in
these m/c cycles higher & lower address bytes are identical and
equal to the 8 bit address of the I/O port while in case of MRMC or
MWRMC, the address bus output is the true 16bits address.