SEMICONDUCTOR TECHNICAL DATA

 
  !

 !
 ! J SUFFIX
CERAMIC PACKAGE
20
High–Performance Silicon–Gate CMOS 1
CASE 732–03

The MC54/74HC244A is identical in pinout to the LS244. The device

inputs are compatible with standard CMOS outputs; with pullup resistors, N SUFFIX
they are compatible with LSTTL outputs. PLASTIC PACKAGE
20 CASE 738–03
This octal noninverting buffer/line driver/line receiver is designed to be
1
used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. The device has noninverting outputs and two DW SUFFIX
20 SOIC PACKAGE
active–low output enables. 1
The HC244A is similar in function to the HC240A and HC241A. CASE 751D–04

• Output Drive Capability: 15 LSTTL Loads SD SUFFIX

20 SSOP PACKAGE
• Outputs Directly Interface to CMOS, NMOS, and TTL 1 CASE 940C–03
• Operating Voltage Range: 2 to 6 V
DT SUFFIX
• Low Input Current: 1 µA 20 TSSOP PACKAGE
• High Noise Immunity Characteristic of CMOS Devices 1 CASE 948E–02
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A ORDERING INFORMATION
• Chip Complexity: 136 FETs or 34 Equivalent Gates MC54HCXXXAJ Ceramic
MC74HCXXXAN Plastic
MC74HCXXXADW SOIC
MC74HCXXXASD SSOP
MC74HCXXXADT TSSOP
LOGIC DIAGRAM

2 18 PIN ASSIGNMENT
A1 YA1

4 16 ENABLE A 1 20 VCC
A2 YA2
A1 2 19 ENABLE B
6 14 YB4 3 18 YA1
A3 YA3
A2 4 17 B4
8 12
A4 YA4 YB3 5 16 YA2
DATA NONINVERTING
INPUTS 11 9 OUTPUTS A3 6 15 B3
B1 YB1
YB2 7 14 YA3
13 7 A4 8 13 B2
B2 YB2
YB1 9 12 YA4
15 5
B3 YB3 GND 10 11 B1

17 3
B4 YB4

FUNCTION TABLE
PIN 20 = VCC Inputs Outputs
1 PIN 10 = GND
OUTPUT ENABLE A Enable A,
ENABLES 19 Enable B A, B YA, YB
ENABLE B
L L L
L H H
H X Z

Z = high impedance

2/97

 Motorola, Inc. 1997 1 REV 7

MC54/74HC244A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol

ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Parameter
DC Supply Voltage (Referenced to GND)
Value
– 0.5 to + 7.0
Unit
V
This device contains protection
circuitry to guard against damage

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout

ÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin
ÎÎÎ
DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ
ÎÎÎ
DC Input Current, per Pin
– 0.5 to VCC + 0.5
± 20
V
mA
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 35 mA

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 75 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
SSOP or TSSOP Package† 450
Unused outputs must be left open.

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
Tstg Storage Temperature – 65 to + 150 _C

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C
(Plastic DIP, SOIC, SSOP or TSSOP Package) 260

ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎ
(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎ
ÎÎÎ Parameter Min Max Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC

ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout
ÎÎÎ ÎÎÎ
ÎÎÎ
DC Supply Voltage (Referenced to GND)

ÎÎÎ
ÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND)
2.0
0
6.0
VCC
V
V

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf
ÎÎÎ ÎÎÎ
ÎÎÎ
Operating Temperature, All Package Types

ÎÎÎ
ÎÎÎ
Input Rise and Fall Time VCC = 2.0 V
– 55
0
+ 125
1000
_C
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ VCC – 55 to
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VIH Minimum High–Level Input Vout = VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v Voltage |Iout| 20 µA 3.0 2.1 2.1 2.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 3.15 3.15 3.15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 4.2 4.2 4.2
VIL Maximum Low–Level Input Vout = 0.1 V 2.0 0.5 0.5 0.5 V
v
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
Voltage
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ |Iout| 20 µA 3.0 0.9 0.9 0.9

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 1.35 1.35 1.35
6.0 1.8 1.8 1.8

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOH

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Minimum High–Level Output

ÎÎÎÎÎÎÎÎÎ ÎÎÎ
Vin = VIH 2.0 1.9 1.9 1.9 V

v ÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 5.9 5.9 5.9
Vin = VIH |Iout| 2.4 mA 3.0 2.48 2.34 2.2

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ |Iout| 6.0 mA 4.5 3.98 3.84 3.7

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 7.8 mA 6.0 5.48 5.34 5.2

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC244A

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ ÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Symbol ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
v
ÎÎÎÎÎÎÎÎ
v ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Parameter Test Conditions
VCC
V
– 55 to
25_C 85_C 125_C Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VOL Maximum Low–Level Output Vin = VIL 2.0 0.1 0.1 0.1 V
v
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 0.1 0.1 0.1

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Vin = VIL |Iout| 2.4 mA 3.0 0.26 0.33 0.4
v
ÎÎÎÎ Î
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
|Iout| 6.0 mA 4.5 0.26 0.33 0.4
|Iout| 7.8 mA 6.0 0.26 0.33 0.4

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Iin
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
IOZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Leakage Current

ÎÎÎÎ
ÎÎÎ
Maximum Three–State Leakage
Vin = VCC or GND
Output in High–Impedance State
6.0
6.0
± 0.1
± 0.5
± 1.0
± 5.0
± 1.0
± 10
µA
µA

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Current Vin = VIL or VIH
Vout = VCC or GND

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Quiescent Supply

ÎÎÎÎ
ÎÎÎ
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 4.0 40 160 µA

NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
VCC – 55 to
v v 25_C 85_C 125_C

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
S b l
Symbol P
Parameter V U i
Unit

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPLH, Maximum Propagation Delay, A to YA or B to YB 2.0 96 115 135 ns
tPHL (Figures 1 and 3) 3.0 50 60 70

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 18 23 27

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
6.0 15 20 23

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
tPLZ, Maximum Propagation Delay, Output Enable to YA or YB 2.0 110 140 165 ns
tPHZ (Figures 2 and 4) 3.0 60 70 80

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tPZL,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPZH ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Propagation Delay, Output Enable to YA or YB

ÎÎÎÎ
(Figures 2 and 4)
ÎÎÎ
2.0
3.0
110
60
140
70
165
80
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 22 28 33
6.0 19 24 28

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
tTLH,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL ÎÎÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Output Transition Time, Any Output

ÎÎÎÎ
(Figures 1 and 3)
ÎÎÎ
2.0
3.0
60
23
75
27
90
32
ns

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
4.5 12 15 18
6.0 10 13 15

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cout
ÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
Maximum Input Capacitance

ÎÎÎÎ
ÎÎÎ
Maximum Three–State Output Capacitance (Output in
—
—
10
15
10
15
10
15
pF
pF

ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
High–Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD P
Power Di i i C
Dissipation i
Capacitance (P
(Per B ff )*
Buffer)* 34 F
pF
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
MC54/74HC244A

SWITCHING WAVEFORMS

tr tf VCC
DATA INPUT VCC ENABLE 50%
90%
A OR B 50% A OR B GND
10% GND tPZL tPLZ
tPLH tPHL HIGH
OUTPUT 90% 50% IMPEDANCE
50% OUTPUT Y
YA OR YB 10% VOL
10% tPZH tPHZ
tTLH tTHL 90% VOH
OUTPUT Y 50%
HIGH
IMPEDANCE

Figure 1. Figure 2.

TEST CIRCUITS

TEST POINT TEST POINT

CONNECT TO VCC WHEN
OUTPUT OUTPUT 1 kΩ
TESTING tPLZ AND tPZL.
DEVICE DEVICE CONNECT TO GND WHEN
UNDER UNDER TESTING tPHZ AND tPZH.
TEST CL* TEST CL*

* Includes all probe and jig capacitance * Includes all probe and jig capacitance

Figure 3. Test Circuit Figure 4. Test Circuit

PIN DESCRIPTIONS

INPUTS to these pins, the outputs are enabled and the devices func-
tion as noninverting buffers. When a high level is applied, the
A1, A2, A3, A4, B1, B2, B3, B4 outputs assume the high impedance state.
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
Data input pins. Data on these pins appear in noninverted OUTPUTS
form on the corresponding Y outputs, when the outputs are
enabled. YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
CONTROLS
Device outputs. Depending upon the state of the output–
Enable A, Enable B (Pins 1, 19) enable pins, these outputs are either noninverting outputs or
Output enables (active–low). When a low level is applied high–impedance outputs.

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC244A

LOGIC DETAIL

TO THREE OTHER
A OR B INVERTERS

ONE OF 8
INVERTERS

VCC
DATA
INPUT
A OR B
YA
OR
YB

ENABLE A OR
ENABLE B

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HC244A

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC PACKAGE NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
20 11 CASE 732–03 POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
ISSUE E 2. DIMENSION L TO CENTER OF LEADS WHEN
1 10
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
MILLIMETERS INCHES
A DIM MIN MAX MIN MAX
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C L C 3.81 5.08 0.150 0.200
F D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
N J 0.20 0.30 0.008 0.012
J K 3.18 4.06 0.125 0.160
H K L 7.62 BSC 0.300 BSC
D G M M 0_ 15 _ 0_ 15_
N 0.25 1.02 0.010 0.040
SEATING
PLANE

N SUFFIX
–A– PLASTIC PACKAGE
CASE 738–03 NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
20 11 ISSUE E Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
B 3. DIMENSION L TO CENTER OF LEAD WHEN
1 10 FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
C L
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 1.010 1.070 25.66 27.17
B 0.240 0.260 6.10 6.60
–T– C 0.150 0.180 3.81 4.57
K D 0.015 0.022 0.39 0.55
SEATING
PLANE M E 0.050 BSC 1.27 BSC
F 0.050 0.070 1.27 1.77
E N G 0.100 BSC 2.54 BSC
J 0.008 0.015 0.21 0.38
G F K 0.110 0.140 2.80 3.55
J 20 PL
L 0.300 BSC 7.62 BSC
D 20 PL 0.25 (0.010) M T B M M 0_ 15 _ 0_ 15_
0.25 (0.010) M T A M N 0.020 0.040 0.51 1.01

DW SUFFIX
–A– PLASTIC SOIC PACKAGE NOTES:
1. DIMENSIONING AND TOLERANCING PER
CASE 751D–04 ANSI Y14.5M, 1982.
20 11 ISSUE E 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
–B– 10X P (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
0.010 (0.25) M B M
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
1 10 (0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

20X D MILLIMETERS INCHES

J DIM MIN MAX MIN MAX
0.010 (0.25) M T A S B S A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
F D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
R X 45 _ J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
C R 0.25 0.75 0.010 0.029

–T– SEATING
PLANE
18X G M
K

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC244A

OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
NOTES:
ISSUE B 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20X K REF 2. CONTROLLING DIMENSION: MILLIMETER.
0.25 (0.010) 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
0.12 (0.005) M T U S V S PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
N GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
L/2 20 11 M FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
N SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
L B F PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
DETAIL E EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
PIN 1 1 10 CONDITION. DAMBAR INTRUSION SHALL NOT
IDENT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.

ÉÉÉ
ÇÇÇ
K 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
–U–

ÇÇÇ
ÉÉÉ
A 7. DIMENSION A AND B ARE TO BE DETERMINED AT
–V– J J1 DATUM PLANE –W–.
MILLIMETERS INCHES
0.20 (0.008) M T U S K1 DIM MIN MAX MIN MAX
A 7.07 7.33 0.278 0.288
B 5.20 5.38 0.205 0.212
SECTION N–N C 1.73 1.99 0.068 0.078
D 0.05 0.21 0.002 0.008
F 0.63 0.95 0.024 0.037
–W– G 0.65 BSC 0.026 BSC
C H 0.59 0.75 0.023 0.030
0.076 (0.003)
J 0.09 0.20 0.003 0.008
–T– SEATING J1 0.09 0.16 0.003 0.006
PLANE D G DETAIL E
K 0.25 0.38 0.010 0.015
K1 0.25 0.33 0.010 0.013
H L 7.65 7.90 0.301 0.311
M 0_ 8_ 0_ 8_

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
20X K REF ISSUE A NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
0.15 (0.006) T U S 0.10 (0.004) M T U S V S Y14.5M, 1982.

ÍÍÍÍ
2. CONTROLLING DIMENSION: MILLIMETER.
K 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

ÍÍÍÍ
K1 PROTRUSIONS OR GATE BURRS. MOLD FLASH
20 11 OR GATE BURRS SHALL NOT EXCEED 0.15
2X L/2 (0.006) PER SIDE.

ÍÍÍÍ
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
B J J1 FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
L –U– PER SIDE.
PIN 1 5. DIMENSION K DOES NOT INCLUDE DAMBAR
IDENT SECTION N–N PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
1 10 EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
N 0.25 (0.010) 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
0.15 (0.006) T U S 7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
A M
MILLIMETERS INCHES
–V– DIM MIN MAX MIN MAX
A 6.40 6.60 0.252 0.260
N B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
F D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
DETAIL E G 0.65 BSC 0.026 BSC
H 0.27 0.37 0.011 0.015
J 0.09 0.20 0.004 0.008
–W– J1 0.09 0.16 0.004 0.006
C K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC 0.252 BSC
G
D H M 0_ 8_ 0_ 8_
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE

High–Speed CMOS Logic Data 7 MOTOROLA

DL129 — Rev 6
MC54/74HC244A

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◊ MC74HC244A/D
MOTOROLA 8 High–Speed CMOS Logic Data
DL129 — Rev 6