Word-Wide Flashfile™ Memory Family 28F160S5, 28F320S5: Advance Information

E WORD-WIDE
FlashFile MEMORY FAMILY

ADVANCE INFORMATION
28F160S5, 28F320S5
Includes Extended Temperature Specifications
n Two 32-Byte Write Buffers n Cross-Compatible Command Support

2 s per Byte Effective Intel Standard Command Set
Programming Time Common Flash Interface (CFI)
n Operating Voltage Scaleable Command Set (SCS)
5V VCC n 100,000 Block Erase Cycles
5V VPP n Enhanced Data Protection Features
n 70 ns Read Access Time (16 Mbit) Absolute Protection with V PP = GND
90 ns Read Access Time (32 Mbit) Flexible Block Locking
n High-Density Symmetrically-Blocked Block Erase/Program Lockout
Architecture during Power Transitions
32 64-Kbyte Erase Blocks (16 Mbit) n Configurable x8 or x16 I/O
64 64-Kbyte Erase Blocks (32 Mbit) n Automation Suspend Options
n System Performance Enhancements Program Suspend to Read
STS Status Output Block Erase Suspend to Program
n Industry-Standard Packaging Block Erase Suspend to Read
SSOP and TSOP (16 Mbit) n ETOX V Nonvolatile Flash
SSOP (32 Mbit) Technology
Intels Word-Wide FlashFile memory family provides high-density, low-cost, nonvolatile, read/write storage
solutions for a wide range of applications. The word-wide memories are available at various densities in the
same package type. Their symmetrically-blocked architecture, voltage, and extended cycling provide highly
flexible components suitable for resident flash arrays, SIMMs, and memory cards. Enhanced suspend
capabilities provide an ideal solution for code or data storage applications. For secure code storage
applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM,
the word-wide memories offer three levels of protection: absolute protection with VPP at GND, selective block
locking, and program/erase lockout during power transitions. These alternatives give designers ultimate
control of their code security needs.
This family of products is manufactured on Intels 0.4 m ETOX V process technology. It comes in the
industry-standard 56-lead SSOP. In addition, the 16-Mb device is available in the industry-standard 56-lead
TSOP package.
June 1997 Order Number: 290609-001
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F160S5 and 28F320S5 may contain design defects or errors known as errata. Current characterized errata are available
on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intels website at http:\\www.intel.com
COPYRIGHT INTEL CORPORATION, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.

E CONTENTS
28F160S5, 28F320S5
PAGE PAGE
4.8 Write to Buffer Command ...........................26
1.0 INTRODUCTION .............................................5
4.9 Byte/Word Write Command ........................26
1.1 New Features...............................................5
4.10 STS Configuration Command...................27
1.2 Product Overview.........................................5
4.11 Block Erase Suspend Command ..............27
1.3 Pinout and Pin Description ...........................6
4.12 Program Suspend Command ...................27
2.0 PRINCIPLES OF OPERATION .......................9 4.13 Set Block Lock-Bit Commands .................28
2.1 Data Protection ..........................................10 4.14 Clear Block Lock-Bits Command ..............28
3.0 BUS OPERATION .........................................11 5.0 DESIGN CONSIDERATIONS ........................38

3.1 Read ..........................................................11 5.1 Three-Line Output Control..........................38
3.2 Output Disable ...........................................11 5.2. STS and WSM Polling ...............................38
3.3 Standby......................................................11 5.3 Power Supply Decoupling ..........................38
3.4 Deep Power-Down .....................................11 5.4 VPP Trace on Printed Circuit Boards...........38
3.5 Read Query Operation ...............................11 5.5 VCC, VPP, RP# Transitions..........................38
3.6 Read Identifier Codes Operation ................12 5.6 Power-Up/Down Protection ........................38
3.7 Write ..........................................................12
6.0 ELECTRICAL SPECIFICATIONS..................39
4.0 COMMAND DEFINITIONS ............................12 6.1 Absolute Maximum Ratings ........................39
4.1 Read Array Command................................16 6.2 Operating Conditions..................................39
4.2 Read Query Mode Command.....................16 6.2.1 Capacitance.........................................40
4.2.1 Query Structure Output .......................16 6.2.2 AC Input/Output Test Conditions .........40
4.2.2 Query Structure Overview ...................18 6.2.3 DC Characteristics...............................41
4.2.3 Block Status Register ..........................19 6.2.4 AC Characteristics - Read-Only
4.2.4 CFI Query Identification String.............20 Operations..........................................43
4.2.5 System Interface Information..............21 6.2.5 AC Characteristics - Write Operations .45
4.2.6 Device Geometry Definition .................22 6.2.6 Reset Operations.................................47
4.2.7 Intel-Specific Extended Query Table ...23 6.2.7 Erase, Program, and Lock-Bit
Configuration Performance.................48
4.3 Read Identifier Codes Command ...............24
4.4 Read Status Register Command................24 APPENDIX A: Device Nomenclature and
4.5 Clear Status Register Command................25 Ordering Information ..................................49
4.6 Block Erase Command ..............................25 APPENDIX B: Additional Information ...............50
4.7 Full Chip Erase Command .........................25
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ADVANCE INFORMATION

28F160S5, 28F320S5 E
REVISION HISTORY
Number Description
-001 Original version
4
ADVANCE INFORMATION

E
1.0 INTRODUCTION
28F160S5, 28F320S5
Specifically designed for 5V systems, the

28F160S5 and 28F320S5 support read and write
This datasheet contains Word-Wide FlashFile operation with VCC equal to VPP. Coupled with this
memory (28F160S5, 28F320S5) specifications. capability, high programming performance is
Section 1 provides a flash memory overview. achieved through small, highly-optimized write
Sections 2, 3, 4, and 5 describe the memory buffer operations. Additionally, the dedicated VPP
organization and functionality. Section 6 covers pin gives complete data protection when VPP
electrical specifications for extended temperature VPPLK.
product offerings.
A Common Flash Interface (CFI) permits OEM-
specified software algorithms to be used for entire
1.1 New Features families of devices. This allows device-independent,
JEDEC ID-independent, and forward- and
The Word-Wide FlashFile memory family maintains backward-compatible software support for the
basic compatibility with Intels 28F016SA and specified flash device families. Flash vendors can
28F016SV. Key enhancements include: standardize their existing interfaces for long-term
compatibility.
Common Flash Interface (CFI) Support
Scaleable Command Set (SCS) allows a single,
Scaleable Command Set (SCS) Support simple software driver in all host systems to work
S5 Technology with all SCS-compliant flash memory devices,
independent of system-level packaging (e.g.,
Enhanced Suspend Capabilities memory card, SIMM, or direct-to-board placement).
Additionally, SCS provides the highest
They share a compatible Status Register, basic system/device data transfer rates and minimizes
software commands, and pinout. These similarities device and system-level implementation costs.
enable a clean migration from the 28F016SA or
28F016SV. When upgrading, it is important to note A Command User Interface (CUI) serves as the
the following differences: interface between the system processor and
internal device operation. A valid command
Because of new feature and density options, sequence written to the CUI initiates device
the devices have different device identifier automation. An internal Write State Machine (WSM)
codes. This allows for software optimization. automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
New software commands. configuration operations.
To take advantage of the 5V technology on the
28F160S5 and 28F320S5, allow VPP A block erase operation erases one of the devices
connection to VCC. The 28F160S5 and 64-Kbyte blocks typically within tWHQV2/EHQV2
independent of other blocks. Each block can be
28F320S5 FlashFile memories do not support a
independently erased 100,000 times. Block erase
12V VPP option. suspend allows system software to suspend block
erase to read or write data from any other block.
1.2 Product Overview Data is programmed in byte, word or page
increments. Program suspend mode enables the
The Word-Wide FlashFile memory family provides system to read data or execute code from any other
density upgrades with pinout compatibility for the flash memory array location.
16- and 32-Mbit densities. They are high-
performance memories arranged as 1 Mword and The device incorporates two Write Buffers of 32
2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of bytes (16 words) to allow optimum-performance
8 bits. This data is grouped in thirty-two and sixty- data programming. This feature can improve
four 64-Kbyte blocks that can be erased, locked, system program performance by up to eight times
and unlocked in-system. Figure 1 shows the block over non-buffer programming.
diagram, and Figure 4 illustrates the memory
organization.
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ADVANCE INFORMATION

28F160S5, 28F320S5
Individual block locking uses a combination of block The BYTE# pin allows either x8 or x16 read/writes
E
lock-bits to lock and unlock blocks. Block lock-bits to the device. BYTE# at logic low selects 8-bit
gate block erase, full chip erase, program and write mode with address A0 selecting between the low
to buffer operations. Lock-bit configuration byte and high byte. BYTE# at logic high enables
operations (Set Block Lock-Bit and Clear Block 16-bit operation with address A1 becoming the
Lock-Bits commands) set and clear lock-bits. lowest order address. Address A0 is not used in 16-
bit mode.
The Status Register and the STS pin in RY/BY#
mode indicate whether or not the device is busy When one of the CEX# pins (CE0#, CE1#) and RP#
executing an operation or ready for a new pins are at VCC, the component enters a CMOS
command. Polling the Status Register, system standby mode. Driving RP# to GND enables a deep
software retrieves WSM feedback. STS in RY/BY# power-down mode which significantly reduces
mode gives an additional indicator of WSM activity power consumption, provides write protection,
by providing a hardware status signal. Like the resets the device, and clears the Status Register. A
Status Register, RY/BY#-low indicates that the reset time (tPHQV) is required from RP# switching
WSM is performing a block erase, program, or lock- high until outputs are valid. Likewise, the device
bit operation. RY/BY#-high indicates that the WSM has a wake time (tPHEL) from RP#-high until writes
is ready for a new command, block erase is to the CUI are recognized.
suspended (and program is inactive), program is
suspended, or the device is in deep power-down
mode. 1.3 Pinout and Pin Description
The Automatic Power Savings (APS) feature The 16-Mbit device is available in the 56-lead
substantially reduces active current when the TSOP and 56-lead SSOP. The 32- Mb device is
device is in static mode (addresses not switching). available in the 56-lead SSOP. The pinouts are
shown in Figures 2 and 3.
DQ0 - DQ15
Output Buffer Input Buffer
Query VCC
I/O Logic
BYTE#
Multiplexer
Write Buffer
Register
CE#
Output
Identifier
Command
Data
Register WE#
User
OE#
Interface
RP#
Status
WP#
Register
Multiplexer
Data
Comparator
16-Mbit: A0- A20 Y-Decoder Y-Gating STS

Input Buffer Write State
32-Mbit: A0 - A21
Program/Erase VPP
Machine
Voltage Switch
Address 16-Mbit: Thirty-two
Latch X-Decoder 32-Mbit: Sixty-four VCC
64-Kbyte Blocks GND
Address
Counter
0608_01
Figure 1. 28F320S5 and 28F160S5 Block Diagram
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ADVANCE INFORMATION

E Table 1. Pin Descriptions
28F160S5, 28F320S5
Sym Type Name and Function

A0A21 INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally
latched during a write cycle. A 0 selects high or low byte when operating in x8 mode.
In x16 mode, A0 is not used; input buffer is off.
16-Mbit A0A20 32-Mbit A0A21
DQ0 INPUT/ DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles;
DQ15 OUTPUT outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CE0#, INPUT CHIP ENABLE: Activates the devices control logic, input buffers, decoders, and
CE1# sense amplifiers. With CE 0# or CE1# high, the device is deselected and power
consumption reduces to standby levels. Both CE 0# and CE1# must be low to select
the device. Device selection occurs with the latter falling edge of CE 0# or CE1#. The
first rising edge of CE0# or CE1# disables the device.
RP# INPUT RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
OE# INPUT OUTPUT ENABLE: Gates the devices outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
STS OPEN STATUS: Indicates the status of the internal state machine. When configured in
DRAIN level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
OUTPUT of the STATUS pin, see the Configuration command. Tie STS to VCC with a pull-up
resistor.
WP# INPUT WRITE PROTECT: Master control for block locking. When V IL, locked blocks
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
BYTE# INPUT BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
VPP SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
VCC SUPPLY DEVICE POWER SUPPLY: Do not float any power pins.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
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28F160S5, 28F320S5 E
28F016SA 28F160S3 28F160S3 28F016SA
28F016SV 28F160S5 28F160S5 28F016SV
3/5# NC 1 56 WP# WP#

CE1# CE1# 2 55 WE# WE#
NC NC 3 54 OE# OE#
A20 A20 4 53 STS RY/BY#
RY/BY#
A19 A19 5 52 DQ15 DQ15
A18 A18 6 51 DQ7 DQ7
A17 A17 7 50 DQ14 DQ14
A16 A16 8 49 DQ6 DQ6
VCC VCC 9 48 GND GND
A15 A15 10 56-LEAD TSOP 47 DQ13 DQ13
A14 A14 11 STANDARD PINOUT 46 DQ5 DQ5
A13 A13 12 45 DQ12 DQ12
A12 A12 13 44 DQ4 DQ4
CE0# CE0# 14 mm x 20 mm VCC VCC
14 43
VPP VPP 15 TOP VIEW 42 GND GND
RP# RP# 16 41 DQ11 DQ11
A11 A11 17 40 DQ3 DQ3
A10 A10 18 39 DQ10 DQ10
A9 A9 19 38 DQ2 DQ2
A8 A8 20 37 VCC VCC
GND GND 21 36 DQ9 DQ9
A7 A7 22 35 DQ1 DQ1
A6 A6 23 34 DQ8 DQ8
A5 A5 24 33 DQ0 DQ0
A4 A4 25 32 A0 A0
A3 A3 26 31 BYTE# BYTE#
A2 A2 27 30 NC NC
A1 A1 28 29 NC NC
Highlights pinout changes.

0608_02
Figure 2. 28F160S5 TSOP 56-Lead Pinout
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ADVANCE INFORMATION

E 28F160S5, 28F320S5
Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout
2.0 PRINCIPLES OF OPERATION After initial device power-up or return from deep
power-down mode (see Bus Operations), the
The Word-Wide FlashFile memories include an device defaults to read array mode. Manipulation
on-chip Write State Machine (WSM) to manage of external memory control pins allow array read,
block erase, program, and lock-bit configuration standby, and output disable operations.
functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure,
programming, lock-bit configuration, and minimal
processor overhead with RAM-like interface
timings.
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ADVANCE INFORMATION

28F160S5, 28F320S5
Read Array, Status Register, query, and identifier

E
via the Read Array command. Block erase
codes can be accessed through the CUI suspend allows system software to suspend a
independent of the VPP voltage. Proper block erase to read or write data from any other
programming voltage on VPP enables successful block. Program suspend allows system software
block erasure, program, and lock-bit to suspend a program to read data from any
configuration. All functions associated with other flash memory array location.
altering memory contentsblock erase, program,
lock-bit configuration, status, and identifier
codesare accessed via the CUI and verified 2.1 Data Protection
through the Status Register.
Depending on the application, the system
Commands are written using standard micro- designer may choose to make the VPP power
processor write timings. The CUI contents serve supply switchable or hardwired to VPPH. The
as input to the WSM that controls the block device supports either design practice, and
erase, programming, and lock-bit configuration. encourages optimization of the processor-
The internal algorithms are regulated by the memory interface.
WSM, including pulse repetition, internal
verification, and margining of data. Addresses When VPP VPPLK, memory contents cannot be
and data are internally latched during write altered. When high voltage is applied to VPP, the
cycles. Writing the appropriate command outputs two-step block erase, program, or lock-bit
array data, identifier codes, or Status Register configuration command sequences provide
data. protection from unwanted operations. All write
functions are disabled when VCC voltage is below
Interface software that initiates and polls the write lockout voltage VLKO or when RP# is at
progress of block erase, programming, and lock- VIL. The devices block locking capability
bit configuration can be stored in any block. This provides additional protection from inadvertent
code is copied to and executed from system code or data alteration.
RAM during flash memory updates. After
successful completion, reads are again possible
0608_05
Figure 4. Memory Map
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ADVANCE INFORMATION

E
3.0 BUS OPERATION 3.4 Deep Power-Down
28F160S5, 28F320S5
The local CPU reads and writes flash memory in- RP# at VIL initiates the deep power-down mode.
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus In read mode, RP#-low deselects the memory,
cycles. places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time tPLPH. Time tPHQV is required
3.1 Read after return from power-down until initial memory
access outputs are valid. After this wake-up
Block information, query information, identifier interval, normal operation is restored. The CUI
codes and Status Registers can be read resets to read array mode, and the Status
independent of the VPP voltage. Register is set to 80H.
The first task is to place the device into the During block erase, programming, or lock-bit
desired read mode by writing the appropriate configuration modes, RP#-low will abort the
read-mode command (Read Array, Query, Read operation. STS in RY/BY# mode remains low
Identifier Codes, or Read Status Register) to the until the reset operation is complete. Memory
CUI. Upon initial device power-up or after exit contents being altered are no longer valid; the
from deep power-down mode, the device data may be partially corrupted after
automatically resets to read array mode. Control programming or partially altered after an erase or
pins dictate the data flow in and out of the lock-bit configuration. Time tPHWL is required after
component. CE0#, CE1# and OE# must be driven RP# goes to logic-high (VIH) before another
active to obtain data at the outputs. CE0# and command can be written.
CE1# are the device selection controls, and,
when both are active, enable the selected It is important in any automated system to assert
memory device. OE# is the data output (DQ0 RP# during system reset. When the system
DQ15) control: When active it drives the selected comes out of reset, it expects to read from the
memory data onto the I/O bus. WE# must be at flash memory. Automated flash memories
VIH and RP# must be at VIH. Figure 16 illustrates provide status information when accessed during
a read cycle. block erase, programming, or lock-bit
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
3.2 Output Disable may not occur because the flash memory may be
providing status information instead of array data.
With OE# at a logic-high level (VIH), the device Intels Flash memories allow proper CPU
outputs are disabled. Output pins DQ0DQ15 are initialization following a system reset through the
placed in a high-impedance state. use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.3 Standby
CE0# or CE1# at a logic-high level (VIH) places 3.5 Read Query Operation
the device in standby mode, substantially
reducing device power consumption. DQ0DQ15 The read query operation outputs block status,
(or DQ0 DQ7 in x8 mode) outputs are placed in Common Flash Interface (CFI) ID string, system
a high-impedance state independent of OE#. If interface, device geometry, and Intel-specific
deselected during block erase, programming, or extended query information.
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
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28F160S5, 28F320S5
3.6 Read Identifier Codes 3.7 Write

E
Operation
Writing commands to the CUI enables reading of
The read-identifier codes operation outputs the device data, query, identifier codes, inspection
manufacturer code, device code, and block lock and clearing of the Status Register. Additionally,
configuration codes for each block configuration when VPP = VPPH, block erasure, programming,
(see Figure 5). Using the manufacturer and and lock-bit configuration can also be performed.
device codes, the system software can
automatically match the device with its proper The Block Erase command requires appropriate
algorithms. The block-lock configuration codes command data and an address within the block
identify each blocks lock-bit setting. to be erased. The Byte/Word Write command
requires the command and address of the
location to be written. Set Block Lock-Bit
commands require the command and address
within the block to be locked. The Clear Block
Lock-Bits command requires the command and
an address within the device.
The CUI does not occupy an addressable

memory location. It is written when WE#, CE0#,
and CE1# are active and OE# = VIH. The address
and data needed to execute a command are
latched on the rising edge of WE# or CEX#
(CE0#, CE1#), whichever goes high first.
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0 COMMAND DEFINITIONS

VPP voltage VPPLK enables read operations
from the Status Register, identifier codes, or
memory blocks. Placing VPPH on VPP enables
successful block erase, programming, and lock-
bit configuration operations.
Device operations are selected by writing specific

commands into the CUI. Table 2 and Table 3
0608_06
define these commands.
Figure 5. Device Identifier Code Memory Map
12
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E Table 2. Bus Operations
28F160S5, 28F320S5
Mode Notes RP# CE0# CE1# OE#(11) WE#(11) Address VPP DQ(8) STS(3)
Read 1,2 VIH VIL VIL VIL VIH X X DOUT X
Output Disable VIH VIL VIL VIH VIH X X High Z X
Standby VIH VIL VIH X X X X High Z X
VIH VIL
VIH VIH
Reset/Power- 10 VIL X X X X X X High Z High Z(9)
Down Mode
Read Identifier 4 VIH VIL VIL VIL VIH See X DOUT High Z(9)
Codes Figure 5
Read Query 5 VIH VIL VIL VIL VIH See Table 6 X DOUT High Z(9)
Write 3,6,7 VIH VIL VIL VIH VIL X VPPH DIN X
NOTES:
1. Refer to Table 19. When VPP VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPPH for VPP. See Table 19, for VPPLK and VPPH
voltages.
3. STS in RY/BY# mode (default) is VOL when the WSM is executing internal block erase, programming, or lock-bit
configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive),
program suspend mode, or deep power-down mode.
4. See Section 4.3 for read identifier code data.
5. See Section 4.2 for read query data.
6. Command writes involving block erase, write, or lock-bit configuration are reliably executed when VPP = VPPH and
VCC = VCC1/2 (see Section 6.2).
7. Refer to Table 3 for valid DIN during a write operation.
8. DQ refers to DQ07 if BYTE# is low and DQ015 if BYTE# is high.
9. High Z will be VOH with an external pull-up resistor.
10. RP# at GND 0.2V ensures the lowest deep power-down current.
11. OE# = VIL and WE# = VIL concurrently is an undefined state and should not be attempted.
13
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28F160S5, 28F320S5
Table 3. Word-Wide FlashFile Memory Command Set Definitions(13)

E
Command Scaleable Bus Notes First Bus Cycle Second Bus Cycle
or Basic Cycles
Command Req'd
Set(14)
Oper(1) Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4)
Read Array SCS/BCS 1 Write X FFH
Read Identifier Codes SCS/BCS 2 5 Write X 90H Read IA ID
Read Query SCS 2 Write X 98H Read QA QD
Read Status Register SCS/BCS 2 Write X 70H Read X SRD
Clear Status Register SCS/BCS 1 Write X 50H
Write to Buffer SCS >2 8, 9, 10 Write BA E8H Write BA N
Word/Byte Program SCS/BCS 2 6,7 Write X 40H Write PA PD
or
10H
Block Erase SCS/BCS 2 6,10 Write X 20H Write BA D0H
Block Erase, Word/Byte SCS/BCS 1 6 Write X B0H
Program Suspend
Block Erase, Word/Byte SCS/BCS 1 6 Write X D0H
Program Resume
STS pin Configuration SCS 2 Write X B8H Write X CC
Set Block Lock-Bit SCS 2 11 Write X 60H Write BA 01H
Clear Block Lock-Bits SCS 2 12 Write X 60H Write X D0H
Full Chip Erase SCS 2 10 Write X 30H Write X D0H
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E
NOTES:
28F160S5, 28F320S5
1. Bus operations are defined in.Table 2.

2. X = Any valid address within the device.
BA = Address within the block being erased or locked.
IA = Identifier Code Address: see Table 12.
QA = Query database Address.
PA = Address of memory location to be programmed.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from Status Register. See Table 15 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code. (See Table 14.)
4. The upper byte of the data bus (DQ815) during command writes is a Dont Care in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device, and block-lock codes. See
Section 4.3 for read identifier code data.
6. If a block is locked (i.e., the blocks lock-bit is set to 0), WP# must be at VIH in order to perform block erase, program and
suspend operations. Attempts to issue a block erase, program and suspend operation to a locked block while WP# is VIL
will fail.
7. Either 40H or 10H are recognized by the WSM as the byte/word program setup.
8. After the Write to Buffer command is issued, check the XSR to make sure a Write Buffer is available.
9. N = byte/word count argument such that the number of bytes/words to be written to the input buffer = N + 1. N = 0 is 1
byte/word length, and so on. Write to Buffer is a multi-cycle operation, where a byte/word count of N + 1 is written to the
correct memory address (WA) with the proper data (WD). The Confirm command (D0h) is expected after exactly N + 1 write
cycles; any other command at that point in the sequence aborts the buffered write. Writing a byte/word count outside the
buffer boundary causes unexpected results and should be avoided.
10. The write to buffer, block erase, or full chip erase operation does not begin until a Confirm command (D0h) is issued.
Confirm also reactivates suspended operations.
11. A block lock-bit can be set only while WP# is VIH.
12. WP# must be at VIH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits.
13. Commands other than those shown above are reserved for future use and should not be used.
14. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The
Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set.
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28F160S5, 28F320S5 E
4.1 Read Array Command
Query data are always presented on the lowest-
Upon initial device power-up and after exit from order data outputs (DQ0-7) only. The numerical
deep power-down mode, the device defaults to read offset value is the address relative to the maximum
array mode. This operation is also initiated by bus width supported by the device. On this device,
writing the Read Array command. The device the Query table device starting address is a 10h
remains enabled for reads until another command word address, since the maximum bus width is x16.
is written. Once the internal WSM has started block
erase, program, or lock-bit configuration, the device For this word-wide (x16) device, the first two bytes
will not recognize the Read Array command until of the Query structure, Q and R in ASCII, appear
the WSM completes its operationunless the WSM on the low byte at word addresses 10h and 11h.
is suspended via an Erase-Suspend or Program- This CFI-compliant device outputs 00H data on
Suspend command. The Read Array command upper bytes. Thus, the device outputs ASCII Q in
functions independently of the VPP voltage. the low byte (DQ0-7) and 00h in the high byte
(DQ8-15).
4.2 Read Query Mode Command Since the device is x8/x16 capable, the x8 data is
still presented in word-relative (16-bit) addresses.
This section defines the data structure or However, the fill data (00h) is not the same as
database returned by the Common Flash Interface driven by the upper bytes in the x16 mode. As in
(CFI) Query command. System software should x16 mode, the byte address (A0) is ignored for
parse this structure to gain critical information such Query output so that the odd byte address (A0
as block size, density, x8/x16, and electrical high) repeats the even byte address data (A0 low).
specifications. Once this information has been Therefore, in x8 mode using byte addressing, the
obtained, the software will know which command device will output the sequence Q, Q, R, R,
sets to use to enable flash writes, block erases, and Y, Y, and so on, beginning at byte-relative
otherwise control the flash component. The Query address 20h (which is equivalent to word offset 10h
is part of an overall specification for multiple in x16 mode).
command set and control interface descriptions
called Common Flash Interface, or CFI. At Query addresses containing two or more bytes
of information, the least significant data byte is
presented at the lower address, and the most
4.2.1 QUERY STRUCTURE OUTPUT significant data byte is presented at the higher
address.
The Query database allows system software to
gain critical information for controlling the flash
component. This section describes the devices
CFI-compliant interface that allows the host system
to access Query data.
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E Table 4. Summary of Query Structure Output as a Function of Device and Mode
28F160S5, 28F320S5
Device Type/Mode Word Addressing Byte Addressing

Location Query Data Location Query Data
Hex, ASCII Hex, ASCII
x16 device/ 10h 0051h Q 20h 51h Q
x16 mode 11h 0052h R 21h 00h null
12h 0059h Y 22h 52h R
x16 device/ N/A(1) N/A 20h 51h Q
x8 mode 21h 51h Q
22h 52h R
NOTE:
1. The system must drive the lowest order addresses to access all the devices array data when the device is configured in x8
mode. Therefore, word addressing where lower addresses are not toggled by the system isNot Applicable for x8-
configured devices.
Table 5. Example of Query Structure Output of a x16- and x8-Capable Device

Device Word Addressing: Byte Byte Addressing:
Address Query Data Address Query Data
A16A1 D15D0 A7A0 D7D0
0010h 0051h Q 20h 51h Q
0011h 0052h R 21h 51h Q
0012h 0059h Y 22h 52h R
0013h P_IDLO PrVendor 23h 52h R
0014h P_IDHI ID # 24h 59h Y
0015h PLO PrVendor 25h 59h Y
0016h PHI TblAdr 26h P_IDLO PrVendor
0017h A_IDLO AltVendor 27h P_IDLO ID #
0018h A_IDHI ID # 28h P_IDHI
... ... ... ...
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28F160S5, 28F320S5
4.2.2 QUERY STRUCTURE OVERVIEW

E
The Query command causes the flash component
to display the Common Flash Interface (CFI) Query
structure or database. The structure sub-sections
and address locations are summarized in Table 8.
The following sections describe the Query structure

sub-sections in detail.
Table 6. Query Structure(1)

Offset Sub-Section Name Description
00h Manufacturer Code
01h Device Code
(BA+2)h(2) Block Status Register Block-specific information
04-0Fh Reserved Reserved for vendor-specific information
10h CFI Query Identification String Command set ID and vendor data offset
1Bh System Interface Information Device timing & voltage information
27h Device Geometry Definition Flash device layout
P(3) Primary Intel-specific Extended Query Vendor-defined additional information
table specific to the Primary Vendor Algorithm
NOTES:
1. Refer to Section 4.2.1 and Table 4 for the detailed definition of offset address as a function of device word width and mode.
2. BA = The beginning location of a Block Address (i.e., 08000h is the beginning location of block 1 when the block size is
32 Kword).
3. Offset 15 defines P which points to the Primary Intel-specific Extended Query Table.
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E
4.2.3 BLOCK STATUS REGISTER
28F160S5, 28F320S5
Block Erase Status (BSR.1) allows system software

to determine the success of the last block erase
The Block Status Register indicates whether an operation. BSR.1 can be used just after power-up to
erase operation completed successfully or whether verify that the VCC supply was not accidentally
a given block is locked or can be accessed for flash removed during an erase operation. This bit is only
program/erase operations. reset by issuing another erase operation to the
block. The Block Status Register is accessed from
word address 02h within each block.
Table 7. Block Status Register

Offset Length Description 28F32/160S5
(bytes) x16 Device/Mode
(BA+2)h(1) 01h Block Status Register BA+2: 0000h or
0001h
BSR.0 = Block Lock Status BA+2 (bit 0): 0 or 1
1 = Locked
0 = Unlocked
BSR.1 = Block Erase Status BA+2 (bit 1): 0 or 1
1 = Last erase operation did not complete
successfully
0 = Last erase operation completed successfully
BSR 2-7 Reserved for future use BA+2 (bits 2-7): 0
NOTE:
1. BA = The beginning location of a Block Address (i.e., 008000h is the beginning location of block 1 in word mode.)
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28F160S5, 28F320S5
4.2.4 CFI QUERY IDENTIFICATION STRING

E
The Identification String provides verification that
the component supports the Common Flash
Interface specification. Additionally, it indicates
which version of the spec and which vendor-
specified command set(s) is (are) supported.
Table 8. CFI Identification

(Bytes)
10h 03h Query-Unique ASCII string QRY 10: 0051h
11: 0052h
12: 0059h
13h 02h Primary Vendor Command Set and Control Interface ID Code 13: 0001h
16-bit ID Code for Vendor-Specified Algorithms 14: 0000h
15h 02h Address for Primary Algorithm Extended Query Table 15: 0031h
Offset value = P = 31h 16: 0000h
17h 02h Alternate Vendor Command Set and Control Interface ID Code 17: 0000h
Second Vendor-Specified Algorithm Supported 18: 0000h
Note: 0000h means none exists
19h 02h Address for Secondary Algorithm Extended Query Table 19: 0000h
Note: 0000h means none exists 1A: 0000h
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E 28F160S5, 28F320S5
4.2.5 SYSTEM INTERFACE INFORMATION
The following device information can be useful in

optimizing system interface software.
Table 9. System Interface Information
(bytes)
1Bh 01h VCC Logic Supply Minimum Program/Erase Voltage 1B: 0030h
bits 74 BCD volts
bits 30 BCD 100 mv
1Ch 01h VCC Logic Supply Maximum Program/Erase Voltage 1C: 0055h
bits 74 BCD volts
bits 30 BCD 100 mv
1Dh 01h VPP [Programming] Supply Minimum Program/Erase 1D: 0030h
Voltage
bits 74 HEX volts
bits 30 BCD 100 mv
1Eh 01h VPP [Programming] Supply Maximum Program/Erase 1E: 0055h
Voltage
bits 74 HEX volts
bits 30 BCD 100 mv
1Fh 01h Typical Time-Out per Single Byte/Word Program, 2N - 1F: 0003h
sec
20h 01h Typical Time-Out for Max. Buffer Write, 2 N -sec 20: 0006h
21h 01h Typical Time-Out per Individual Block Erase, 2N m-sec 21: 000Ah
22h 01h Typical Time-Out for Full Chip Erase, 2N m-sec 22: 000Fh
23h 01h Maximum Time-Out for Byte/Word Program, 23: TBD
2N Times Typical
24h 01h Maximum Time-Out for Buffer Write, 2 N Times Typical 24: TBD
25h 01h Maximum Time-Out per Individual Block Erase, 25: TBD
2N Times Typical
26h 01h Maximum Time-Out for Chip Erase, 2N Times Typical 26: TBD
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28F160S5, 28F320S5
4.2.6 DEVICE GEOMETRY DEFINITION

E
This field provides critical details of the flash device
geometry.
Table 10. Device Geometry Definition

(bytes)
27h 01h Device Size = 2N in Number of Bytes 27: 0015h
(16 Mbit)
27: 0016h
(32 Mbit)
28h 02h Flash Device Interface Description 28: 0002h
29: 0000h
value meaning
0002h x8/x16 asynchronous
2Ah 02h Maximum Number of Bytes in Write Buffer = 2 N 2A: 0005h
2B: 0000h
2Ch 01h Number of Erase Block Regions within Device: 2C: 0001h
bits 70 = x = # of Erase Block Regions
2Dh 04h Erase Block Region Information y: 32 Blocks
(16 Mbit)
bits 150 = y, Where y+1 = Number of Erase Blocks of 2D: 001Fh
Identical Size within Region 2E: 0000h
bits 3116 = z, Where the Erase Block(s) within This y: 64 Blocks
Region are (z) 256 Bytes (32 Mbit)
2D: 003Fh
2E: 0000h
z: (64-KB)
2F: 0000h
30: 0001h
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E
4.2.7 INTEL-SPECIFIC EXTENDED QUERY
TABLE
28F160S5, 28F320S5
Certain flash features and commands are optional.

The Intel-Specific Extended Query table specifies
this and other similar types of information.
Table 11. Primary-Vendor Specific Extended Query

Offset(1) Length Description
(bytes) Data
(P)h 03h Primary Extended Query Table 31: 0050h

Unique ASCII String PRI 32: 0052h
33: 0049h
(P+3)h 01h Major Version Number, ASCII 34: 0031h
(P+4)h 01h Minor Version Number, ASCII 35: 0030h
(P+5)h 04h Optional Feature & Command Support 36: 000Fh
37: 0000h
bit 0 Chip Erase Supported (1=yes, 0=no) 38: 0000h
bit 1 Suspend Erase Supported (1=yes, 0=no) 39: 0000h
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bits 531 Reserved for future use; undefined bits
are 0
(P+9)h 01h Supported Functions after Suspend 3A: 0001h
Read Array, Status, and Query are always supported
during suspended Erase or Program operation. This field
defines other operations supported.
bit 0 Program Supported after Erase Suspend
(1=yes, 0=no)
bits 1-7 Reserved for future use; undefined bits are 0
(P+A)h 02h Block Status Register Mask 3B: 0003h
3C: 0000h
Defines which bits in the Block Status Register section of
Query are implemented.
bit 0 Block Status Register Lock-Bit [BSR.0] active
(1=yes, 0=no)
bit 1 Block Erase Status Bit [BSR.1] active
(1=yes, 0=no)
bits 2-15 Reserved for future use; undefined bits
are 0
NOTES:
1. The variable P is a pointer which is defined at offset 15h in Table 8.
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28F160S5, 28F320S5
Table 11. Primary-Vendor Specific Extended Query (Continued)

E
Offset Length Description
(bytes) Data
(P+C)h 01h VCC Logic Supply Optimum Program/Erase voltage 3D: 0050h
(highest performance)
bits 74 BCD value in volts
bits 30 BCD value in 100 mv
(P+D)h 01h VPP [Programming] Supply Optimum Program/Erase 3E: 0050h
voltage
bits 74 HEX value in volts
bits 30 BCD value in 100 mv
(P+E)h reserved Reserved for future use
Table 12. Identifier Codes 4.3 Read Identifier Codes

Command
Code Address(2) Data
Manufacturer Code 000000 B0 The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
Device Code 16 Mbit 000001 D0 command write, read cycles from addresses shown
32 Mbit 000001 D4 in Figure 5 retrieve the manufacturer, device, block
Block Lock Configuration X0002(1) lock configuration, and block erase status codes
(see Table 12 for identifier code values). To
Block is Unlocked DQ0 = 0
terminate the operation, write another valid
Block is Locked DQ0 = 1 command. Like the Read Array command, the
Reserved for Future Use DQ2-7 Read Identifier Codes command functions
Block Erase Status x0002(1) independently of the VPP voltage. Following the
Read Identifier Codes command, the information in
Last erase completed DQ1 = 0
Table 12 can be read.
successfully
Last erase did not DQ1 = 1
complete successfully 4.4 Read Status Register
Reserved for Future Use DQ2-7 Command
NOTES:
1. X selects the specific block lock configuration code. The Status Register may be read to determine
See Figure 5 for the device identifier code memory when programming, block erasure, or lock-bit
map. configuration is complete and whether the operation
2. A0 should be ignored in this address. The lowest order completed successfully. It may be read at any time
address line is A1 in both word and byte mode. by writing the Read Status Register command.
After writing this command, all subsequent read
operations output data from the Status Register
until another valid command is written. The Status
Register contents are latched on the falling edge of
OE#, CE0#, or CE1# whichever occurs last. OE# or
CEX# must toggle to VIH to update the Status
Register latch. The Read Status Register command
functions independently of the VPP voltage.
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E
Following a program, block erase, set block lock-bit,
28F160S5, 28F320S5
analyzing STS in level RY/BY# mode or Status

or clear block lock-bits command sequence, only Register bit SR.7. Toggle OE#, CE0#, or CE1# to
SR.7 is valid until the Write State Machine update the Status Register.
completes or suspends the operation. Device I/O
pins DQ0-6 and DQ8-15 are invalid. When the When the block erase is complete, Status Register
operation completes or suspends (SR.7 = 1), all bit SR.5 should be checked. If a block erase error is
contents of the Status Register are valid when read. detected, the Status Register should be cleared
before system software attempts corrective actions.
The eXtended Status Register (XSR) may be read The CUI remains in read Status Register mode until
to determine Write Buffer availability (see Table 16). a new command is issued.
The XSR may be read at any time by writing the
Write to Buffer command. After writing this This two-step command sequence of set-up
command, all subsequent read operations output followed by execution ensures that block contents
data from the XSR, until another valid command is are not accidentally erased. An invalid Block Erase
written. The contents of the XSR are latched on the command sequence will result in both Status
falling edge of OE# or CEX# whichever occurs last Register bits SR.4 and SR.5 being set to 1. Also,
in the read cycle. Write to buffer command must be reliable block erasure can only occur when
re-issued to update the XSR latch. VCC = VCC1/2 and VPP = VPPH. In the absence of
these voltages, block contents are protected
against erasure. If block erase is attempted while
4.5 Clear Status Register VPP VPPLK, SR.3 and SR.5 will be set to 1.
Command Successful block erase requires that the
corresponding block lock-bit be cleared, or WP# =
Status Register bits SR.5, SR.4, SR.3, and SR.1 VIH. If block erase is attempted when the
are set to 1s by the WSM and can only be reset corresponding block lock-bit is set and WP# = VIL,
by the Clear Status Register command. These bits the block erase will fail and SR.1 and SR.5 will be
indicate various failure conditions (see Table 15). set to 1.
By allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or programming several 4.7 Full Chip Erase Command
bytes/words in sequence) may be performed. The
Status Register may be polled to determine if an The Full Chip Erase command followed by a
error occurred during the sequence. Confirm command erases all unlocked blocks. After
the Confirm command is written, the device erases
To clear the Status Register, the Clear Status all unlocked blocks from block 0 to block 31 (or 63)
Register command is written. It functions sequentially. Block preconditioning, erase, and
independently of the applied VPP voltage. This verify are handled internally by the WSM. After the
command is not functional during block erase or Full Chip Erase command sequence is written to
program suspend modes. the CUI, the device automatically outputs the Status
Register data when read. The CPU can detect full
chip erase completion by polling the STS pin in
4.6 Block Erase Command level RY/BY# mode or Status Register bit SR.7.
Block Erase is executed one block at a time and When the full chip erase is complete, Status
initiated by a two-cycle command. A Block Erase Register bit SR.5 should be checked to see if the
Setup command is written first, followed by a operation completed successfully. If an erase error
Confirm command. This command sequence occurred, the Status Register should be cleared
requires appropriate sequencing and an address before issuing the next command. The CUI remains
within the block to be erased (erase changes all in read Status Register mode until a new command
block data to FFH). Block preconditioning, erase, is issued. If an error is detected while erasing a
and verify are handled internally by the WSM block during a full chip erase operation, the WSM
(invisible to the system). After the two-cycle block skips the remaining cells in that block and proceeds
erase sequence is written, the device automatically to erase the next block. Reading the block valid
outputs Status Register data when read (see Figure status code by issuing the Read Identifier Codes
9). The CPU can detect block erase completion by command or Query command informs the user of
which block(s) failed to erase.
25
ADVANCE INFORMATION

28F160S5, 28F320S5
This two-step command sequence of setup followed

E
If an error occurs while writing, the device will stop
by execution ensures that block contents are not programming, and Status Register bit SR.4 will be
accidentally erased. An invalid Full Chip Erase set to a 1 to indicate a program failure. Any time a
command sequence will result in both Status media failure occurs during a program or an erase
Register bits SR.4 and SR.5 being set to 1. Also, (SR.4 or SR.5 is set), the device will not accept any
reliable full chip erasure can only occur when more Write to Buffer commands. Additionally, if the
VCC = VCC1/2 and VPP = VPPH. In the absence these user attempts to write past an erase block boundary
voltages, block contents are protected against with a Write to Buffer command, the device will
erasure. If full chip erase is attempted while VPP abort programming. This will generate an Invalid
VPPLK, SR.3 and SR.5 will be set to 1. When WP# = Command/Sequence error and Status Register bits
VIL, only unlocked blocks are erased. Full chip SR.5 and SR.4 will be set to 1. To clear SR.4
erase cannot be suspended. and/or SR.5, issue a Clear Status Register
command.
4.8 Write to Buffer Command Reliable buffered programming can only occur
when VCC = VCC1/2 and VPP = VPPH. If programming
To program the flash device via the write buffers, a is attempted while VPP VPPLK, Status Register bits
Write to Buffer command sequence is initiated. A SR.4 and SR.5 will be set to 1. Programming
variable number of bytes or words, up to the buffer attempts with invalid VCC and VPP voltages produce
size, can be written into the buffer and programmed spurious results and should not be attempted.
to the flash device. First, the Write to Buffer setup Finally, successful programming requires that the
command is issued along with the Block Address. corresponding Block Lock-Bit be cleared, or WP# =
At this point, the eXtended Status Register VIH. If a buffered write is attempted when the
information is loaded and XSR.7 reverts to the corresponding Block Lock-Bit is set and WP# = VIL,
buffer available status. If XSR.7 = 0, no write SR.1 and SR.4 will be set to 1.
buffer is available. To retry, continue monitoring
XSR.7 by issuing the Write to Buffer setup
command with the Block Address until XSR.7 = 1. 4.9 Byte/Word Program Command
When XSR.7 transitions to a 1, the buffer is ready
for loading. Byte/Word programming is executed by a two-cycle
command sequence. Byte/Word Program setup
Now a Word/Byte count is issued at an address (standard 40H or alternate 10H) is written, followed
within the block. On the next write, a device start by a second write that specifies the address and
address is given along with the write buffer data. data (latched on the rising edge of WE#). The WSM
For maximum programming performance and lower then takes over, controlling the program and verify
power, align the start address at the beginning of a algorithms internally. After the write sequence is
Write Buffer boundary. Subsequent writes must written, the device automatically outputs Status
supply additional device addresses and data, Register data when read. The CPU can detect the
depending on the count. All subsequent addresses completion of the program event by analyzing STS
must lie within the start address plus the count. in level RY/BY# mode or Status Register bit SR.7.
After the final buffer data is given, a Write Confirm When programming is complete, Status Register bit
command is issued. This initiates the WSM to begin SR.4 should be checked. If a programming error is
copying the buffer data to the flash memory. If a detected, the Status Register should be cleared.
command other than Write Confirm is written to the The internal WSM verify only detects errors for 1s
device, an Invalid Command/Sequence error will that do not successfully program to 0s. The CUI
be generated and Status Register bits SR.5 and remains in read Status Register mode until it
SR.4 will be set to 1. For additional buffer writes, receives another command. Refer to Figure 7 for
issue another Write to Buffer setup command and the Word/Byte Program flowchart.
check XSR.7. The write buffers can be loaded while
the WSM is busy as long as XSR.7 indicates that a Also, Reliable byte/word programming can only
buffer is available. Refer to Figure 6 for the Write to occur when VCC = VCC1/2 and VPP = VPPH. In the
Buffer flowchart. absence of this high voltage, contents are protected
against programming. If a byte/word program is
26
ADVANCE INFORMATION

E
attempted while VPP VPPLK, Status Register bits
28F160S5, 28F320S5
also be set to 1, indicating that the device is in the

SR.4 and SR.3 will be set to 1. Successful erase suspend mode. STS in level RY/BY# mode
byte/word programming requires that the will also transition to VOH. Specification tWHRH2
corresponding block lock-bit be cleared. If a defines the block erase suspend latency.
byte/word program is attempted when the
corresponding block lock-bit is set and WP# = VIL, At this point, a Read Array command can be written
SR.1 and SR.4 will be set to 1. to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
4.10 STS Configuration Command data in other blocks. Using the Program Suspend
command (see Section 4.12), a program operation
The Status (STS) pin can be configured to different can also be suspended. During a program operation
states using the STS pin Configuration command. with block erase suspended, Status Register bit
Once the STS pin has been configured, it remains SR.7 will return to 0 and STS in RY/BY# mode will
in that configuration until another configuration transition to VOL. However, SR.6 will remain 1 to
command is issued or RP# is low. Initially, the STS indicate block erase suspend status.
pin defaults to level RY/BY# operation where STS
low indicates that the state machine is busy. STS The only other valid commands while block erase is
high indicates that the state machine is ready for a suspended are Read Status Register and Block
new operation or suspended. Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
To reconfigure the Status (STS) pin to other modes, will continue the block erase process. Status
the STS pin Configuration command is issued register bits SR.6 and SR.7 will automatically clear
followed by the desired configuration code. The and STS in RY/BY# mode will return to VOL. After
three alternate configurations are all pulse mode for the Erase Resume command is written, the device
use as a system interrupt as described in Table 14. automatically outputs Status Register data when
For these configurations, bit 0 controls Erase read (see Figure 10). VPP must remain at VPPH and
Complete interrupt pulse, and bit 1 controls Write VCC must remain at VCC1/2 (the same VPP and VCC
Complete interrupt pulse. When the device is levels used for block erase) while block erase is
configured in one of the pulse modes, the STS pin suspended. RP# must also remain at VIH (the same
pulses low with a typical pulse width of 250 ns. RP# level used for block erase). Block erase cannot
Supplying the 00h configuration code with the resume until program operations initiated during
Configuration command resets the STS pin to the block erase suspend have completed.
default RY/BY# level mode. Refer to Table 14 for
configuration coding definitions. The Configuration
command may only be given when the device is not 4.12 Program Suspend Command
busy or suspended. Check SR.7 for device status.
An invalid configuration code will result in both The Program Suspend command allows program
Status Register bits SR.4 and SR.5 being set to 1. interruption to read data in other flash memory
locations. Once the programming process starts,
writing the Program Suspend command requests
4.11 Block Erase Suspend that the WSM suspend the program sequence at a
Command predetermined point in the algorithm. The device
continues to output Status Register data when read
The Block Erase Suspend command allows after the Program Suspend command is written.
block-erase interruption to read or program data in Polling Status Register bits SR.7 can determine
another block of memory. Once the block erase when the programming operation has been
process starts, writing the Block Erase Suspend suspended. When SR.7 = 1, SR.2 should also be
command requests that the WSM suspend the set to 1, indicating that the device is in the
block erase sequence at a predetermined point in program suspend mode. STS in level RY/BY#
the algorithm. The device outputs Status Register mode will also transition to VOH. Specification
data when read after the Block Erase Suspend tWHRH1 defines the program suspend latency.
command is written. Polling Status Register bits
SR.7 can determine when the block erase operation At this point, a Read Array command can be written
has been suspended. When SR.7 = 1, SR.6 should to read data from locations other than that which is
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28F160S5, 28F320S5
suspended. The only other valid commands while

E
A successful set block lock-bit operation requires
programming is suspended are Read Status that WP# = VIH. If it is attempted with WP# = VIL,
Register and Program Resume. After a Program the operation will fail and SR.1 and SR.4 will be set
Resume command is written, the WSM will to 1. See Table 13 for write protection alternatives.
continue the programming process. Status Register Refer to Figure 11 for the Set Block Lock-Bit
bits SR.2 and SR.7 will automatically clear and STS flowchart.
in RY/BY# mode will return to VOL. After the
Program Resume command is written, the device
automatically outputs Status Register data when 4.14 Clear Block Lock-Bits
read. VPP must remain at VPPH and VCC must Command
remain at VCC1/2 (the same VPP and VCC levels used
for programming) while in program suspend mode. All set block lock-bits are cleared in parallel via the
RP# must also remain at VIH (the same RP# level Clear Block Lock-Bits command. This command is
used for programming). Refer to Figure 8 for the valid only when WP# = VIH.
Program Suspend/Resume flowchart.
The clear block lock-bits operation is initiated using
a two-cycle command sequence. A Clear Block
4.13 Set Block Lock-Bit Command Lock-Bits setup command is written followed by a
Confirm command. Then, the device automatically
A flexible block locking and unlocking scheme is outputs Status Register data when read (see Figure
enabled via a combination of block lock-bits. The 12). The CPU can detect completion of the clear
block lock-bits gate program and erase operations. block lock-bits event by analyzing STS in level
With WP# = VIH, individual block lock-bits can be RY/BY# mode or Status Register bit SR.7.
set using the Set Block Lock-Bit command.
Set block lock-bit is initiated using a two-cycle This two-step sequence of set-up followed by
command sequence. The Set Block Lock-Bit setup execution ensures that block lock-bits are not
along with appropriate block or device address is accidentally cleared. An invalid Clear Block
written followed by the Set Block Lock-Bit Confirm Lock-Bits command sequence will result in Status
and an address within the block to be locked. The Register bits SR.4 and SR.5 being set to 1. Also,
WSM then controls the set lock-bit algorithm. After a reliable clear block lock-bits operation can only
the sequence is written, the device automatically occur when VCC = VCC1/2 and VPP = VPPH. If a clear
outputs Status Register data when read. The CPU block lock-bits operation is attempted while VPP
can detect the completion of the set lock-bit event VPPLK, SR.3 and SR.5 will be set to 1. In the
by analyzing STS in level RY/BY# mode or Status absence of these voltages, the block lock-bits
Register bit SR.7. contents are protected against alteration. A
successful clear block lock-bits operation requires
When the set lock-bit operation is complete, Status that WP# = VIH.
Register bit SR.4 should be checked. If an error is
detected, the Status Register should be cleared. If a clear block lock-bits operation is aborted due to
The CUI will remain in read Status Register mode VPP or VCC transitioning out of valid range or RP# or
until a new command is issued. WP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
This two-step sequence of setup followed by lock-bits is required to initialize block lock-bit
execution ensures that lock-bits are not accidentally contents to known values.
set. An invalid Set Block Lock-Bit command will
result in Status Register bits SR.4 and SR.5 being When the operation is complete, Status Register bit
set to 1. Also, reliable operations occur only when SR.5 should be checked. If a clear block lock-bit
VCC = VCC1/2 and VPP = VPPH. In the absence these error is detected, the Status Register should be
voltages, lock-bit contents are protected against cleared. The CUI will remain in read Status Register
alteration. mode until another command is issued.
28
ADVANCE INFORMATION

E 28F160S5, 28F320S5
Table 13. Write Protection Alternatives

Block
Operation Lock- WP# Effect
Bit
Program and 0 VIL or VIH Block erase and programming enabled
Block Erase 1 VIL Block is locked. Block erase and programming disabled
VIH Block Lock-Bit override. Block erase and programming enabled
Full Chip Erase 0,1 VIL All unlocked blocks are erased
X VIH Block Lock-Bit override. All blocks are erased
Set or Clear X VIL Set or clear block lock-bit disabled
Block Lock-Bit VIH Set or clear block lock-bit enabled
Table 14. Configuration Coding Definitions

Pulse on Pulse on
Reserved Write Erase
Complete Complete
bits 72 bit 1 bit 0
DQ7DQ2 = Reserved DQ7DQ2 are reserved for future use.

DQ1/DQ0 = STS Pin Configuration Codes default (DQ1/DQ0 = 00) RY/BY#, level mode
00 = default, level mode RY/BY# -----used to control HOLD to a memory controller to
(device ready) indication prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
01 = pulse on Erase complete
configuration 01 ER INT, pulse mode(1)
10 = pulse on Flash Program complete -----used to generate a system interrupt pulse when
11 = pulse on Erase or Program Complete any flash device in an array has completed a block
erase or sequence of queued block erases. Helpful
Configuration Codes 01b, 10b, and 11b are all pulse for reformatting blocks after file system free space
mode such that the STS pin pulses low then high reclamation or cleanup
when the operation indicated by the given
configuration is completed. configuration 10 PR INT, pulse mode(1)
-----used to generate a system interrupt pulse when
Configuration Command Sequences for STS pin any flash device in an array has complete a
configuration (masking bits D7D2 to 00h) are as program operation. Provides highest performance
follows: for servicing continuous buffer write operations.
Default RY/BY# level mode B8h, 00h
ER INT (Erase Interrupt): B8h, 01h configuration ER/PR INT, pulse mode(1)
Pulse-on-Erase Complete -----used to generate system interrupts to trigger
PR INT (Program Interrupt): B8h, 02h servicing of flash arrays when either erase or flash
Pulse-on-Flash-Program Complete program operations are completed when a common
ER/PR INT (Erase or Program Interrupt): B8h, 03h interrupt service routine is desired.
Pulse-on-Erase or Program Complete
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
29
ADVANCE INFORMATION

28F160S5, 28F320S5
Table 15. Status Register Definition

E
WSMS ESS ECLBS BWSLBS VPPS BWSS DPS R
7 6 5 4 3 2 1 0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS Check STS in RY/BY# mode or SR.7 to determine
1 = Ready block erase, programming, or lock-bit configuration
0 = Busy completion. SR.6-0 are invalid while SR.7 = 0.
SR.6 = ERASE SUSPEND STATUS
1 = Block erase suspended
0 = Block erase in progress/completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS If both SR.5 and SR.4 are 1s after a block erase
1 = Error in block erasure or clear lock-bits or lock-bit configuration attempt, an improper
0 = Successful block erase or clear lock-bits command sequence was entered.
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in program or block lock-bit
0 = Successful program or set block lock-bit
SR.3 = VPP STATUS SR.3 does not provide a continuous indication of
1 = VPP low detect, operation abort VPP level. The WSM interrogates and indicates the
0 = VPP OK VPP level only after a block erase, program, or lock-
bit configuration operation. SR.3 reports accurate
feedback only when VPP = VPPH.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program suspended
0 = Program in progress/completed
SR.1 = DEVICE PROTECT STATUS SR.1 does not provide a continuous indication of
1 = Block Lock-Bit and/or block lock-bit values. The WSM interrogates the
RP# lock detected, operation abort block lock-bit, and WP# only after a block erase,
0 = Unlock program, or lock-bit configuration operation. It
informs the system, depending on the attempted
operation, if the block lock-bit is set.
SR.0 = RESERVED FOR FUTURE SR.0 is reserved for future use and should be
ENHANCEMENTS masked when polling the Status Register.
Table 16. Extended Status Register Definition

WBS R R R R R R R
7 6 5 4 3 2 1 0
NOTES:
XSR.7 = WRITE BUFFER STATUS After a Write to buffer command, XSR.7 indicates
1 = Write to buffer available that another Write to buffer command is possible.
0 = Write to buffer not available
XSR.6 = RESERVED FOR FUTURE SR.60 are reserved for future use and should be
ENHANCEMENTS masked when polling the status register
30
ADVANCE INFORMATION

E Start Bus Command
28F160S5, 28F320S5
Comments
Operation
Write Write to Data = E8h
Set Time-Out Buffer Addr = Block Address
Read XSR.7=valid
Addr = X
Issue Write Command No Standby Check XSR.7
E8H, Block Address 1 = Write buffer available
0 = Write buffer not available
Read Extended Write Data = N = word/byte count
Status Register (Note 1, 2) N = 0 corresponds to count = 1
Addr = Block Address
Write Data = write buffer data
0 Write Buffer (Note 3, 4) Addr = device start address
XSR.7 =
Time-Out? Write Data = write buffer data
(Note 5, 6) Addr = device address
1 Write Buffer Data = D0h
Write Word or Byte write to flash Addr = X
Count, Block Address confirm
Read Status Register data
Write Buffer Data, CE# & OE# low updates SR
Start Address Addr = X
Standby Check SR.7
1 = WSM ready
X=0 0 = WSM busy
1. Byte- or word-count values on DQ0-7 are loaded into
the Count register.
Yes
2. The device now outputs the Status Register when
X=N read (XSR is no longer available).
3. Write Buffer contents will be programmed at the
device start address or destination flash address.
No 4. Align the start address on a Write Buffer boundary for
Yes
maximum programming performance.
Abort Buffer 5. The device aborts the Write to Buffer command if the
Yes Write to Another current address is outside of the original block
Write
Block Address address.
Command?
6. The Status Register indicates an improper command
Yes Buffer Write to sequence if the Write to Buffer command is aborted.
No Flash Aborted Follow this with a Clear Status Register command.
Write Next Buffer Data,
Device Address Full status check can be done after all Erase and
Write sequences complete. Write FFh after the last
operation to reset the device to Read Array mode.
X=X+1
Buffer Write to Flash

Confirm D0H
Another
Issue Read
Buffer
Status Command
Write?
No
Read
Status Register No
Suspend
Write Loop
0 Suspend Yes
SR.7 =
Write?
1
Full Status
Check if Desired
Buffer Write to
Flash Complete
0608_07
Figure 6. Write to Buffer Flowchart
31
ADVANCE INFORMATION

28F160S5, 28F320S5 E
0608_08
Figure 7. Single Byte/Word Program Flowchart
32
ADVANCE INFORMATION

E 28F160S5, 28F320S5
0608_09
Figure 8. Program Suspend/Resume Flowchart
33
ADVANCE INFORMATION

28F160S5, 28F320S5
Start
Bus Command
E
Comments
Operation
Write Erase Block Data = 28h or 20h
Addr = Block Address
Device
Supports Read XSR.7=valid
Queuing Addr = X
Yes
Standby Check XSR.7
1 = Erase queue available
Set Time-Out 0 = No Erase queue available
Write Erase Block Data = 28H
Issue Block Queue Addr = Block Address
Erase Command 28H, Read SR.7=valid; SR.6-0=X
With the device enabled,
Block Address
OE# low updates SR
No Read Extended Status Addr = X
Standby Check XSR.7
Register
1 = Erase queue available
0 = No Erase queue available
Write Erase Data = D0H
Is Queue
Erase Block 0=No (Note 1) Confirm Addr = X
Available? Read Status Register data
Time-Out? No
XSR.7= With the device enabled,
(Include this section for compatibility
OE# low updates SR

with future SCS-compliant devices)
1=Yes Addr = X
Standby Check SR.7
Queued Erase Section
Another 1 = WSM ready

Block 0 = WSM busy
Yes
Erase? 1. The Erase Confirm byte must follow Erase Setup when
Yes the Erase Queue status (XSR.7)=0.
Yes
Issue Erase Command Full status check can be done after all Erase and Write
28H Block Address sequences complete. Write FFh after the last
1=No operation to reset the device to Read Array mode.
Read Extended
No Status Register
Is Queue Issue Single Block

Full? Erase Command 20H,
XSR.7= Block Address
0=Yes
Write Confirm D0H Write Confirm D0H
Block Address Block Address
Another
Issue Read
Block
Status Command
Erase?
No
Read
Status Register No
Suspend
Erase Loop
0 Suspend Yes
SR.7 =
Erase
1
Full Status
Check if Desired
Erase Flash
Block(s) Complete
0609_10
Figure 9. Block Erase Flowchart
34
ADVANCE INFORMATION

E 28F160S5, 28F320S5
Start Bus Command Comments

Operation
Write Erase Data = B0H

Write B0H Suspend Addr = X
Status Register Data

Read
Read Addr = X
Status Register
Check SR.7
Standby 1 = WSM Ready
0 0 = WSM Busy
SR.7 =
Check SR.6
Standby
1 = Block Erase Suspended
1 0 = Block Erase Completed
Write Erase Data = D0H

0 Resume Addr = X
SR.6 = Block Erase Completed
Read Read or Write

Write?
Read Array Write

Data No Loop
Done?
Yes
Write D0H Write FFH
Block Erase Resumed Read Array Data
Figure 10. Block Erase Suspend/Resume Flowchart
35
ADVANCE INFORMATION

28F160S5, 28F320S5
Start Bus
E
Command Comments
Operation
Set Data = 60H

Write 60H, Write Block/Master Addr = Block Address (Block),
Block/Device Address
Lock-Bit Setup Device Address (Master)
Data = 01H (Block),

Set
Write 01H/F1H, Write F1H (Master)
Block or Master
Block/Device Address Addr = Block Address (Block),
Lock-Bit Confirm
Device Address (Master)
Read Read Status Register Data

Status Register
Check SR.7
Standby
0 1 = WSM Ready
SR.7 = 0 = WSM Busy
Repeat for subsequent lock-bit set operations.

Full status check can be done after each lock-bit set operation
1
or after a sequence of lock-bit set operations.
Full Status Write FFH after the last lock-bit set operation to place device in
Check if Desired read array mode.
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus

Command Comments
Data (See Above) Operation
Check SR.3
Standby 1 = Programming Voltage Error
1
SR.3 = Voltage Range Error Detect
Check SR.1
0 1 = Device Protect Detect
RST# = VIH
Standby (Set Master Lock-Bit Operation)
1
SR.1 = Device Protect Error RST# = VIH , Master Lock-Bit Is Set
(Set Block Lock-Bit Operation)
0 Check SR.4,5
Standby
Both 1 = Command Sequence Error
1 Command Sequence
SR.4,5 =
Error Check SR.4
Standby
1 = Set Lock-Bit Error
0
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
1 Register command in cases where multiple lock-bits are set
SR.4 = Set Lock-Bit Error before full status is checked.
If error is detected, clear the Status Register before attempting retry
0 or other error recovery.
Set Lock-Bit Successful
Figure 11. Set Block Lock-Bit Flowchart
36
ADVANCE INFORMATION

E Start Bus
28F160S5, 28F320S5
Command Comments
Operation
Clear Block Data = 60H

Write
Write 60H Lock-Bits Setup Addr = X
Clear Block Data = D0H

Write Addr = X
Lock-Bits Confirm
Write D0H
Read Status Register Data

Read Status
Register
Check SR.7
Standby 1 = WSM Ready
0 0 = WSM Busy
SR.7 =
Write FFH after the Clear Block Lock-Bits operation to place device
to read array mode.
1
Full Status
Check if Desired
Clear Block Lock-Bits

Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus

Command Comments
Data (See Above) Operation
Standby Check SR.3

1 = Programming Voltage Error
1 Detect
SR.3 = Voltage Range Error
Check SR.1
Standby 1 = Device Protect Detect
0
RST# = VIH , Master Lock-Bit Is Set
1 Check SR.4,5
SR.1= Device Protect Error
Standby Both 1 = Command Sequence Error
0
Check SR.5
Standby
1 Command Sequence 1 = Clear Block Lock-Bits Error
SR.4,5 = Error
0 SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status
Register command.
If error is detected, clear the Status Register before attempting
1 Clear Block Lock-Bits retry or other error recovery.
SR.5 = Error
Clear Block Lock-Bits

Successful
Figure 12. Clear Block Lock-Bits Flowchart
37
ADVANCE INFORMATION

28F160S5, 28F320S5 E
5.0 DESIGN CONSIDERATIONS Additionally, for every eight devices, a 4.7 F
electrolytic capacitor should be placed at the arrays
power supply connection between VCC and GND.
5.1 Three-Line Output Control The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
Intel provides three control inputs to accommodate
multiple memory connections: CEX# (CE0#, CE1#),
OE#, and RP#. Three-line control provides for: 5.4 VPP Trace on Printed Circuit
a. Lowest possible memory power dissipation;
Boards
b. Data bus contention avoidance. Updating target-system resident flash memories
requires that the printed circuit board designer pay
To use these control inputs efficiently, an address attention to VPP power supply traces. The VPP pin
decoder should enable CEx# while OE# should be supplies the memory cell current for programming
connected to all memory devices and the systems and block erasing. Use similar trace widths and
READ# control line. This assures that only selected layout considerations given to the VCC power bus.
memory devices have active outputs, while de- Adequate VPP supply traces and decoupling will
selected memory devices are in standby mode. decrease VPP voltage spikes and overshoots.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD 5.5 VCC, VPP, RP# Transitions
should also toggle during system reset.
Block erase, program, and lock-bit configuration are
not guaranteed if RP# VIH, or if VPP or VCC fall
5.2 STS and WSM Polling outside of a valid voltage range (VCC1/2 and VPPH).
If VPP error is detected, Status Register bit SR.3
STS is an open drain output that should be and SR.4 or SR.5 are set to 1. If RP# transitions
connected to VCC by a pull-up resistor to provide a to VIL during block erase, program, or lock-bit
hardware form of detecting block erase, program, configuration, STS in level RY/BY# mode will
and lock-bit configuration completion. In default remain low until the reset operation is complete.
mode, it transitions low during execution of these Then, the operation will abort and the device will
commands and returns to VOH when the WSM has enter deep power-down. Because the aborted
finished executing the internal algorithm. For operation may leave data partially altered, the
alternate STS pin configurations, see Section 4.10. command sequence must be repeated after normal
STS can be connected to an interrupt input of the operation is restored.
system CPU or controller. It is active at all times.
STS, in default mode, is also VOH when the device
is in block erase suspend (with programming 5.6 Power-Up/Down Protection
inactive) or in reset/power-down mode.
The device offers protection against accidental
block erase, programming, or lock-bit configuration
5.3 Power Supply Decoupling during power transitions.
Flash memory power switching characteristics A system designer must guard against spurious
require careful device decoupling. Standby current writes for VCC voltages above VLKO when VPP is
levels, active current levels and transient peaks active. Since both WE# and CEX# must be low for a
produced by falling and rising edges of CEX# and command write, driving either input signal to VIH will
OE# are areas of interest. Two-line control and inhibit writes. The CUIs two-step command
proper decoupling capacitor selection will suppress sequence architecture provides an added level of
transient voltage peaks. Each device should have a protection against data alteration.
0.1 F ceramic capacitor connected between its
VCC and GND and VPP and GND. These high- In-system block lock and unlock renders additional
frequency, low-inductance capacitors should be protection during power-up by prohibiting block
placed as close as possible to package leads. erase and program operations. RP# = VIL disables
the device regardless of its control inputs states.
38
ADVANCE INFORMATION

E
6.0 ELECTRICAL SPECIFICATIONS
28F160S5, 28F320S5
NOTICE: This datasheet contains information on products

in the design phase of development. Do not finalize a
design with this information. Revised information will be
6.1 Absolute Maximum Ratings published when the product is available. Verify with your
local Intel Sales office that you have the latest datasheet
before finalizing a design
Temperature under Bias ................ 40C to +85C
Storage Temperature................... 65C to +125C *WARNING: Stressing the device beyond the Absolute
Voltage On Any Pin Maximum Ratings may cause permanent damage. These
(except VCC and VPP ) are stress ratings only. Operation beyond the Operating
.................................... 0.5V to + VCC +0.5V(1) Conditions is not recommended and extended exposure
beyond the Operating Conditions may affect device
VCC Supply Voltage ............ 0.2V to + VCC+0.5V(1) reliability.
VPP Update Voltage during NOTES:
Block Erase, Flash Write, and
1. All specified voltages are with respect to GND. Minimum
Lock-Bit Configuration ........... 0.2V to +7.0V(2)
DC voltage is 0.5V on input/output pins and 0.2V on
Output Short Circuit Current.....................100 mA(3) VCC and VPP pins. During transitions, this level may
undershoot to 2.0V for periods <20 ns. Maximum DC
voltage on input/output pins and VCC is VCC +0.5V
which, during transitions, may overshoot to VCC +2.0V
for periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +7.0V
for periods <20 ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
4. Operating temperature is for extended product defined
by this specification.
6.2 Operating Conditions

Table 17. Temperature and VCC Operating Conditions (1)
Symbol Parameter Notes Min Max Unit Test Condition
TA Operating Temperature -40 +85 C Ambient Temperature
VCC1 VCC Supply Voltage (5V 5%) 4.75 5.25 V
VCC2 VCC Supply Voltage (5V 10%) 4.50 5.50 V
NOTES:
1. Device operations in the VCC voltage ranges not covered in the table produce spurious results and should not be
attempted.
39
ADVANCE INFORMATION

28F160S5, 28F320S5
6.2.1 CAPACITANCE
E
Table 18. Capacitance(1), TA = +25C, f = 1 MHz
Symbol Parameter Typ Max Unit Condition
CIN Input Capacitance 6 8 pF VIN = 0.0V
COUT Output Capacitance 8 12 pF VOUT = 0.0V
NOTE:
1. Sampled, not 100% tested.
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS

3.0
INPUT 1.5 TEST POINTS 1.5 OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 13. Transient Input/Output Reference Waveform for VCC = 5.0V 5%

(High Speed Testing Configuration)
2.4
2.0 2.0
INPUT TEST POINTS OUTPUT
0.8 0.8
0.45
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC = 5.0V 10%
(Standard Testing Configuration)
1.3V Test Configuration Capacitance Loading Value

1N914 Test Configuration CL (pF)
VCC = 5.0V 5% 30
R L = 3.3 k
VCC = 5.0V 10% 100
DEVICE
UNDER OUT
TEST
CL
C L Includes Jig
Capacitance
Figure 15. Transient Equivalent Testing

Load Circuit
40
ADVANCE INFORMATION

E
6.2.3 DC CHARACTERISTICS
28F160S5, 28F320S5
Table 19. DC Characteristics, TA = 40oC to +85oC

Sym Parameter Notes Typ Max Unit Conditions
ILI Input Load Current 1 1 A VCC = VCC Max
VIN = VCC or GND
ILO Output Leakage Current 1 10 A VCC = VCC Max
Vout = VCC or GND
ICCS VCC Standby Current 1,3,6 25 100 A CMOS Inputs
VCC = VCC Max
CEX# = RP# = VCC 0.2V
0.4 2 mA TTL Inputs
VCC = VCC Max
CEX# = RP# = VIH
ICCD VCC Deep Power-Down Current 1 20 A RP# = GND 0.2V
IOUT (RY/BY#) = 0 mA
ICCR VCC Read Current 1,5,6 50 mA CMOS Inputs
VCC = VCC Max
CEX# = GND
f = 8 MHz, IOUT = 0 mA
65 mA TTL Inputs
VCC = VCC Max
CEX# = VIL
f = 8 MHz, IOUT = 0 mA
ICCW VCC Programming and Set Lock- 1,7 35 mA VPP = VPPH
Bit Current
ICCE VCC Block Erase or Clear Block 1,7 30 mA VPP = VPPH
Lock-Bits Current
ICCWS VCC Program Suspend or Block 1,2 10 mA CEX# = VIH
ICCES Erase Suspend Current
IPPS VPP Standby or VPP Read 1 2 15 A VPP VCC
IPPR Current
10 200 A VPP VCC

IPPD VPP Deep Power-Down Current 1 0.1 5 A RP# = GND 0.2V
IPPW VPP Program or Set Lock-Bit 1,7 80 mA VPP = VPPH
Current
IPPE VPP Block Erase or Clear Block 1,7 40 mA VPP = VPPH
Lock-Bits Current
IPPWS VPP Program Suspend or Block 1 10 200 A VPP = VPPH
IPPES Erase Suspend Current
41
ADVANCE INFORMATION

28F160S5, 28F320S5
Table 19. DC Characteristics (Continued)

E
Sym Parameter Notes Min Max Unit Conditions
VIL Input Low Voltage 7 0.5 0.8 V
VIH Input High Voltage 7 2.0 VCC + 0.5 V
VOL Output Low Voltage 3,7 0.45 V VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage (TTL) 3,7 2.4 V VCC = VCC Min
IOH = 2.5 mA
VOH2 Output High Voltage (CMOS) 3,7 0.85 V VCC = VCC Min
VCC IOH = 2.5 mA
VCC 0.4 V VCC = VCC Min
IOH = 100 A
VPPLK VPP Lockout Voltage 4,7 1.5 V
VPPH VPP Voltage 4 4.5 5.5 V
VLKO VCC Lockout Voltage 8 2.0 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC voltage and TA = +25C. These currents are
valid for all product versions (packages and speeds).
2. ICCWS and ICCES are specified with the device de-selected. If read or programmed while in erase suspend mode, the
devices current is the sum of ICCWS or ICCES and ICCR or ICCW.
3. Includes STS in level RY/BY# mode.
4. Block erase, program, and lock-bit configurations are inhibited when VPP VPPLK, and not guaranteed in the range between
VPPLK (max) and VPPH (min), and above VPPH (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA at 5V VCC static operation.
6. CMOS inputs are either VCC 0.2V or GND 0.2V. TTL inputs are either VIL or VIH.
8. With VCC VLKO flash memory writes are inhibited.
42
ADVANCE INFORMATION

E
6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS
28F160S5, 28F320S5
Table 20. AC Read Characteristics (1,5), TA = 40oC to +85oC

Versions(4) 5V 5% VCC -70/-90
(All units in ns unless otherwise noted) 5V 10% VCC -80/-100 -100/-110
# Sym Parameter Notes Min Max Min Max Min Max
R1 tAVAV Read/Write Cycle Time 16 Mbit 1 70 80 100
32 Mbit 1 90 100 110
R2 tAVQV Address to Output Delay 16 Mbit 1 70 80 100
32 Mbit 1 90 100 110
R3 tELQV CEX# to Output Delay 16 Mbit 2 70 80 100
32 Mbit 2 90 100 110
R4 tPHQV RP# High to Output Delay 400 400 400
R5 tGLQV OE# to Output Delay 2 30 35 40
R6 tELQX CEX# to Output in Low Z 3 0 0 0
R7 tEHQZ CEX# High to Output in High Z 3 25 30 35
R8 tGLQX OE# to Output in Low Z 3 0 0 0
R9 tGHQZ OE# High to Output in High Z 3 10 10 15
R10 tOH Output Hold from Address, CEX#, or 3 0 0 0

OE# Change, Whichever Occurs First
R11 tELFL CEX# Low to BYTE# High or Low 3 5 5 5

tELFH
R12 tFLQV BYTE# to Output Delay 16 Mbit 3 70 80 100

tFHQV
32 Mbit 3 90 100 110
R13 tFLQZ BYTE# to Output in High Z 3 25 30 30

NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CEX# without impact on tELQV.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Figures 13 through 15 for testing characteristics.
43
ADVANCE INFORMATION

28F160S5, 28F320S5 E
Note: CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
0608_17
Figure 16. AC Waveform for Read Operations
44
ADVANCE INFORMATION

E
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS
28F160S5, 28F320S5
Table 21. Write Operations(1,6), TA = 40C to +85C

Versions(6) 5V 5% Valid for All
5V 10% VCC Speeds
# Sym Parameter Notes Min Max Unit
W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX# ) Going Low 2 1 s

W2 tELWL CEX# Setup to WE# Going Low 10 ns
(tWLEL) (WE# Setup to CEX# Going Low) 0 ns

W3 tWLWH WE# Pulse Width 40 ns
(tELEH) (CEX# Pulse Width) 50 ns

W4 tDVWH (tDVEH) Data Setup to WE# (CEX# ) Going High 3 40 ns
W5 tAVWH (tAVEH) Address Setup to WE# (CEX# ) Going High 3 40 ns
W6 tWHEH CEX# Hold from WE# High 10 ns
(tEHWH) (WE# Hold from CEX# High) 0 ns

W7 tWHDX (tEHDX) Data Hold from WE# (CEX# ) High 5 ns
W8 tWHAX (tEHAX) Address Hold from WE# (CEX# ) High 5 ns
W9 tWHWL WE# Pulse Width High 30 ns
(tEHEL) (CEX# Pulse Width High) 25 ns

W10 tSHWH (tSHEH) WP# VIH Setup to WE# (CEX# ) Going High 100 ns
W11 tVPWH (tVPEH) VPP Setup to WE# (CEX# ) Going High 2 100 ns
W12 tWHGL (tEHGL) Write Recovery before Read 0 ns
W13 tWHRL (tEHRL) WE# High to STS in RY/BY# Low 90 ns
W14 tQVSL WP# VIH Hold from Valid SRD 2,4 0 ns
W15 tQVVL VPP Hold from Valid SRD, STS in RY/BY# High 2,4 0 ns
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
3. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.
4. VPP should be at VPPH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Figures 13 through 15 for testing characteristics.
45
ADVANCE INFORMATION

28F160S5, 28F320S5 E
NOTES:
A. VCC power-up and standby.
B. Write block erase or program setup.
C. Write block erase confirm or valid address and data..
D. Automated erase or program delay.
E. Read Status Register data.
F. Write Read Array command.
CEX# is the latter of CE0# and CE1# low or the first of CE0# or CE1# high.
0608_18
Figure 17. AC Waveform for Write Operations
46
ADVANCE INFORMATION

E
6.2.6 RESET OPERATIONS
28F160S5, 28F320S5
Figure 18. AC Waveform for Reset Operation
Table 22. Reset AC Specifications(1)

# Sym Parameter Notes Min Max Unit
P1 tPLPH RP# Pulse Low Time 100 ns
(If RP# is tied to V CC, this specification is not applicable)
P2 tPLRH RP# Low to Reset during Block Erase, Program, or Lock- 2,3 12 s
Bit Configuration
P3 t5VPH VCC at 4.5V to RP# High 50 s
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete
within tPLPH.
3. A reset time, tPHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.
47
ADVANCE INFORMATION

28F160S5, 28F320S5
6.2.7 ERASE, PROGRAM, AND LOCK-BIT CONFIGURATION PERFORMANCE

E
Table 23. Erase/Write/Lock Performance(3,4)
5V 5%,
5V 10% VCC
Version 5V VPP
# Sym Parameter Notes Typ(1) Max Units
W16 Byte/word program time (using write buffer) 5 2 TBD s
W16 tWHQV1 Per byte program time (without write buffer) 2 9.24 TBD s
tEHQV1
W16 tWHQV1 Per word program time (without write buffer) 2 9.24 TBD s
tEHQV1
W16 Block program time (byte mode) 2 0.5 TBD sec
W16 Block program time (word mode) 2 0.38 TBD sec
W16 Block program time (using write buffer) 2 0.13 TBD sec
W16 tWHQV2 Block erase time 2 0.34 TBD sec
tEHQV2
W16 Full chip erase time 16 Mbit 10.7 sec
32 Mbit 21.4 sec
W16 tWHQV3 Set Lock-Bit time 2 9.24 TBD s

tEHQV3
W16 tWHQV4 Clear block lock-bits time 2 0.34 TBD sec
tEHQV4
W16 tWHRH1 Program suspend latency time to read 5.6 7 s
tEHRH1
W16 tWHRH2 Erase suspend latency time to read 9.4 13.1 s
tEHRH2
NOTES:
1. Typical values measured at TA = +25C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled but not 100% tested.
5. Uses whole buffer.
48
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E APPENDIX A
28F160S5, 28F320S5
DEVICE NOMENCLATURE AND ORDERING

INFORMATION
Product line designator for all Intel Flash products
T E 2 8 F 1 6 0 S5 - 7 0
Package Access Speed (ns)
DT = Extended Temp. 70 ns (5V, 30 pF), 80 ns (5V)
56-Lead SSOP
TE = Extended Temp.
56-Lead TSOP Device Type
Device Density 5 = 5V VCC, 5V VPP
160 = 16-Mbit
320 = 32-Mbit Product Family
S = FlashFile Memory
0609_20
Order Code by Density Valid Operational Combinations

10% VCC 5% VCC
16 Mb 32 Mb 100 pF load 30 pF load
(16 Mb / 32 Mb) (16 Mb / 32 Mb)
E28F160S5-70 E28F320S5-90 -80 / -100 -70 / -90
E28F160S5-100 E28F320S5-110 -100 / -110
DA28F160S5-70 DA28F320S5-90 -80 / -100 -70 / -100
DA28F160S5-100 DA28F320S5-110 -100 / -110
49
ADVANCE INFORMATION

28F160S5, 28F320S5
APPENDIX B
E
ADDITIONAL INFORMATION(1,2)
Order Number Document/Tool
290608 Word-Wide FlashFileMemory Family 28F160S3, 28F320S3 Datasheet
292203 AP-645 28F160S3/S5 Compatibility with 28F016SA/SV
292204 AP-646 Common Flash Interface and Command Sets
290528 28F016SV 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile Memory Datasheet
290489 28F016SA 16-Mb (1Mbit x 16, 2Mbit x 8) FlashFile Memory Datasheet
297372 16-Mbit Flash Product Family Users Manual
292123 AP-374 Flash Memory Write Protection Techniques
292144 AP-393 28F016SV Compatibility with 28F016SA
292159 AP-607 Multi-Site Layout Planning with Intels FlashFile Components,

Including ROM Capability
292163 AP-610 Flash Memory In-System Code and Data Update Techniques
Contact Intel/Distribution CFI - Common Flash Interface Reference Code

Sales Office
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intels World Wide Web home page at http://www.intel.com for technical documentation and tools.
50
ADVANCE INFORMATION

Word-Wide Flashfile™ Memory Family 28F160S5, 28F320S5: Advance Information

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E WORD-WIDE

FlashFile MEMORY FAMILY

n Two 32-Byte Write Buffers n Cross-Compatible Command Support

June 1997 Order Number: 290609-001

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COPYRIGHT INTEL CORPORATION, 1997 CG-041493

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3.0 BUS OPERATION .........................................11 5.0 DESIGN CONSIDERATIONS ........................38

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Specifically designed for 5V systems, the

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Output Buffer Input Buffer

16-Mbit: A0- A20 Y-Decoder Y-Gating STS

Figure 1. 28F320S5 and 28F160S5 Block Diagram

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Sym Type Name and Function

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3/5# NC 1 56 WP# WP#

Highlights pinout changes.

Figure 2. 28F160S5 TSOP 56-Lead Pinout

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Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout

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Read Array, Status Register, query, and identifier

Figure 4. Memory Map

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3.6 Read Identifier Codes 3.7 Write

The CUI does not occupy an addressable

4.0 COMMAND DEFINITIONS

Device operations are selected by writing specific

Figure 5. Device Identifier Code Memory Map

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Table 3. Word-Wide FlashFile Memory Command Set Definitions(13)

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1. Bus operations are defined in.Table 2.

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Device Type/Mode Word Addressing Byte Addressing

Table 5. Example of Query Structure Output of a x16- and x8-Capable Device

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4.2.2 QUERY STRUCTURE OVERVIEW

The following sections describe the Query structure

Table 6. Query Structure(1)

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Block Erase Status (BSR.1) allows system software

Table 7. Block Status Register

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4.2.4 CFI QUERY IDENTIFICATION STRING

Table 8. CFI Identification

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4.2.5 SYSTEM INTERFACE INFORMATION

The following device information can be useful in

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4.2.6 DEVICE GEOMETRY DEFINITION

Table 10. Device Geometry Definition

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